fundamentals of digital signal processing
DESCRIPTION
Fundamentals of Digital Signal Processing. יהודה אפק, נתן אינטרטור אוניברסיטת תל אביב. What is DSP?. Converting a continuously changing waveform (analog) into a series of discrete levels (digital) and then performing Digital Computations. What is DSP?. - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/1.jpg)
Fundamentals of Digital Signal Processing
יהודה אפק, נתן אינטרטור
אוניברסיטת תל אביב
![Page 2: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/2.jpg)
What is DSP?Converting a continuously changing waveform (analog) into a series of discrete levels (digital) and then performing Digital Computations
![Page 3: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/3.jpg)
What is DSP?
The analog waveform is sliced into equal segments and the waveform amplitude is measured in the middle of each segment
The collection of measurements make up the digital representation of the waveform
![Page 4: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/4.jpg)
A/D Parameters
1 .Sampling Frequency – The rate at which we convert the analog data into digital
2 .Dynamic range – The ratio between the highest to lowest value (which is not zero)
![Page 5: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/5.jpg)
What is DSP?0
0.22 0.
44 0.64 0.
82 0.98 1.
11 1.2 1.24
1.27
1.24
1.2
1.11
0.98
0.82
0.64
0.44
0.22
0-0
.22
-0.4
4-0
.64
-0.8
2-0
.98
-1.1
1-1
.2-1
.26
-1.2
8-1
.26
-1.2
-1.1
1-0
.98
-0.8
2 -0.6
4 -0.4
4 -0.2
20
-2
-1.5
-1
-0.5
0
0.5
1
1.5
21 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37
![Page 6: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/6.jpg)
Converting Analog into Digital
Electronically
The device that does the conversion is called an Analog to Digital Converter (ADC)
There is a device that converts digital to analog that is called a Digital to Analog Converter (DAC)
![Page 7: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/7.jpg)
Converting Analog into Digital
ElectronicallyThe simplest form of ADC uses a resistance ladder to switch in the appropriate number of resistors in series to create the desired voltage that is compared to the input (unknown) voltage. Each SW includes a resistor.
V-7
V-6
V-low
V-1
V-2
V-3
V-4
V-5
V-high
SW-8
SW-7
SW-6
SW-5
SW-4
SW-3
SW-2
SW-1
Output
![Page 8: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/8.jpg)
Converting Analog into Digital
ElectronicallyThe output of the resistance ladder is compared to the analog voltage in a comparator
When there is a match, the digital equivalent (switch configuration) is captured
Analog Voltage
ResistanceLadder Voltage
ComparatorOutput Higher
EqualLower
![Page 9: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/9.jpg)
Analog to Digital (Ladder Comparison)
![Page 10: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/10.jpg)
Converting Analog into DigitalComputationally
The binary search is a mathematical technique that uses an initial guess, the expected high, and the expected low in a simple computation to refine a new guessThe computation continues until the refined guess matches the actual value (or until the maximum number of calculations is reached)Faster way, start with previous value as the initial guess
![Page 11: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/11.jpg)
VHDL: A QUICK PRIMER
![Page 12: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/12.jpg)
Let’s Start Simple• Support different description levels
– Structural (specifying interconnections of the gates), – Dataflow (specifying logic equations), and – Behavioral (specifying behavior)
![Page 13: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/13.jpg)
VHDL Description of Combinational Networks
![Page 14: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/14.jpg)
Entity-Architecture Pair
entity name port names port mode (direction)port type
reserved words
punctuation
![Page 15: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/15.jpg)
VHDL Program Structure
![Page 16: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/16.jpg)
4-bit Adder
![Page 17: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/17.jpg)
4-bit Adder (cont’d)
![Page 18: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/18.jpg)
4-bit Adder - Simulation
![Page 19: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/19.jpg)
Modeling Flip-Flops Using VHDL Processes
•Whenever one of the signals in the sensitivity list changes, the sequential statements are executed
in sequence one time
General form of process
![Page 20: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/20.jpg)
D Flip-flop Model
Bit values are enclosed in single quotes
![Page 21: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/21.jpg)
JK Flip-Flop Model
![Page 22: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/22.jpg)
JK Flip-Flop Model
![Page 23: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/23.jpg)
Using Nested IFs and ELSEIFs
![Page 24: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/24.jpg)
VHDL Models for a MUX
Sel represents the integerequivalent of a 2-bit binary number with bits A and B
If a MUX model is used inside a process, the MUX can be modeled using a CASE statement(cannot use a concurrent statement):
![Page 25: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/25.jpg)
MUX Models (1)
library IEEE;use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;entity SELECTOR is
port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( 3 downto 0); Y : out std_logic;)
end SELECTOR;
architecture RTL1 of SELECTOR isbegin
p0 : process (A, SEL) begin
if (SEL = "0000") then Y <= A(0); elsif (SEL = "0001") then Y <= A(1); elsif (SEL = "0010") then Y <= A(2); elsif (SEL = "0011") then Y <= A(3); elsif (SEL = "0100") then Y <= A(4); elsif (SEL = "0101") then Y <= A(5); elsif (SEL = "0110") then Y <= A(6); elsif (SEL = "0111") then Y <= A(7); elsif (SEL = "1000") then Y <= A(8); elsif (SEL = "1001") then Y <= A(9); elsif (SEL = "1010") then Y <= A(10); elsif (SEL = "1011") then Y <= A(11); elsif (SEL = "1100") then Y <= A(12); elsif (SEL = "1101") then Y <= A(13); elsif (SEL = "1110") then Y <= A(14); else Y <= A(15); end if;
end process;end RTL1;
![Page 26: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/26.jpg)
MUX Models (2)architecture RTL3 of SELECTOR is
begin with SEL select
Y <= A(0) when "0000 ," A(1) when "0001 ," A(2) when "0010 ," A(3) when "0011 ," A(4) when "0100 ," A(5) when "0101 ," A(6) when "0110 ," A(7) when "0111 ," A(8) when "1000 ," A(9) when "1001 ," A(10) when "1010 ," A(11) when "1011 ," A(12) when "1100 ," A(13) when "1101 ," A(14) when "1110 ," A(15) when others ;
end RTL3;
•library IEEE;•use IEEE.std_logic_1164.all;•use IEEE.std_logic_unsigned.all;•entity SELECTOR is• port (• A : in std_logic_vector(15 downto 0);• SEL : in std_logic_vector( 3 downto 0);• Y : out std_logic;)•end SELECTOR;
![Page 27: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/27.jpg)
MUX Models (3)architecture RTL2 of SELECTOR is
begin p1 : process (A, SEL) begin
case SEL is when "0000" => Y <= A(0); when "0001" => Y <= A(1); when "0010" => Y <= A(2); when "0011" => Y <= A(3); when "0100" => Y <= A(4); when "0101" => Y <= A(5); when "0110" => Y <= A(6); when "0111" => Y <= A(7); when "1000" => Y <= A(8); when "1001" => Y <= A(9); when "1010" => Y <= A(10); when "1011" => Y <= A(11); when "1100" => Y <= A(12); when "1101" => Y <= A(13); when "1110" => Y <= A(14); when others => Y <= A(15);
end case; end process;
end RTL2;
•library IEEE;•use IEEE.std_logic_1164.all;•use IEEE.std_logic_unsigned.all;•entity SELECTOR is• port (• A : in std_logic_vector(15 downto 0);• SEL : in std_logic_vector( 3 downto 0);• Y : out std_logic;)•end SELECTOR;
![Page 28: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/28.jpg)
MUX Models (4)
architecture RTL4 of SELECTOR isbegin
Y <= A(conv_integer(SEL));end RTL4;
•library IEEE;•use IEEE.std_logic_1164.all;•use IEEE.std_logic_unsigned.all;•entity SELECTOR is• port (• A : in std_logic_vector(15 downto 0);• SEL : in std_logic_vector( 3 downto 0);• Y : out std_logic;)•end SELECTOR;
![Page 29: Fundamentals of Digital Signal Processing](https://reader036.vdocuments.us/reader036/viewer/2022062302/5681638d550346895dd48281/html5/thumbnails/29.jpg)
Compilation and Simulation of VHDL Code
•Compiler (Analyzer) – checks the VHDL source code –does it conforms with VHDL syntax and semantic rules–are references to libraries correct
•Intermediate form used by a simulator or by a synthesizer•Elaboration
–create ports, allocate memory storage, create interconnections ... ,–establish mechanism for executing of VHDL processes