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Front End Manufacturing Technology
C. Rinn CleavelinSi Technology Development
Texas Instruments, Inc.Dallas, Texas
2
Topics Transistor Performance Trends Transistor Scaling Challenges New Device Architectures
Advanced CMOS Non-Classical CMOS Memories
New Front End Materials & Modules Lithographic Trends Summary
3
The definition of Moores Law has come to
refer to almost anything related to the
semiconductor industry that when plotted on
semi-log paper approximates a straight line.
Gordon Moore, 1995
Moores Law / Productivity
4
Transistor Performance Trend
1
10
100
1,000
10,000
100,000
1980 1985 1990 1995 2000 2005 2010 2015
Freq
uenc
y (M
Hz)
2X / 4 Years
2X / 2 - 2½ Years
2X / 2½ Years
MPU Clock Frequency Historical Trend:
Transistor scaling has contributed ~ 17-19%/yearArchitectural Design innovation contributed additional ~ 13-21%/year
Innovationneeded to maintain historical trend
Sources: SEMATECH, 2001 ITRS ORTC
Historical Data 01 ITRS Projection
Year
5
Topics Transistor Performance Trends Transistor Scaling Challenges New Device Architectures
Advanced CMOS Non-Classical CMOS Memories
New Front End Materials & Modules Lithographic Trends Summary
6
Transistor Scaling Key Challenges
Isolation: Minimum Pitch and SOI
Gate Dielectric: Leakage vs Speed
Gate Electrode: polySi vs Metal (Mid-gap vs Dual Work Function)
Ultra-Shallow Junctions (USJ) Low resistance contacts Low resistance abrupt S/D extensions
7
Technology Generation 130 nm 90 nm 65 nm 45 nm 32 nm 22 nmYear Production 2001 2004 2007 2010 2013 2016MPU Gate Length (nm)MPU Gate Length (nm) 6565 3737 2525 1818 1313 99DRAM (production) 512M 1G 4G 8G 32G 64GDRAM chip (cm2) 1.27 0.93 1.83 1.81 2.39 2.38 DRAM cost (µ ¢/bit) 7.7 2.7 0.96 0.34 0.12 0.042Wafer Diameter (mm)Wafer Diameter (mm) 300300 300300 300300 300300 450450 450450Logic M gates 97 193 386 773 1546 3092 Logic M gates/cm2 69 138 276 552 1104 2209Logic chip (cm2) 1.4 1.4 1.4 1.4 1.4 1.4Frequency (GHz) 1.7 3.9 6.7 11.5 19.3 28.7µP cost (µµµµ ¢/T) 97 34 12 4.3 1.5 0.54Power/ Chip (W) 130 160 190 218 251 288Power Supply MPU (V) 1.2 1.0 0.7 0.6 0.5 0.4Levels of Metal 7 8 9 9-10 9-10 10EOT (nm)EOT (nm) 1.31.3--1.61.6 0.90.9--1.41.4 0.60.6--1.11.1 0.50.5--0.80.8 0.40.4--0.60.6 0.40.4--0.50.5XXjj at Channel (nm)at Channel (nm) 2727--4545 1515--2525 1010--1717 77--1212 55--99 44--66
2001 ITRS Scaling Projections
8
Device Scaling Issues: Beyond 65nm Gate Stack
Tunneling => high Ioff Inversion Layer => EOT limit PolySi Depletion => Ion reduced Mobility degradation => Ion reduced CD control Reliability
Source/Drain Series Resistance => Ion reduced Dopant Profile Control
TED suppression USJ abrupt S/D extensions Contacts to S/D
Tunneling Drain to body & source to drain
P-WELL
STI STISOURCE DRAIN
GATE
Si-Substrate
Halo I2
Threshold Voltage: VDD VT decreases Subthreshold Slope kT/q CD Control
9
Isolation Roadmap
LOCOS ! Shallow Trench Isolation STI ! STI / SOI! SOI only?
STI induced to resolve LOCOS Birds Beak
Future device scaling and alternate structures such as Double Gate Logic devices and new member elements may lead to SOI only isolation.
IBM 16MB DRAMIBM 4MB DRAM
LOCOSSTI
10
Gate Length Scaling: ITRS ITRS Roadmap Acceleration ContinuesGate Length
10
100
1000
1995 1998 2001 2004 2007 2010 2013 2016
Year of Production
Tech
nolo
gy N
ode
-DR
AM H
alf-P
itch
(nm
)
2001 MPU Physical Gate Length
1999 ITRS MPU Gate-Length
2-year Cycle
3-year Cycle
2001 MPU Printed Gate Length
11
1.E-071.E-061.E-051.E-041.E-031.E-021.E-01
1.E+001.E+011.E+02
2001 2003 2005 2007 2009 2011 2013 2015
Year
J gat
e (A
/cm
2 )
0
0.5
1
1.5
2
2.5
3T
ox (nm)
Simulated Jgate, oxynitride
Specified Jgate, ITRS
Tox
Beyond this point, oxynitride too leaky; high K needed
Simulations by C. Osburn, NCSU and ITRS
2001 ITRS Projections Versus Simulations of Direct Tunneling Gate Leakage Current Density for Low Standby Power Logic
12
Topics Transistor Performance Trends Transistor Scaling Challenges New Device Architectures
Advanced CMOS Non-Classical CMOS Memories
New Front End Materials & Modules Lithographic Trends Summary
13
Limits of CMOS ScalingPlanarCMOS
TIME
Device EvolutionDevice Evolution
DeviceStructure
Size
Non-Planar CMOS
New SwitchStructure
0 - 7 years. 7 - 12 years 12 + Years.
Sub 50nm ?c- Sibody
source
drainPSG
gate gate PSG
HfO2
100 nmAgere 02
14
New Device Architectures SOI
Partially Depleted (PD) Fully Depleted (FD): Ultra-Thin Body
Double Gate Structures FinFET Tri, Pi Gate DG-SOI
Memory Innovations FeRAM, MRAM, Ovonics, etc
15
SOI Device Structures
BuriedOxide
Si-Substrate
STI STISOURCE DRAIN
GATE
CSOI CSOI
Bulk CMOS Partially Depleted CMOSPartially Depleted CMOS
P-WELL
" Short Channel Effect controlled by channel doping/halo as in Bulk" Reduced junction capacitances => faster speed, lower leakage" Device design translation straight forward between Bulk and PD SOI" Complete isolation between devices" Rad-hard
P-WELL
STI STISOURCE DRAIN
GATE
Si-Substrate
CBULK CBULK
Halo I2
16
Buried oxide
Drain(VD)
Partially versus Fully Depleted
Substrate = Back gate (VE)
Source(VS)
Drain(VD)
Gate (VG)
xs xd
tSi
tBOxbody region (Vbody)Substrate =Back gate (VE)
Source(VS)
Gate (VG)
tSi
tBOx
Partially depleted device" Bulk bottom junction capacitances
replaced by thick oxide capacitance " Gate side lateral junction
capacitance comparable to Bulk case. Can be smaller for PD in case of silicon film thinning
Fully depleted device" Bulk bottom junction capacitances
replaced by thick oxide capacitance " Full depletion of silicon film suppress
lateral junction capacitance"Speed improvement compared to PD
"Smaller power consumptionCourtesy of Olivier Faynot, LETI
17
Buried oxide
Drain(VD)
Partially versus Fully Depleted
Substrate = Back gate (VE)
Source(VS)
Drain(VD)
Gate (VG)
xs xd
tsi
tBOxbody region (Vbody)Substrate =Back gate (VE)
Source(VS)
Gate (VG)
tsi
tBOx
Partially depleted device" 4 or 5 nodes" Front and back gate decoupled
" internal floating body node" Floating-Body effects" VT=f (Vbody) independent of VE
Fully depleted device" 4 nodes" tsi<40nm (for deep sub-µm MOS)" No neutral floating region
" independent of 'body' voltage" subthreshold swing=60mV/decade
" Front-Back interface coupling" VT= f (VE)
Courtesy of Olivier Faynot, LETI
18
SOI: Power Reduction
19
Merits of Device Scaling <50nm Options
- Fabrication very difficult- Parasitic elements?
- Best case for SCE control- Relaxed constraint on Tsi
Double Gate
- Parasitic capacitances increase- Reduced SCE
- Relaxed constraint on Tsi
Partial Ground Plane
- Parasitic capacitances increase
- Subthreshold swing increase
- Reduced SCE- Relaxed constraint on Tsi
Ground Plane
- Scalability: Ultra-thin film- Small parasitic capacitances
- Simpler FD architecture
Standard FD device
WeaknessesStrengths
20
SOI is ~1.5 3x over bulk wafer pricing Etch Pit Density, typically ~600-1000/cm2
PD and to lesser extent FD have floating body effects which must be comprehended
FD requires Silicon body thickness control less than ~0.2 - 0.4x of Lg or for example 18nm Lg, tsi~36 - 72A for 45nm node
SOI Fabrication/Process Issues
21
New Device Architectures SOI
Partially Depleted (PD) Fully Depleted (FD): Ultra-Thin Body
Double Gate Structures FinFET Tri, Pi Gate DG-SOI
Memory Innovations FeRAM, MRAM, Ovonics, etc
22
Double Gate Structures: FinFET
23
Double Gate Structures: FinFET Gate
24
Double Gate Structures: Tri-Gate
25
Double Gate Structures: Tri-Gate
26
DG Fabrication/Process Issues Moat etch
Defines vertical gates Etch and gate dielectric interaction on vertical gate
structures Gate dielectric (including high-K integration)
Integrity, mobility, manufacturability Gate materials and etch
Depletion issues, hence Metal gate Junction and Contact
Ion Implant, PLAD, SEG Ground plane design
Implant through thin BOx
27
Options Below 50nm
High +++10-20nmHigh1015-1016GP, PGP & Metal gate
Very High +++
++15-30nmHigh1015-1016DG & Metal gate
Very High +++
++5-15nmHigh1015-1016FD & Metal gate
High ++++10-20nmMedium1017-1018DG & N+ /P+ Poly
High ++10-20nmLow1018-1019GP, PGP, DG & N+ Poly
Very High ++++5-15nmLow1018-1019FD & N+ Poly
High ++50-150nmLow1018-1019PD
Ref. o-/Low1018-1019BULK
PerfParasitic cap
Silicon filmMobilityDoping
28
New Device Architectures SOI
Partially Depleted (PD) Fully Depleted (FD): Ultra-Thin Body
Double Gate Structures FinFET Tri, Pi Gate DG-SOI
Memory Innovations FeRAM, MRAM, Ovonics, etc
29Many choices in development
4b/cVt1111 0000
#cel
ls
Bit-Sense Line
M1 Word Lines
M4 Word Lines
Magnetic Storage Bits
M2 MetalM3 Metal
Top View
Side ViewSide ViewInterlayerDielectrics
M1 Word Lines
M4 Word Lines
1 1 1 10 0
Sense CurrentDirections
Data Storage Region
ResistiveElectrode
AmorphousChalcogenide
MaterialHeater
CrystallineAmorphousChalcogenide
Material
Crystalline
PolymerNROMETOX®-
4bpc
MRAM OUMFERAM
Word line
Charge Storage Sites in Nitride:
2 LocationsONO Stack
P-Sub
Bit Line
Oxide
Buried Diffusion Bit lines
* Other brands and names are the property of their respective owners
Word linePolymer Layer
Bit line Bit line Bit linePolymer Layer
Word line
Word line
S. Lai - Intel
Memory Technologies
Phase Change
30
Memory Technologies Comparison
Log Number of Erase/Write Cycles
Log
Writ
e Ti
me
(fast
er >
)
ROM Space
ROMEPROM
Not in-systemChangeableUnlimited Read
Cycles
VolatileMemorySpace
SRAMDRAM
New NV RAM Space
FeRAM OUM MRAMLimited Unlimited Read Read Cycles Cycles
Flash Space
ETOX NAND
Unlimited Read Cycles
S. Lai - Intel
31
FeRAMWhat Is FeRAM?
Operation Selected crystalline materials
have spontaneous polarization Data is stored by applying a
voltage to align the internal dipoles Up or Down
Attributes Non-Volatile Fast Random Read Access Fast Write with very low power
consumption Destructive read, limited read and
write cycles
E
P
Ec
Pr
Esat
Source: Physics Today 7/98
32
Operation Cell is 1 MJT + 1 Transistor Electric current switches the
magnetic polarity Change in magnetic polarity
sensed as resistance change Attributes
Non-Volatile, High Density Non Destructive Read Low Voltage & Low Power Write = Read Speed, < 50 nsec Unlimited R/W Endurance Material compatibility with
CMOS a key challenge
Bit-Sense Line
M1 Word Lines
M4 Word Lines
Magnetic Storage Bits
M2 MetalM3 Metal
Top View
Side ViewSide ViewInterlayerDielectrics
M1 Word Lines
M4 Word Lines
1 1 1 10 0
Sense CurrentDirections
MRAM
S. Lai - Intel
33
Topics Transistor Performance Trends Transistor Scaling Challenges New Device Architectures
Advanced CMOS Non-Classical CMOS Memories
New Front End Materials & Modules Lithographic Trends Summary
34
New Front End Materials & Modules
Substrates: Strained Si SOI; Ultra Thin Body (UTB) Si 450mm
Gate Dielectrics: Oxide to High-k Gate Electrodes: doped polySi to metal gate Ultra-Shallow Junctions:
Raised S/D Non-equilibrium annealing
Gate Etch / CD Control and Clean
35
SubstratesProgression of CMOS substrate technologies:Bulk SiliconBulk Silicon with Backside GetteringEpitaxial Silicon (P/P+)Partially Depleted (PD-SOI)Strained Silicon (SiGe Relaxed Hetero-structure)Partially Depleted Strained SiliconFully Depleted (FD-SOI)Fully Depleted Strained Silicon
36
Strained-Si MOSFET Structures
Graded Layer0.05
=x
Drain
p+
n- Si1-yGeyy=
y
n+ Si Substrate
n+poly
n Strained Si
SourceSiO
p- Si1-yGey Graded Layery=0.05
y=x
p+ Si Substrate
n+poly
p Strained Si
Source DrainSiO2
Gate
n+ n+
high mobility (µ)channels
p- Relaxed Si1-xGex
2
Gate
n- Relaxed Si1-xGex
Strained Si1-xGex
Courtesy of J. Hoyt - MIT
p+
Graded Layer0.05
=x
Drain
p+
n- Si1-yGeyy=
y
n+ Si Substrate
n+poly
n Strained Si
SourceSiO
p- Si1-yGey Graded Layery=0.05
y=x
p+ Si Substrate
n+poly
p Strained Si
Source DrainSiO2
Gate
n+ n+
high mochannels
p- Relaxed Si1-xGex
2
Gate
n- Relaxed Si1-xGex
Strained Si1-xGexp+
+ Increased effective mobility, increased Ion
- Difficult integration issues: manufacturability- Compatibility with ultra-thin body SOI- Cost (~50% cost adder @300mm)
37
Strained Silicon CMOS
38
Gate Ox. 60 Å
Gate Poly-silicon
Strained Si n-MOSFETon Relaxed Si0.8Ge0.2Lpoly = 0.13 µm
LTOGate Spacer
High mobilityStrained Si Channel130 Å
Relaxed Si0.8Ge0.2
X200000
100 Å
Photo courtesy ofAPRDL, Motorola Inc.
Cross-Section TEM of Strained Si Channel
Rim, Hoyt,and Gibbons,IEDM 1998
39
Cross-Section TEM of Strained Si Transistor
Courtesy UMC/Amberwave
40
Strained Silicon Mobility Enhancement
Vertical Effective Field (MV/cm)0.1 0.2 0.3 0.4 0.5 0.6 0.7
Effe
ctiv
e M
obilit
y (c
m2 / V
-sec
)
0
200
400
600
800
0.290.200.10
VDS = 10 mV Substrate Ge Content, x :
CZ Si Control0
Vertical Effective Field (MV/cm)0.1 0.2 0.3 0.4 0.5 0.6 0.7
Effe
ctiv
e M
obilit
y (c
m2 / V
-sec
)0
50
100
150
200
0.290.220.10
VDS = -10 mV 295 K
Substrate Ge Content, x :
low-field electron and hole mobilities increase with tensile strain in Si peak mobility enhancement ratios: ~ 1.8 for 30% Ge substrate
NMOS PMOS
Courtesy Judy L. Hoyt
41
SOI: Ultra Thin Body (UTB) Si
Yee-Chia Yeo, et. al. UTBFET for NanoCMOS
UTB SI with Strained Si combines advantages of SiGe/Si heterostructure with UTB low leakage
42
Wafer Area Generation Model
0
1
10
100
1,000
10,000
100,00019
60
1965
1970
1975
1980
1985
1990
1995
2000
2005
2010
2015
2020
2025
Year
Area
Dem
and
Per Y
ear (
10^6
Sq.
Inch
es)
2002
Total Wafer Area Trend Model 1976-2025: 10% CAGRCAGRCAGRCAGR
100%
10%
33%
Ironman
Pilot LineLineLineLine
75/100mm125/150mm
200mm300mm
450mm
38/51mm
Sources: VLSI Research, SEMATECH, I300I
450mm out450mm out
2001 Projection for 450mm, 2013
43
New Front End Materials & Modules
Substrates: Strained Si SOI; Ultra Thin Body (UTB) Si 450mm
Gate Dielectrics: Oxide to High-k Gate Electrodes: doped polySi to metal gate Ultra-Shallow Junctions:
Raised S/D Non-equilibrium annealing
Gate Etch / CD Control and Clean
44
PolyPoly--Si /Si /
cc--SiSi
HfSiONHfSiON
Gate Dielectric: SiO2 to High-k
Si/SiO2Interface Control
Gate Oxide Thickness
Poly Si/SiOPoly Si/SiO22/Si TEM Cross/Si TEM Cross--sectionsection
Poly Si/SiOxNy/Si Poly Si/Poly Si/SiOSiOxxNNyy/Si /Si
N profile
Node: >/~250nm 180nm ~65nm ≤65nm?
Si Oxide+ Long History+ Reliable- Leaky < 25A
Si Oxide+ Long History+ Reliable- Leaky < 25A
Si Oxynitride+ Low B penetration+ Reliable- Not scalable <1nm
Si Oxynitride+ Low B penetration+ Reliable- Not scalable <1nm
HfSiON+ Mid High-k+ Scalable <1nm+ Low B penetration- Mobility degraded ~15%
45
MOCVD HfO2 High-κ κ κ κ Dielectric
0
20
40
60
80
100
120
140
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6
Voltage [V]
Cap
acita
nce
[pF]
Corrected Freq DataCVC Model
CVC ModelEOT = 0.95
nmVfb = -0.239 V
Nsurf = 2.11E15
Area = 5.0E-5 cm2Frequency = 100 and 250 kHzGate Electrode : PVD TiN
Gate Leakage4.3 A/cm2 @ 1V10 A/cm2 @ Vfb+1
HfO2 @ 485CInterface: N2O at 750C
PVD TiN 450 Å
HfO2 21 Å Interfacial layer 12 Å
Silicon substrate
TEM (left) for MOCVD HfO2 with EOT = 0.95 nm and CV curve (right) [80]Courtesy International SEMATECH
Effective Dielectric Constant ~ 13.5
46
High-k Leakage Current versus EOT (trends)
1.E-08
1.E-06
1.E-04
1.E-02
1.E+00
1.E+02
1.E+04
1.E+06
0 5 10 15 20 25Equivalent Oxide Thickness [A]
Jg @
+/-
|Vfb
+1| [
A/cm
2 ]
SiO2 modelGoal LineALCVD HfO2
ALCVD Hf-AluminateALCVD Stacks
GoalJg 1A/cm2 @ EOT 1 nm
47
High-k Manufacturability Issues Interface dielectric preparation and control High-k dielectric amorphous phase thermal
limitations Material etch characteristics / selectivity Boron penetration resistance High-k dielectric interactions with gate electrode Deposition complexities for multi-component
dielectric materials Conformal depositions for non-planar gate
structures Metrology of heterogeneous multilayer dielectric
films
48
Gate Dielectric Scaling
Lattice fringes for gate dielectric
14 Å 17 Å 20 Å 29 ÅC-V
HRTEM 14.2 ± 1.7 Å 17.1 ± 2.0 Å 18.6 ± 1.7 Å 26.2 ± 2.2 ÅVert
ical
Sca
ling
Interface Control is critical to achieve <10A effective Gate Dielectric - To achieve 7A effective thickness:
Interface Dielectric <1AHigh-k dielectric <1APoly Depletion <1A => Metal GateChannel Quantum Effect ~4A
49
New Front End Materials & Modules
Substrates: Strained Si SOI; Ultra Thin Body (UTB) Si 450mm
Gate Dielectrics: Oxide to High-k Gate Electrodes: doped polySi to metal gate Ultra-Shallow Junctions:
Raised S/D Non-equilibrium annealing
Gate Etch / CD Control and Clean
50
Gate Electrode: Why metal gate? polySi depletion
EOT reduces => Eox lower => inversion charge lower
For EOT scaling => polySidoping must increase
PMOSFETs: B penetration with thin gate dielectrics Nitrided gates used to reduce B
penetration Compatibility of polySi with
high-k dielectrics Gate resistance of very thin
gates even with silicide
Polysilicon Gate
Gate Oxide
Substrate
Depletion Layer
Tox
Inversion Layer
Wd,Poly
XC,QM
XC,Poly
51
Gate Electrode Options
- Identification of Dual Metal system
- Integration difficult, esp. Dual Metal
- No poly depletion- VT can be lower than
0.4V- Intrinsic devices:(high µ expected)
Metal gate
- VT can not be lower than 0.4V
- No poly depletion - Intrinsic devices:(high µ expected)
Mid-gap gate
- Required doping level higher than PD/Bulk- Simpler Process
N+ Poly gate
Con'sPro's
52
New Front End Materials & Modules
Substrates: Strained Si SOI; Ultra Thin Body (UTB) Si 450mm
Gate Dielectrics: Oxide to High-k Gate Electrodes: doped polySi to metal gate Ultra-Shallow Junctions:
Raised S/D Non-equilibrium annealing
Gate Etch / CD Control and Clean
53
Ultra-Shallow Junctions - USJ
10
100
1000
10000
0 10 20 30 40 50 60 70 80Junction Depth (nm)
Rs
(ohm
/sq.
)
180-nm130-nm100-nm70-nm50-nm35-nmCrystalline DataPreamorphized DataLTA DataUHV-RTCVD DataVortek BF2 Data
54
USJ Advanced Spike RTA
1.E+17
1.E+18
1.E+19
1.E+20
1.E+21
1.E+22
0 100 200 300 400 500 600Depth (A)
Bor
on C
once
ntra
tion
(atm
/cc)
PAI / 1.2E15 BF2 @ 5keV / 950°°°°C Spike
As Implanted
1050°°°°C SpikeRsh = 412
1050°°°°C Refined SpikeImproved T-tRsh = 481
1075°°°°C Refined SpikeRsh = 382
55
1E+18
1E+19
1E+20
1E+21
0 50 100 150 200 250depth (Å)
conc
entra
tion
(/cc)
as implanted
1189°C flash - 414 Ω/
1370°C flash - 433 Ω/
Flash assisted Impulse Anneal, 800°C Flash assisted Impulse Anneal, 800°C Intermediate TemperatureIntermediate Temperature
T
Time
IntermediateTemperature
56
Raised Source/Drain
Raised Source/DrainRaised Source/Drain
Advantages Improves drive current Improves SCE Essential for FD-SOI with
ultra-thin-body Needs
Low Temp Selective EPI process <650 C
Facet control at sidewall edge
High doping (Ge, B, P) Low defects Good uniformity Low CoO
57
New Front End Materials & Modules
Substrates: Strained Si SOI; Ultra Thin Body (UTB) Si 450mm
Gate Dielectrics: Oxide to High-k Gate Electrodes: doped polySi to metal gate Ultra-Shallow Junctions:
Raised S/D Non-equilibrium annealing
Gate Etch / CD Control and Clean
58
Parameters involved in Line-edge roughness add in quadrature:σσσσ LER
2 = σσσσSHOTNOISE2 + σσσσDIFFUSION
2 + σσσσ AERIAL IMAGE2 + σσσσ DEVELOPMENT
2 + σσσσ ETCH 2 + σσσσ MASK
2
Gate Stack Etch
Issues:LER of resist • resist molecular scales (~ 5 nm)• image contrast and flare• mask roughness• development effects
Etched gate edge roughness• transfer of LER from resist • does not scale with etch bias• granularity of film stack adds
Line and sidewall edge roughness
59
Atomistic Lateral Scaling of Gate Length
Gate Edge CD Control and Transistor Performance critical to etching and cleaning chemistries
Gate Stack CD Control
293 lattice planes = 91.9nm wide
Dr. T.J. Headley, Sandia IMRL
Late
ral S
calin
g
60
FEOL Clean Challenges New Materials and Processes
Cleaning and drying High Aspect Ratio (HAR) structures Interface control for deposited high-k dielectrics Post high-k gate stack etch cleans compatible with exposed
materials and CD control Interface control for epitaxial Si and Si-Ge
Scaling and Defect Levels Removal of small particles without affecting materials and
structures Control of contaminates (carbon, etc) for non-oxide gate
dielectrics ESH
Chemical, DI water, energy reduction, and hazardous chemical elimination and avoidance
61
Topics Transistor Performance Trends Transistor Scaling Challenges New Device Architectures
Advanced CMOS Non-Classical CMOS Memories
New Front End Materials & Modules Lithographic Trends Summary
62
32
1.51
0.4 0.350.25
0.180.13
0.10.07
0.05
0.50.6
0.01
0.1
1
10
1980 1990 2000 2010Year
Mic
rons
The Sub-Wavelength Gap
Stretching out wavelength
Abovewavelength
Nearwavelength
Belowwavelength
g-lineλλλλ=436nm
i-lineλλλλ=365nm
DUVλλλλ=248nm
193λλλλ=193nm 157 (VUV)
λλλλ=157nm
Pulling in feature size
Source: Numerical Technologies
0.035
λλλλ =EUV 13.5 nm
Res
olut
ion
Lithographic Front End Trends
63
Lithographic Front End Trends
Start mass production
2001 2003 2005 2007
Technology generation
130 nm 90 nm 65 nm 45 nm
Minimum half-pitch
160 nm 115 nm 80 nm 55 nm
k1-factor
λ=248 nm, NA=0.7
0.45 λ=193 nm, NA=0.63
0.52
λ=193 nm, NA=0.63
0.38 λ=193 nm, NA=0.75
0.45
λ=193 nm, NA=0.85
0.35 λ=157 nm, NA=0.85
0.43
λ=157 nm, NA=0.95?
0.33 λ=157 nm, NA=1.25?
0.44 Respective
DOF in micron
0.48
0.47
0.47
0.32
0.25
0.22
0.16
0.09
Layer-layer overlay
45 nm 32 nm 22 nm 15 nm
Liquid immersion lithography, assuming index = 1.4 and NA = 0.9 in liquid
In Keeping Pace with Moores Law
64
Summary Front End Manufacturing Technology will undergo
significant changes both in the near-term and long-term as new processes, materials, and structures are introduced to meet Roadmap scaling requirements.
Material and process solutions potentially include high-k dielectrics, metal gate electrodes (mid-gap/dual), SOI (PD/FD), Strained Si, Spike and/or non-equilibrium annealing, Raised S/D, and others yet to be identified.
Longer-term new non-classical CMOS structures such as Dual Gate, FinFET, PI/Tri-gate, may be required in combination with new materials to provide the ultimate End-of-Roadmap devices.
65
Acknowledgements
Allen Bowling, Texas Instruments Olivier Faynot, LETI Judy Hoyt, MIT Majid Mansoori, Texas Instruments Shane Palmer, Texas Instruments Walt Trybula, International SEMATECH Rick Wise, Texas Instruments Peter Zeitzoff, International SEMATECH
66
Backup Charts
67
∆ Es ~ 670.x(meV)
Effects of Biaxial Tensile Strain on Si Energy Bands and Mobility
Conduction BandSplitting between ∆2 and ∆4
- reduced intervalleyscattering
- smaller in-plane effectivetransport mass
k
Bulk Si Strained Si
HH
LH
Spin-Orbit
E EValence Band
HH/LH degeneracy lifted at Γ
- reduced interbandscattering
- smaller in-plane transport mass due to band deformation
Γin-plane out-of-
planek
∆2
∆4
[001]
[010]
[100]
∆4
∆2
∆6Ec
Bulk Si Strained Si
ml
mtmt
mt < mlµ = q τ
m*c
Strained Si grown on Relaxed Si1-xGexbiaxial tension
Courtesy of J. Hoyt - MIT