from layout to chips - mycmp · photonic • first run launched in october • already 2 designs...

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CMP annual users’ meeting - 25-Jan-18 - PARIS C ircuits M ulti-P rojets® MPW Services Center for ICs, Photonics & MEMS Prototyping & Low Volume Production mycmp.fr Grenoble - France From layout to chips

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Page 1: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

Circuits Multi-Projets®MPW Services Center for ICs, Photonics & MEMS

Prototyping & Low Volume Productionmycmp.fr

Grenoble - France

From layout to chips

Page 2: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

From layout to chips

MEMS & Photonics MPW services

Page 3: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

CEA/LETI Photonic – Si-310 PHMP2M

MEMS Processes

Bulk Micromachining

MUMPs from MEMSCAP

Teledyne DALSA MIDIS

Outline

Page 4: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

CEA/LETI Photonic – Si-310 PHMP2M

Photonic – Si-310 PHMP2M• 200mm CMOS SOI platform• Silicon film 310 +/-10nm• Multilevel patterning allowing silicon heights of 0, 65, 165 and 300nm• 2 Metal layers (MET1 and Alucap)

Présentateur
Commentaires de présentation
Process CMOS sur une platforme SOI 200mm Une varation du silicium entre 0/65/165/300nm qui permet une flexibilité des structures TiTin: tune les composants
Page 5: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

CEA/LETI Photonic – Si-310 PHMP2M

Photonic – Si-310 PHMP2MPassive components

• Fiber grating coupler 1D/2D• Shallow / Rib / Strip WaveGuides & bends• Ring filter• Multimode interferometers

Active components• Mach Zender modulator• Ring Racetrack modulator• Ge Photodiode• TiTin Metal heater

Présentateur
Commentaires de présentation
Les kits distribués par CMP intègrent des librairies avec des composants actifs et passifs Passifs: Coupleur / Guides d’ondes et filtres optiques Actifs: Modulateurs et Photodiodes Un couche de métal permet aussi d’ajuster les composants
Page 6: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

Direct Connection with CMOS processes• CMP propose several CMOS processses compatible

with photonic process• 3D stacking• Interposer

Packaging Compatibility• Fiber array alignment• Optical packaging

CEA/LETI Photonic – Si-310 PHMP2M

Présentateur
Commentaires de présentation
Les pads peuvent avoir une couche UBM fait en sortie de fab
Page 7: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

Our offer• 2 MPW runs/year: next run in

March 2018• 3D Post-process option available• Supported PDKs: Cadence, Mentor

(Pyxis) , Phoenix software

2018 Expectations• Training Q3: Photonic Introduction,

kit, process and design flow presentation.

• Tutorial will be available Q3

CEA/LETI Photonic – Si-310 PHMP2M

Présentateur
Commentaires de présentation
Prix pour S> 10 mm2 => 900 Euro/mm2 �CMP vend des blocs de 2 x 1 mm
Page 8: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

Realization Examples

1D Fiber coupler

Highly confined waveguides

2D Fiber coupler

Optical Receptors

GE PIN Diode

CEA/LETI Photonic – Si-310 PHMP2M

Optical transceiver circuit

Page 9: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

MEMS Processes

Bulk Micromachining

MUMPs from MEMSCAP

Teledyne DALSA MIDIS

Page 10: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

• Compatible with electronics• Front side bulk micromachining• ams 0.35µ CMOS, SiGe, High Voltage

MPW run turnaround : 8/10 Weeks

Post process turnaround : 5 weeks

Suspended passive device

Bulk micromachining on CMOS

Présentateur
Commentaires de présentation
J’ai modifié la font et l’interligne à droite
Page 11: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

MEMs accelerometer and signal conditioning

• Front-end electronics close to MEMS sensor for better signal to noise ratio

Bulk micromachining designs

Test sensor structures Flow sensor

Page 12: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

A CMOS Compatible Ultrasonic Transducer Fabricated With Deep Reactive Ion EtchingLibor Rufer, Christian C. Domingues, Salvador Mir, Valérie Petrini, Jean-Claude Jeannot, and Patrick DelobelleJOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 15, NO. 6, DECEMBER 2006

• Applications : piezo resistive devices, pressure sensors, transducers

Backside bulk micromachiningIntegration of MEMS sensor and front-end electronics

Membrane and suspend structure on top of cavity

Backside bulk micromachining

Page 13: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

Design Kit• Standard DK for the 0.35µ CMOS process C35B4C3 from ams• Design Rule Manual and technology files provided for MEMS

structures• MEMS DK for :

Fabrication schedule• ams C35B4C3 : next run starts on February 20th

Access to bulk micromachining

Page 14: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

• Company created in 1997, technology

available through CMP since 1998

• 3 different processes : PolyMUMPs

SOIMUMPs

PiezoMUMPs

MEMSCAP

Page 15: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

Features• 2 mechanical and 1 electrical layer of polysilicon• 2 sacrificial layers• 1 electrical conduction layer• 1 electrical isolation layer• Optional post process : etching/release, CO2

drying, sawing

POLY 2

Applications• Acoustics

(microphones)• Accelerometers • Micro-fluidics• Display Technologies

PolyMUMPs

Page 16: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

Features• Silicon On Insulator substrate • Reactive-Ion Etching (RIE)• 10 to 25 µm structural layer• 2 Metal layers

Si

Substrate

METAL

OXYDE

Applications• Gyros• Optical devices• Display technology

Cross section of RIE etching

SOIMUMPs

Page 17: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

Features• Based on SOIMUMPs process• 0.5 µm Aluminium Nitride

piezoelectric layer• Active piezoelectric device• 2 Metal layers

Applications• Energy harvesting• Ultrasonic

transducers• Microphones• Actuators

PiezoMUMPs

Présentateur
Commentaires de présentation
Récupération d'énergie Transducteurs ultrasoniques Microphones Actionneurs
Page 18: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

Design kits and CAD tools

• Physical design, DRC :

• Specific MEMS CAD tools :

Fabrication Schedule • PolyMUMPs : 4 runs in 2018 • SOIMUMPs : 3 runs in 2018 • PiezoMUMPs : 3 runs in 2018

Access to MUMPs

Page 19: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

MEMS Integrated Design for Inertial Sensors (MIDIS™)Features• Getter-free high-vacuum sealing allows resonator Q factors > 20,000• Efficient wafer-level packaging minimizes overall die size• 1.5 μm feature size in a 30 μm thick membrane• Comb height control allows out-of-plane sensing• TSV allows compact design ready for co-packaging

Applications• Accelerometers• Gyroscopes• Resonators• Inertial sensor combos (Sensor fusion)

Inertial sensorCourtesy of CMC

Teledyne DALSA MIDIS platform

Page 20: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

Teledyne DALSA MIDIS platform

Pict

ure

from

CM

C

Présentateur
Commentaires de présentation
Vue de coupe ou l’on peut voir comment on gère et règle les atmosphère (par face arrière) L'étanchéité sous vide poussé sans getter permet des facteurs Q du résonateur> 20 000. TSV permet une conception compacte prête pour le co-emballage. - L’étanchéité à haute préssion de ce proccesse permet des facteur Q elevé - Le packaging niveau wafer est très efficace permet de minimiser la taille de package globale notament grâce aux TSV de la techno
Page 21: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

Cross section of Typical MIDIS process

Teledyne DALSA MIDIS platform

Pict

ure

from

CM

C

Page 22: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

Process Design Kit from Teledyne DALSA• Process parameters specifications• Design rules• DRC deck• Technology files for solid model generation• MIDIS solid model generation• Offers a truly representative 3D view of your design• Ready for design review• Multi-physics simulations

Fabrication schedule• 1 runs scheduled for 2018 (1st run April 10th/devices shipment 1st October)

Access to MIDIS

Page 23: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

Photonic• First Run launched in October• Already 2 designs booked for 2018• Training and Tutorial in September 2018

MEMS Process• 2 Designs in PiezoMUMPS process• 2 ams bulk micromachining designs

2017 Photonic and MEMS Results

Présentateur
Commentaires de présentation
Packaging et hybridation possible par le CMP
Page 24: From layout to chips - myCMP · Photonic • First Run launched in October • Already 2 designs booked for 2018 • Training and Tutorial in September 2018. MEMS Process • 2 Designs

CMP annual users’ meeting - 25-Jan-18 - PARIS

Thank you !

From layout to chips