fpga
DESCRIPTION
a general lecture in FPGA which we gave in the student exhibition 2008 in the collageTRANSCRIPT
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FPGA ( Field programmable gate array )
April 2008
• Prepared by :
Muhammad Ziyada
Muhammad Al tabakh
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Contents
• Hardware engineers vs software developers
• FPGA Market
• History of FPGA
• Modern developments
• Architecture
• Design and programming
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Hardware designers vs software developers
• The hardware engineers roll up their sleeves and work for months without a break
• software programmers would sit back and relax, or play ping-pong, until the hardware was stable.
• the hardware design would quickly become a hardware redesign for some perceived deficiency or new feature request
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VHDL solution
• In the early days, circuits as gate-level schematics.
• saved by (HDLs).
• allowed us to describe the functionality
• Allowed design to be quickly and easily represented and simulated
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VHDL
• VHSIC hardware description language • developed at the behest of the US Department of
Defense • alternative to huge, complex manuals which were
subject to implementation-specific details • logic simulators were developed to read the
VHDL files • logic synthesis tools that read the VHDL
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FPGA market• FPGA Market Will Reach $2.75 Billion by Decade’s
End
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FPGA market
• January 2008 • Celoxica Holdings has agreed the $3m sale of its
electronic system level (ESL) business to US firm Catalytic.
• With this move, we can synthesize the top two languages for high-level algorithm development — C and MATLAB — and deliver both software and hardware implementations
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FPGA market
• Aerospace & Defense
• Automotive
• Broadcast Consumer
• Data Processing and Storage
• Industrial / Scientific / Medical
• Wired Communications
• Wireless Communications
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FPGA market
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Brief history
• the invention of the very first
computers in the 1940's and 1950's
• A Xilinx co-founder, Ross Freeman, invented the field programmable gate array in 1984
• FPGA come after many earlier devices
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Modern development• Configurable Logic Blocks Registers (flip flops) for fast data storage . Logic Routing• Input/Output Blocks Basic pin logic (flip flops, muxs, etc)• Block Ram Internal memory for data storage• Digital Clock Managers Clock distribution• Programmable Routing Matrix
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"Pros" and "Cons"
• ProsLow power consumption; ideal for portable
electronics devices. Upgradeable using software, instead of extensive
hardware replacement .Low cost of overhead .Sometimes replaces as many as twenty traditional
PALs. Parallel computing possibilities .
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• ConsHigh cost of fabricating a completely new chip
Size constraints / limitationsMore difficult to code & debug
Many applications still are, and may remain, in the
theoretical phase
"Pros" and "Cons"
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FPGA vs classical architecture
• Classical operation
Fetch an instruction
Fetch a piece of data
Fetch another piece of data
Perform an operation
Store the result
:
Do the same thing all over again
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FPGA vs classical architecture
• y = (a * b) + (c * d) + (e * f) + (g * h);
• the multiplications are performed in parallel without the need to fetch and decode the instructions. This results in orders-of-magnitude speed improvement.
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FPGA vs conventional circuitFPGA Costs
$0
$50
$100
$150
$200
$250
$300
$350
1998 1999 2000 2001 2002 2003
Co
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per 1
Mil
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n G
ate
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80’s 90’s Now
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The rise of FPGA
• The first devices were primitive diode matrices used in TV channel selectors, HAM radio tuners, emerging defense and space applications.
• replaced by more capable logic devices based on arrays of combinatorial gates
• dramatic change in reprogram ability, more flexible interconnect architectures.
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The rise of FPGA
• Programmable Logic Arrays (PLA)
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The rise of FPGA
• Programmable Array Logic (PAL)
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The rise of FPGA
• Complex PLDs (CPLDs)
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The rise of FPGA
• Field Programmable Gate Arrays (FPGAs)
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Main vendors
• Xilinx spartan and vertix series
ise webback software
• Altera cyclon series
Quartus software
• Mentor Graphic
FPGAdv software
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FPGA design
skip
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FPGA design
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FPGA programming
Languages
HDL languages ( VHDL and VERILOG )
Truth table
Block diagram
Schematic diagram
Flowchart
State machine
And more
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VHDL codeLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY mux2to1 ISPORT ( w0, w1, s : IN STD_LOGIC ;f : OUT STD_LOGIC ) ;END mux2to1 ;ARCHITECTURE Behavior OF mux2to1 ISBEGINPROCESS ( w0, w1, s )BEGINIF s = '0' THENf <= w0 ;ELSE f <= w1 ;END IF ;END PROCESS ;END Behavior ;;
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Soft cores
• MicroBlaze,PowerPC,Nios,… soft processor
• create complete systems composed of, for example, an 8- or 16-bit controller, a UART, and other such I/O devices on a single programmable chip
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Soft processor
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References
• Practical FPGA Programming in C
By David Pellerin, Scott Thibault
• Ece230 vhdl lectures By Khurram Waheed
• VHDL cookbook By peter j.ashenden
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Thank you
Muhammad ziyada
+ 20113246609
Muhammad al tabakh
+ 20121539035