ECE 506

Reconfigurable Computing

http://www.ece.arizona.edu/~ece506

Lecture 5

Logic Block Architecture

Ali Akoglu

FPGA Design, Symmetrical Architecture Approach

Architectural Issues – Ahmed and Rose

• What values of N, I, and K minimize the following parameters?

- Area- Delay- Area-delay product

Architectural Issues – Ahmed and Rose

° What is a high stress routing?

° What are the potential problems with measuring critical path delay under high stress routing?

° How are these issues avoided?

• Routing using minimum number of tracks needed for the circuit

• This leads to increased routing execution time• Inconsistent results in delay• Solution: relax CW by 30%

Design Flow

Background Check

° What is the role of a buffer?• isolate other gates or circuits from each other • drive high current loads • high "fan-out" capability

- for power amplification of a digital signal• output of a logic gate usually connected to the inputs of other

gates. • each input requires a certain amount of current from the gate

output to change state, • each additional gate connection adds to the load of the gate.

Architectural Issues – Ahmed and Rose

Fcin fixed!# of muxes to feed into increases with N

Fully Connected Clusters

• Require fewer than full KxN inputs to achieve high logic utilization:- input sharing, - output-input sharing, - some LUTs not requiring all inputs to be used, - I=K/2*(N+1) (50%-60% is good enough for 98%, hence /2)

• Reducing inputs reduces the size of the device and makes it faster.

Before Placement: Clustering

° Academic studies typically consider fully populated (connected) logic cluster:

• Simpler to write CAD tools

Before Placement: Clustering

° Commercial parts: depopulated

° (this is 50%)

Effect of N and K on Area

° Reduction in total area as cluster size is increased from 1 to 3 for all LUT sizes.

° As clusters are made larger (N>4), there is little impact on total FPGA area.

Effect of N and K on Area

° intercluster area • more external connections localized, reducing area• number of inputs/outputs increase per CLB, this

increases the track count leading to increase in intercluster area

° intracluster area • more MUXes are used in the CLB, increasing area

As N increases

Intracluster area with respect to K

faster pace in increase in logic area than decrease in number of CLBs.

Intercluster area with respect to K

As K increases, number of clusters decreases faster than the rate of increase in external routing area.

Delay vs K and Nrate of change in BLE, CLB and inter-cluster delays, rate of change in the number of BLEs and CLBs on critical path

Effect of N and K on Area-delay product

K = 4-6, N= 4-10 looks OK