FPGA based Software Defined Radio

Centre de Recherche INRIA – Rennes Bretagne Atlantique

Abstract

Software defined radio (SDR) opens a new door to future Internet of Things with higher degree of designing flexibility in context of wireless system development. Prototyping a remote implementation of wireless protocols on a hardware over the web requires a highly versatile software radio platform along with laid-back designing tools. To this aim, an FPGA-based SDR scheme has been proposed combining Virtex-6 Perseus 6010 platform capabilities and a design flow based on High-Level Synthesis (HLS) tools. A full IEEE 802.15.4 (ZigBee) physical layer has been implemented on the proposed platform from a C-language dataflow specification. All the results have been analyzed to lead to a fair comparison between different design flows. Although the proposed SDR has some designing issues, it shows a noticeable designing potentiality to flexible prototyping of future wireless systems.

IRISA / Inria – Cairn TeamEnergy-Efficient Reconfigurable Computing Architectures

An FPGA Software Defined Radio Platform with a High-Level Synthesis Design Flow

University of Rennes 1 – IRISA / InriaENSSAT – 6 rue de kerampont – 22300 Lannion

Francehttp://www.irisa.fr/cairn

Vaibhav Bhatnagar, Ganda Stephane Ouedraogo, Matthieu Gautier, Arnaud Carer and Olivier SentieysIRISA, INRIA, University of Rennes, France

SDR platform integration flows

Integration results of IEEE 802.15.4 on Perseus 6010 platform

IEEE 802.1.4 experience feedback

FPGA design from high level specifications

Key issues : - specific development methodology allowing the

flexibility of high-level specifications,- a modular platform supporting various waveforms.

In this paper:- Nutaq Perseus platform experience - Integration with high-level synthesis design

Transmitter Receiver

Slices FF LUT Slices FF LUT

HC-VHDL 35 134 86 3668 4292 10945

HLS-VHDL 76 188 202 590 1200 1595

DSL: Synchronous Data Flow with controller

Block-level specification using library (C++/VHDL blocks)

Integration using Vivado (ISE) design suite

New methodology: from high level specifications to FPGA integration

We compare:

Two VHDL design flows:- HLS flow from C-language

specification (CatapultC)- Hand-coded VHDL design

Perseus 6010 development tools:- MBDK: Matlab Simulink GUI tool- BSDK: Script based tool

Transmitted baseband signals in Chip-scope Received baseband signals in Chip-scope

Resource estimation of IEEE 802.15.4 transmitter designs

HLS-VHDL Modulated spectrumWorking test bench Perseus

Nutaq Perseus 6010 board- Virtex-6 FPGA- Development tools- Mezzanine add-on cards

Nutaq Radio420X FPGA mezzanine card- SISO full duplex RF transceiver- Wide frequency range: 300 MHz - 3 GHz- Selectable bandwidth: 1.5 - 28 MHz- 12 bits and 40 MBPS (DAC and ADC)

The Nutaq platform

IEEE 802.15.4 transceiver

Dev. time Design space exploration

RTL control

HC-VHDL - - +

HLS-VHDL + + -

Dev. time User-friendlyinterface

Licence depedency

Hardwarecontrol

MBDK + + -- -

BSDK - - + +

Wav

efor

m

desi

gnD

omai

n-sp

ecifi

c la

ngua

ge

RTL merging Third-partyblocks

Library

IP 1 IP 2 IP N-1

IP_x.cpp IP_x_v1.vhd

Waveform description language

Multi-rate framer

.tcl

IP N

HLS tools

.tcl

IP loading

.tcl .tcl

.cpp

.vhd

Framer design

Platf

orm

in

tegr

ation

To FPGA

Bitstream generation

.vhd .vhd

.vhd

.vhd

.bit

Design constraints

HLS tools

IP loading

.vhd .vhd

N IP_x_v2.vhd IP_x_v3.vhd

SDR high-level specifications

Hand-coded VHDL

C/C++

HLS tools

High Level Synthesis

Sript based tools

Graphical User Interface tools

Bit stream

VHD

L de

sign

FPG

A in

tegr

ation

Algo

rithm

To FPGA