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Floating point Data processing instructions

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Th e ARM floating-point arc h itecture presents: An interpretation of t h e coprocessor instruction set w h en t h e coprocessor

number is 1 or 2. ( Th e floating-point system uses two logical coprocessornumbers.)

Eigh t 80-bit floating-point registers in coprocessors 1 and 2 (t h e sameph ysical registers appear in bot h logical coprocessors).

A user-visible floating-point status register (FPSR) w h ich controls variousoperating options and indicates error conditions.

Optionally, a floating-point control register (FPCR) w h ich is user-invisible

and s h ould be used only by t h e support software specific to t h e h ardwareaccelerator.

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Th e coprocessor pipeline followerTh e load/store unit t h at carries out formatconversion on floating-point data typesas t h ey are loaded from and stored to memory.Th e register bank w h ich stores eig h t 80-bitextended precision floating-point operands.

Th e arit h metic unit w h ich incorporates an adder,a multiplier and a divider,toget h er wit h roundingand normalizing h ardware.

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FPA10 Organization

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U se of Memory

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Run time environmentDivision and remainder functions.

Since t h e ARM instruction set does not include divide instructions, t h ese areimplemented as library functions.

Stack-limit c h ecking functions.A minimal embedded system is unlikely to h ave memory management h ardwareavailable for stack overflow detection; t h erefore t h ese library functions are

needed to ensure programs operate safely.

Stack and h eap management.All C programs use t h e stack for (many) function calls, and all but t h e most trivialcreate data structures on t h e h eap.

Program start up.Once t h e stack and h eap are initialized, t h e program starts wit h a call to main ().

Program termination.Most programs terminate by calling _exit (); even a program w h ich runs foreversh ould terminate if an error is detected.

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ARM memory system

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DRAM memory organization

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ARM address register structure

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DRAM timing diagram

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Tming diagram

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Overview of the AMBA specification

Th e Advanced Microcontroller Bus Architecture (AMBA) specificationdefines an onchip communications standard for designing h igh -performance embedded microcontrollers.

Th ree distinct buses are defined wit h in t h e AMBA specification: th e Advanced High-performance Bus (AHB) th e Advanced System Bus (ASB) th e Advanced Peripheral Bus (APB).

A test met h odology is included wit h th e AMBA specification w h ich

provides an infrastructure for modular macrocell test and diagnosticaccess.

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Objectives of the AMBA specification

Th e AMBA specification h as been derived to satisfy four key requirements:

to facilitate t h e right-first-time development of embedded microcontroller products wit h one or more CP U s or signal processors

to be technology-independent and ensure that highly reusable peripheral and system macrocells canbe migrated across a diverse range of IC processes and be appropriate for full-custom, standard celland gate array tec h nologies

to encourage modular system design to improve processor independence,providing a development road-map for advanced cac h ed CP U cores and t h e development of perip h eral libraries

to minimize t h e silicon infrastructure required to support efficient on-c h ip and off-c h ipcommunication for bot h operation and manufacturing test.

AMBAh as been proven in and is being designed into:

PDA microcontrollers, wit h a h igh number of integrated perip h erals but also wit h very low powerconsumption

multi-media microcontrollers wit h floating-point co-processors, on-c h ip video controller and h igh memory bandwidt h

complex perip h eral ASICs for consumer products digital mobile communication devices integrating control and signal-processing functions

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A typical AMBA-based microcontroller

In order to ac h ieve t h eabove, t h e arc h itectureh as t h e key features of:

h igh ly modularity

multi-master support

low-power emp h asis

innovative testmet h odology

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Th e Advanced Microcontroller Bus Arc h itecture (AMBA)

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Bus Transfer steps

Th e bus clock, BCLK. This will usually be the same as mclk, the ARM processor clock.Th e bus master w h ich h olds t h e grant t h en proceeds wit h th e bus transactionusing t h e following signals:

Bus transaction, BTRAN[1:0], indicates whether the next bus cycle will beaddress-only, sequential or non-sequential. It is enabled by t h e grant signal and isah ead of t h e bus cycle to w h ich it refers.

Th e address bus, BA[31:OJ. (Not all address lines need be implemented in systems wit h modest address-space requirements, and in a multiplexed implementation t h e address is sent down t h e data bus.)

Bus transfer direction, BWRITE. Bus protection signals, BPROT[1:0], which indicate instruction or data fetches

and supervisor or user access.Th

e transfer size, BSIZE[1:0], specifies a byte, half-word or word transfer. Bus lock, BLOK, allows a master to retain the bus to complete an atomic readmodify-write transaction.

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Th e data bus, BD[31:0], used to transmit write data and to receive read data. In animplementation wit h multiplexed address and data, t h e address is also transmitteddown t h is bus.

A slave unit may process t h e requested transaction immediately, accepting write

data or issuing read data on ED[31:0], or signal one of the following responses:

Bus wait, BWAIT, allows a slave module to insert wait states when it cannot complete t h e transaction in t h e current cycle.

Bus last, BLAST, allows a slave to terminate a sequential burst to force the busmaster to issue a new bus transaction request to continue.

Bus error, BERROR, indicates a transaction that cannot be completed. If themaster is a processor it s h ould abort t h e transfer.

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H ardware system prototyping tools

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JTAG boundary scan register