flexray communications system protocol …e2...flexray protocol conformance test specification...

FlexRay Communications System

Protocol Conformance Test Specification

Version 3.0.1

FlexRay Protocol Conformance Test Specification

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This specification and the material contained in it, as released by the FlexRay Consortium, is for the purpose of information only. The FlexRay Consortium and the companies that have contributed to it shall not be liable for any use of the specification.

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This specification may be utilized or reproduced without any modification, in any form or by any means, for informational purposes only. For any other purpose, no part of the specification may be utilized or reproduced, in any form or by any means, without permission in writing from the publisher.

Important Information

1. The FlexRay specifications V2.1 and V3.0.1 and the corresponding FlexRay Conformance Test specifications (hereinafter together "FlexRay specifications") have been developed for automotive applications only. They have neither been developed nor tested for non-automotive applications.

2. The FlexRay specifications are retrievable on the FlexRay Website www.flexray.com for information purposes only and without obligation.

3. The technical expertise provided in the FlexRay specifications is subject to continuous further development. The FlexRay specifications serve exclusively as an information source to enable to manufacture and test products which comply with the FlexRay specifications ("FlexRay compliant products"). Observation of the FlexRay specifications does neither guarantee the operability and safety of the FlexRay compliant products, nor does it guarantee the safe cooperation of multiple FlexRay compliant products with each other or with other products. Therefore, the members of the former FlexRay Consortium are not able to assume liability for the operability and safety of such products and the safe cooperation of multiple FlexRay compliant products with each other or with other products.

4. The FlexRay specifications V3.0.1 were submitted to ISO in order to be published as a standard for road vehicles.

The word FlexRay and the FlexRay logo are registered trademarks.

Copyright 2006 - 2010. All rights reserved.

The Core Partners of the FlexRay Consortium are Adam Opel GmbH, Bayerische Motoren Werke AG, Daimler AG, Freescale Halbleiter Deutschland GmbH, NXP B.V., Robert Bosch GmbH and Volkswagen AG.

Version 3.0.1 October 2010 Page 2 of 806

http://www.flexray.com/


Table of Contents1 Introduction.........................................................................................................................................................13

1.1 References...................................................................................................................................................131.2 Revision History.........................................................................................................................................131.3 Acronyms, Abbreviations and Notational Conventions..............................................................................131.4 Scope...........................................................................................................................................................141.5 Test Architecture.........................................................................................................................................141.6 Test Implementation...................................................................................................................................16

1.6.1 Hardware-based Test Implementation................................................................................................161.6.1.1 Lower Tester..............................................................................................................................161.6.1.2 Clock Synchronization..............................................................................................................16

1.6.2 Simulation-based Test Implementation..............................................................................................171.7 Internal RX Delay.......................................................................................................................................181.8 Analog Delays.............................................................................................................................................181.9 Accepted Deviations...................................................................................................................................181.10 Testability Requirements..........................................................................................................................20

1.10.1 CHI Delay Constraints.....................................................................................................................201.10.2 Consequences for Interpretation of Test Steps.................................................................................221.10.3 Special Handling of vMacrotick Counter........................................................................................22

1.11 Test Execution...........................................................................................................................................221.11.1 Single Channel CC...........................................................................................................................221.11.2 Dual Channel CC.............................................................................................................................221.11.3 Optional TT-E Feature......................................................................................................................221.11.4 Notes on Sections 2.4 and 2.5..........................................................................................................231.11.5 Basic Configurations........................................................................................................................231.11.6 Modifications, Variants, Instances...................................................................................................23

2 Test......................................................................................................................................................................242.1 General Statements.....................................................................................................................................24

2.1.1 Test Case Structure.............................................................................................................................272.2 Receive Data...............................................................................................................................................30

2.2.1 Static Segment....................................................................................................................................302.2.1.1 TSS............................................................................................................................................302.2.1.2 Reserved Bit..............................................................................................................................322.2.1.3 Payload Preamble Indicator.......................................................................................................332.2.1.4 Null Frame Indicator.................................................................................................................342.2.1.5 Sync Frame Indicator................................................................................................................352.2.1.6 Startup Frame Indicator.............................................................................................................382.2.1.7 Frame ID....................................................................................................................................392.2.1.8 Payload Length..........................................................................................................................402.2.1.9 Cycle Count...............................................................................................................................422.2.1.10 Header CRC............................................................................................................................432.2.1.11 FSS/BSS..................................................................................................................................442.2.1.12 Payload....................................................................................................................................462.2.1.13 BSS..........................................................................................................................................472.2.1.14 Frame CRC..............................................................................................................................482.2.1.15 FES..........................................................................................................................................492.2.1.16 MTS.........................................................................................................................................502.2.1.17 WUP........................................................................................................................................512.2.1.18 Complete Valid Frame.............................................................................................................522.2.1.19 Complete Valid Frame Too Late..............................................................................................532.2.1.20 Complete Valid Frame Too Late Reaching Dynamic Segment...............................................552.2.1.21 More Than One Frame Within One Slot.................................................................................562.2.1.22 Complete Frame With Glitch..................................................................................................602.2.1.23 Noise........................................................................................................................................632.2.1.24 Channel Idle Delimiter............................................................................................................642.2.1.25 Channel Idle After Transmission.............................................................................................652.2.1.26 Falling Edge Within Payload Bit.............................................................................................662.2.1.27 Channel Specific Slot Status Indication..................................................................................672.2.1.28 Modified BSS..........................................................................................................................70



2.2.1.29 Startup Frame Status For Startup Node...................................................................................712.2.1.30 Startup Frame Status For Integrating Node.............................................................................722.2.1.31 Slot Status Indication And Slot Status Updated Indicator.......................................................732.2.1.32 Channel Aligned Startup Frame Status For Startup Node.......................................................752.2.1.33 Receive Valid Frame Within A Transmission slot...................................................................772.2.1.34 Aggregated channel status.......................................................................................................79

2.2.2 Dynamic Segment..............................................................................................................................812.2.2.1 TSS............................................................................................................................................812.2.2.2 Reserved Bit..............................................................................................................................832.2.2.3 Payload Preamble Indicator.......................................................................................................842.2.2.4 Null Frame Indicator.................................................................................................................852.2.2.5 Sync Frame Indicator................................................................................................................862.2.2.6 Startup Frame Indicator.............................................................................................................872.2.2.7 Frame ID....................................................................................................................................882.2.2.8 Payload Length..........................................................................................................................892.2.2.9 Cycle Count...............................................................................................................................902.2.2.10 Header CRC............................................................................................................................912.2.2.11 FSS/BSS..................................................................................................................................922.2.2.12 Payload....................................................................................................................................932.2.2.13 BSS..........................................................................................................................................942.2.2.14 Frame CRC..............................................................................................................................952.2.2.15 FES..........................................................................................................................................962.2.2.16 DTS.........................................................................................................................................972.2.2.17 MTS.........................................................................................................................................982.2.2.18 WUP........................................................................................................................................992.2.2.19 Complete Valid Frame...........................................................................................................1002.2.2.20 Complete Valid Frame Too Late Reaching Symbol Window................................................1012.2.2.21 Complete Valid Frame Too Late Reaching NIT....................................................................1032.2.2.22 Noise......................................................................................................................................1052.2.2.23 Channel Idle After Transmission...........................................................................................1062.2.2.24 Dynamic Frame Starting In The Dynamic Segment Offset..................................................1082.2.2.25 Noise Before Transmitted Dynamic Frame...........................................................................1092.2.2.26 Independent Nature Of The Dynamic Segment....................................................................110

2.2.3 Symbol Window...............................................................................................................................1122.2.3.1 MTS.........................................................................................................................................1122.2.3.2 Two MTS Within Symbol Window.........................................................................................1142.2.3.3 Complete Syntactically Correct Frame Within Symbol Window............................................1162.2.3.4 Complete Syntactically Correct Frame Reaching NIT............................................................1172.2.3.5 Wakeup Decoding....................................................................................................................1192.2.3.6 Noise........................................................................................................................................1222.2.3.7 Three MTS Within Symbol Window.......................................................................................1232.2.3.8 WUDOP Reception.................................................................................................................125

2.2.4 Network Idle Time...........................................................................................................................1282.2.4.1 Complete Syntactically Correct Frame Within NIT................................................................1282.2.4.2 Complete Syntactically Correct Frame Reaching Static Segment..........................................1292.2.4.3 MTS.........................................................................................................................................1302.2.4.4 Wakeup Decoding....................................................................................................................1312.2.4.5 Noise........................................................................................................................................133

2.3 CHI...........................................................................................................................................................1342.3.1 Timing Related Configuration Data.................................................................................................134

2.3.1.1 pMicroPerCycle.......................................................................................................................1342.3.1.2 gMacroPerCycle......................................................................................................................1362.3.1.3 gNumberOfStaticSlots.............................................................................................................1392.3.1.4 gdStaticSlot.............................................................................................................................1412.3.1.5 gdActionPointOffset................................................................................................................1442.3.1.6 gdMinislot...............................................................................................................................1472.3.1.7 gNumberOfMinislots...............................................................................................................1502.3.1.8 pLatestTx.................................................................................................................................1532.3.1.9 gdMinislotActionPointOffset..................................................................................................1562.3.1.10 gdDynamicSlotIdlePhase......................................................................................................158



2.3.1.11 gdSymbolWindow.................................................................................................................1602.3.1.12 pLatestTx Violation...............................................................................................................1622.3.1.13 gdSymbolWindowActionPointOffset....................................................................................163

2.3.2 Protocol Operation Related Configuration Data..............................................................................1642.3.2.1 gColdstartAttempts..................................................................................................................1642.3.2.2 gListenNoise............................................................................................................................1652.3.2.3 pdListenTimeout......................................................................................................................1662.3.2.4 pMacroInitialOffset.................................................................................................................1692.3.2.5 pRateCorrectionOut During Startup (1)..................................................................................1722.3.2.6 pRateCorrectionOut During Startup (2)..................................................................................1752.3.2.7 pMicroInitialOffset[A]............................................................................................................1782.3.2.8 pMicroInitialOffset[B]............................................................................................................1812.3.2.9 pdAcceptedStartupRange........................................................................................................1842.3.2.10 pChannels..............................................................................................................................1872.3.2.11 pWakeupChannel...................................................................................................................1882.3.2.12 pKeySlotOnlyEnabled (1).....................................................................................................1892.3.2.13 pKeySlotOnlyEnabled (2).....................................................................................................1912.3.2.14 pKeySlotID............................................................................................................................1922.3.2.15 pKeySlotUsedForSync..........................................................................................................1952.3.2.16 pKeySlotUsedForStartup.......................................................................................................1962.3.2.17 pDecodingCorrection............................................................................................................1972.3.2.18 pDelayCompensation............................................................................................................1992.3.2.19 pKeySlotOnlyEnabled (3).....................................................................................................2012.3.2.20 pdListenTimeout And Startup Frame Reception...................................................................2022.3.2.21 pOffsetCorrectionOut............................................................................................................2052.3.2.22 pRateCorrectionOut...............................................................................................................2082.3.2.23 pSecondKeySlotID and pTwoKeySlotMode.........................................................................2112.3.2.24 pKeySlotID = 0.....................................................................................................................2142.3.2.25 External Rate and Offset Correction (TT-L Mode)...............................................................215

2.3.3 Frame Related Configuration Data..................................................................................................2172.3.3.1 gPayloadLengthStatic..............................................................................................................2172.3.3.2 gdTSSTransmitter....................................................................................................................218

2.3.4 Symbol Related Configuration Data................................................................................................2202.3.4.1 gdWakeupTxIdle.....................................................................................................................2202.3.4.2 gdWakeupTxActive.................................................................................................................2212.3.4.3 pWakeupPattern.......................................................................................................................2222.3.4.4 pWakeupPattern < 2................................................................................................................2232.3.4.5 Intentional Prevention Of CAS Reception..............................................................................224

2.3.5 Control Of Protocol Operation Control...........................................................................................2262.3.5.1 POC:default config..................................................................................................................226

2.3.5.1.1 Command CONFIG........................................................................................................2262.3.5.1.2 Command FREEZE........................................................................................................2282.3.5.1.3 Command DEFERRED_HALT......................................................................................229

2.3.5.2 POC:config..............................................................................................................................2302.3.5.2.1 Command CONFIG_COMPLETE.................................................................................2302.3.5.2.2 Command FREEZE........................................................................................................2312.3.5.2.3 Command DEFERRED_HALT......................................................................................232

2.3.5.3 POC:ready...............................................................................................................................2332.3.5.3.1 Command CONFIG........................................................................................................2332.3.5.3.2 Command RUN..............................................................................................................2342.3.5.3.3 Command WAKEUP......................................................................................................2352.3.5.3.4 Command FREEZE........................................................................................................2362.3.5.3.5 Command DEFERRED_HALT......................................................................................2372.3.5.3.6 Command ALLOW_COLDSTART...............................................................................238

2.3.5.4 POC startup states...................................................................................................................2392.3.5.5 POC:normal active..................................................................................................................240

2.3.5.5.1 Command IMMEDIATE_READY And Received WUDOP.........................................2402.3.5.5.2 Command DEFERRED_HALT - Command CLEAR_DEFERRED.............................2422.3.5.5.3 Command FREEZE........................................................................................................2442.3.5.5.4 Command ALL_SLOTS.................................................................................................245



2.3.5.5.5 Command DEFERRED_READY - Command CLEAR_DEFERRED..........................2462.3.5.6 POC:normal passive................................................................................................................248

2.3.5.6.1 Command IMMEDIATE_READY And Received WUDOP.........................................2482.3.5.6.2 Command DEFERRED_HALT - Command CLEAR_DEFERRED.............................2502.3.5.6.3 Command FREEZE........................................................................................................2522.3.5.6.4 Command ALL_SLOTS ................................................................................................2532.3.5.6.5 Command DEFERRED_READY - Command CLEAR_DEFERRED..........................255

2.3.5.7 POC:wakeup listen..................................................................................................................2572.3.5.7.1 Command IMMEDIATE_READY................................................................................2572.3.5.7.2 Command FREEZE........................................................................................................2592.3.5.7.3 Command DEFERRED_READY And Correct Wakeup Decoding...............................2602.3.5.7.4 Command DEFERRED_HALT......................................................................................262

2.3.5.8 POC:halt..................................................................................................................................2632.3.5.8.1 Command FREEZE........................................................................................................2632.3.5.8.2 Command DEFAULT_CONFIG....................................................................................264

2.3.5.9 POC:wakeup send...................................................................................................................2652.3.5.9.1 Command IMMEDIATE_READY................................................................................2652.3.5.9.2 Command FREEZE........................................................................................................2672.3.5.9.3 Command DEFERRED_READY - Command CLEAR_DEFERRED..........................2682.3.5.9.4 Command DEFERRED_HALT - Command CLEAR_DEFERRED.............................270

2.3.5.10 POC:wakeup detect...............................................................................................................2722.3.5.10.1 Command IMMEDIATE_READY..............................................................................2722.3.5.10.2 Command FREEZE......................................................................................................2742.3.5.10.3 Command DEFERRED_READY................................................................................2752.3.5.10.4 Command DEFERRED_HALT....................................................................................276

2.3.5.11 POC:coldstart listen...............................................................................................................2772.3.5.11.1 Command IMMEDIATE_READY...............................................................................2772.3.5.11.2 Command FREEZE......................................................................................................2792.3.5.11.3 Command DEFERRED_READY................................................................................2802.3.5.11.4 Command DEFERRED_HALT....................................................................................281

2.3.5.12 POC:coldstart collision resolution.........................................................................................2822.3.5.12.1 Command IMMEDIATE_READY..............................................................................2822.3.5.12.2 Command FREEZE......................................................................................................2842.3.5.12.3 Command DEFERRED_READY - Command CLEAR_DEFERRED........................2852.3.5.12.4 Command DEFERRED_HALT - Command CLEAR_DEFERRED...........................287

2.3.5.13 POC:coldstart consistency check..........................................................................................2892.3.5.13.1 Command IMMEDIATE_READY..............................................................................2892.3.5.13.2 Command FREEZE......................................................................................................2912.3.5.13.3 Command DEFERRED_READY - Command CLEAR_DEFERRED........................2922.3.5.13.4 Command DEFERRED_HALT - Command CLEAR_DEFERRED...........................294

2.3.5.14 POC:coldstart gap..................................................................................................................2962.3.5.14.1 Command IMMEDIATE_READY ..............................................................................2962.3.5.14.2 Command FREEZE......................................................................................................2982.3.5.14.3 Command DEFERRED_READY................................................................................2992.3.5.14.4 Command DEFERRED_HALT....................................................................................300

2.3.5.15 POC:initialize schedule.........................................................................................................3012.3.5.15.1 Command IMMEDIATE_READY..............................................................................3012.3.5.15.2 Command FREEZE......................................................................................................3032.3.5.15.3 Command ALLOW_COLDSTART.............................................................................3042.3.5.15.4 Command DEFERRED_READY................................................................................3052.3.5.15.5 Command DEFERRED_HALT....................................................................................306

2.3.5.16 POC:integration coldstart check............................................................................................3072.3.5.16.1 Command IMMEDIATE_READY..............................................................................3072.3.5.16.2 Command FREEZE......................................................................................................3092.3.5.16.3 Command DEFERRED_READY................................................................................3102.3.5.16.4 Command DEFERRED_HALT....................................................................................3112.3.5.16.5 Command ALLOW_COLDSTART.............................................................................312

2.3.5.17 POC:coldstart join.................................................................................................................3132.3.5.17.1 Command IMMEDIATE_READY..............................................................................3132.3.5.17.2 Command FREEZE......................................................................................................315



2.3.5.17.3 Command ALLOW_COLDSTART.............................................................................3162.3.5.17.4 Command DEFERRED_READY - Command CLEAR_DEFERRED........................3172.3.5.17.5 Command DEFERRED_HALT - Command CLEAR_DEFERRED...........................319

2.3.5.18 POC:integration listen...........................................................................................................3212.3.5.18.1 Command IMMEDIATE_READY..............................................................................3212.3.5.18.2 Command FREEZE......................................................................................................3222.3.5.18.3 Command ALLOW_COLDSTART.............................................................................3232.3.5.18.4 Command DEFERRED_READY................................................................................3242.3.5.18.5 Command DEFERRED_HALT....................................................................................325

2.3.5.19 POC:integration consistency check.......................................................................................3262.3.5.19.1 Command IMMEDIATE_READY..............................................................................3262.3.5.19.2 Command FREEZE......................................................................................................3282.3.5.19.3 Command DEFERRED_READY................................................................................3292.3.5.19.4 Command DEFERRED_HALT....................................................................................330

2.3.6 Control Of Symbol Transmission....................................................................................................3312.3.6.1 MTS Transmission..................................................................................................................3312.3.6.2 WUDOP Transmission............................................................................................................3322.3.6.3 Automatic WUDOP Transmission...........................................................................................3332.3.6.4 Request of WUDOP Transmission..........................................................................................3342.3.6.5 Request For MTS And WUDOP Transmission.......................................................................335

2.3.7 Control Of External Clock Correction.............................................................................................3362.3.7.1 External Offset Correction......................................................................................................3362.3.7.2 External Rate Correction.........................................................................................................338

2.3.8 Buffer Configuration........................................................................................................................3402.3.8.1 Transmit Buffer.......................................................................................................................340

2.3.8.1.1 Transmit Buffer Assignment On A Via Slot ID In The Static Segment..........................3402.3.8.1.2 Transmit Buffer Assignment On A Via Cycle Count In The Static Segment.................3412.3.8.1.3 Transmit Buffer Assignment On B Via Slot ID In The Static Segment..........................3422.3.8.1.4 Transmit Buffer Assignment On B Via Cycle Count In The Static Segment.................3432.3.8.1.5 Transmit Buffer Assignment On A&B Via Slot ID In The Static Segment....................3442.3.8.1.6 Transmit Buffer Assignment On A&B Via Cycle Count In The Static Segment...........3452.3.8.1.7 Transmit Buffer Assignment On A Via Slot ID In The Dynamic Segment....................3472.3.8.1.8 Transmit Buffer Assignment On A Via Cycle Count In The Dynamic Segment............3482.3.8.1.9 Transmit Buffer Assignment On B Via Slot ID In The Dynamic Segment....................3492.3.8.1.10 Transmit Buffer Assignment On B Via Cycle Count In The Dynamic Segment..........3502.3.8.1.11 Message Length............................................................................................................3512.3.8.1.12 Transmit Buffer Assignment In The Static and Dynamic Segment..............................3532.3.8.1.13 Payload Data Valid Flag...............................................................................................3542.3.8.1.14 Frame Transmitted Indicator.........................................................................................3552.3.8.1.15 Active Message Buffer Identification...........................................................................3562.3.8.1.16 Transmit Buffer Assignment Via Cycle Repetition and Cycle Offset..........................3582.3.8.1.17 Reception And Transmission In The Same Static Slot In Different Cycles.................359

2.3.8.2 Receive Buffer.........................................................................................................................3602.3.8.2.1 Receive Buffer Configuration By Slot And Channel In The Static Segment.................3602.3.8.2.2 Receive Buffer Configuration By Slot, Channel And Cycle In The Static Segment......3612.3.8.2.3 Receive Buffer Configuration With Specific Size In The Static Segment.....................3632.3.8.2.4 Receive Buffer Configuration By Slot And Channel In The Dynamic Segment...........3642.3.8.2.5 Receive Buffer Configuration By Slot, Channel And Cycle In The Dynamic Segment 3652.3.8.2.6 Receive Buffer Assignment Via Cycle Repetition and Cycle Offset..............................3662.3.8.2.7 Buffer Updated Flag In Frame Contents Data................................................................3682.3.8.2.8 Receiving Null And Non-Null Frame In The Same Slot On Different Channels...........369

2.3.8.3 Queued Receive Buffer...........................................................................................................3712.3.8.3.1 FIFO Frame Validity Admittance Criteria......................................................................3712.3.8.3.2 FIFO Channel Admittance Criteria.................................................................................3732.3.8.3.3 Received Frame Placed Into None-Queued Receive Buffer / FIFO Buffer...................3752.3.8.3.4 FIFO Cycle Counter Admittance Criteria.......................................................................3762.3.8.3.5 Non-queued Receive Buffer For Both Channels And FIFO Buffer...............................3772.3.8.3.6 FIFO Frame Identifier Admittance Criteria....................................................................3782.3.8.3.7 Configuration Of FIFO Admittance Criteria..................................................................3792.3.8.3.8 FIFO Access After Transition From Normal Passive.....................................................381



2.3.8.3.9 FIFO Access After Transition From Normal Active.......................................................3832.3.8.3.10 Queued Receive Buffer Performance...........................................................................384

2.3.8.4 Buffer Configuration Data Class 1 and Class 2.......................................................................3862.3.8.5 Slot Status Updated Indicator..................................................................................................3892.3.8.6 Payload Data Valid Flag..........................................................................................................390

2.3.9 Timer And Interrupt Service............................................................................................................3922.3.9.1 Cycle Count And Macrotick Timer (Repetitive Mode)...........................................................3922.3.9.2 Cycle Count And Macrotick Timer (Non-Repetitive Mode)...................................................3942.3.9.3 Macrotick Only Timer (Repetitive Mode)...............................................................................3952.3.9.4 Macrotick Only Timer (Non-repetitive Mode)........................................................................3962.3.9.5 Timer Activation And Deactivation.........................................................................................3972.3.9.6 Generation Of Interrupt Requests For Various Interrupt Sources...........................................400

2.3.10 Message ID And Network Management Vector.............................................................................4022.3.10.1 Message ID............................................................................................................................402

2.3.10.1.1 Message ID Transmission.............................................................................................4022.3.10.1.2 Message ID Reception And Filtering...........................................................................403

2.3.10.2 Network Management Vector................................................................................................4052.3.10.2.1 Network Management Vector Transmission.................................................................4052.3.10.2.2 Network Management Vector Length...........................................................................4062.3.10.2.3 Network Management Vector Update Time.................................................................408

2.4 Clock Synchronization..............................................................................................................................4102.4.1 Synchronization Process..................................................................................................................410

2.4.1.1 Offset Correction.....................................................................................................................4102.4.1.1.1 POC:normal active..........................................................................................................410

2.4.1.1.1.1 No Deviation (Startup Node).................................................................................4102.4.1.1.1.2 No Deviation (Integrating Node)...........................................................................4112.4.1.1.1.3 Deviation Inside Bounds (Startup Node)...............................................................4122.4.1.1.1.4 Deviation Inside Bounds (Integrating Node).........................................................4142.4.1.1.1.5 Different Deviation On Channel A&B Inside Bounds...........................................4162.4.1.1.1.6 Different Deviation Inside Bounds........................................................................4182.4.1.1.1.7 Deviation Outside Bounds (Halt Allowed)............................................................4202.4.1.1.1.8 Deviation Outside Bounds (Halt Not Allowed).....................................................4212.4.1.1.1.9 Missing Sync Frames (Sync Node, Halt Allowed)................................................4222.4.1.1.1.10 Missing Sync Frames (Sync Node, Halt Not Allowed).......................................4242.4.1.1.1.11 Missing Sync Frames (No Sync Node, Halt Allowed).........................................4262.4.1.1.1.12 Missing Sync Frames (No Sync Node, Halt Not Allowed).................................4282.4.1.1.1.13 Content Error In Sync Frames (Sync Node, Halt Not Allowed)..........................4302.4.1.1.1.14 Deviation Inside Bounds (Integrating Node, Single Startup Frame)...................4312.4.1.1.1.15 gSyncFrameIDCountMax....................................................................................4332.4.1.1.1.16 Missing Sync Frame And Deviation Outside Bounds (Halt Allowed)................4342.4.1.1.1.17 Maximum Macrotick Shortening.........................................................................4362.4.1.1.1.18 Additional Verification For Missing Sync Frames (Sync Node, Halt Allowed). .4382.4.1.1.1.19 Missing Sync Frames (Sync Node, Halt Allowed, Even Cycle)..........................4392.4.1.1.1.20 Missing Sync Frames (Sync Node, Halt Allowed, Odd Cycles).........................4412.4.1.1.1.21 Missing Sync Frames (No Sync Node, Halt Allowed, Even Cycle, Remain One Sync Frame).............................................................................................................................4432.4.1.1.1.22 Missing Sync Frames (No Sync Node, Halt Allowed, Odd Cycle, Remain One Sync Frame).............................................................................................................................445

2.4.1.1.2 POC:normal passive.......................................................................................................4472.4.1.1.2.1 Resynchronization (Transition To POC:normal active Allowed)..........................4472.4.1.1.2.2 Resynchronization (Transition To POC:normal active Not Allowed)...................4492.4.1.1.2.3 Resynchronization After Resumption Of Sync Frame Simulation (Transition To POC:normal active Allowed)...................................................................................................4512.4.1.1.2.4 Deviation Outside Bounds (Halt Allowed)............................................................4532.4.1.1.2.5 Resynchronization After Resumption Of Startup/Sync Frame Simulation (Integrating Node, Transition To POC:normal active Allowed)..............................................4552.4.1.1.2.6 Additional Verification For Resynchronization After Resumption Of Sync Frame Simulation (Transition To POC:normal active Allowed).........................................................457

2.4.1.2 Rate Correction........................................................................................................................4592.4.1.2.1 POC:normal active..........................................................................................................459



2.4.1.2.1.1 No Deviation (Startup Node).................................................................................4592.4.1.2.1.2 No Deviation (Integrating Node)...........................................................................4602.4.1.2.1.3 Deviation Inside Bounds (Startup Node)...............................................................4612.4.1.2.1.4 Deviation Inside Bounds (Integrating Node).........................................................4632.4.1.2.1.5 Cluster Drift Damping...........................................................................................4652.4.1.2.1.6 Different Deviation On Channel A&B...................................................................4682.4.1.2.1.7 Different Deviation Inside Bounds........................................................................4702.4.1.2.1.8 Deviation Outside Bounds (Transition To POC:halt Allowed)..............................4722.4.1.2.1.9 Deviation Outside Bounds (Transition To POC:halt Not Allowed).......................4742.4.1.2.1.10 Deviation Inside Bounds (Integrating Node, Single Startup Frame)...................4762.4.1.2.1.11 Missing Sync Frames (Sync Node, Halt Not Allowed).......................................4782.4.1.2.1.12 gSyncFrameIDCountMax (1)..............................................................................4802.4.1.2.1.13 gSyncFrameIDCountMax (2)..............................................................................481

2.4.1.2.2 POC:normal passive.......................................................................................................4822.4.1.2.2.1 Resynchronization (Transition To POC:normal active Allowed)..........................4822.4.1.2.2.2 Resynchronization (Transition To POC:normal active Not Allowed)...................484

2.4.2 Time Representation........................................................................................................................4862.4.2.1 Cycle Counter..........................................................................................................................4862.4.2.2 Macrotick Counter...................................................................................................................4872.4.2.3 Slot Counter and Cycle Counter In POC:normal passive.......................................................4892.4.2.4 Macrotick Counter In POC:normal passive............................................................................491

2.5 Wakeup.....................................................................................................................................................4922.5.1 Correct Wakeup Decoding...............................................................................................................4922.5.2 Wakeup Decoding With Receive Window Violation.......................................................................4942.5.3 Wakeup Decoding With Low Phase Violation.................................................................................4962.5.4 Wakeup Decoding Idle Phase Violation...........................................................................................4982.5.5 Wakeup Listen Without Noise..........................................................................................................4992.5.6 Wakeup Listen With Initial Noise Interference................................................................................5012.5.7 Wakeup Listen With Noise Interference..........................................................................................5032.5.8 Wakeup Listen With Enduring Noise Interference..........................................................................5052.5.9 Wakeup Listen With Symbol Interference (DC)..............................................................................5072.5.10 Wakeup Listen With Indirect Header Interference.........................................................................5092.5.11 Wakeup Listen With Direct Header Interference...........................................................................5102.5.12 Wakeup Listen With Indirect WUP Interference............................................................................5112.5.13 Wakeup Listen With Direct WUP Interference..............................................................................5132.5.14 WUP With Indirect Collision.........................................................................................................5152.5.15 WUP With WUP Collision.............................................................................................................5172.5.16 WUP With Header Collision..........................................................................................................5192.5.17 WUP With Unknown Collision......................................................................................................5212.5.18 WUP With Insignificant Collision.................................................................................................5232.5.19 Wakeup Listen And Permanent Noise On Available Channel(s) Longer Than tWakeupNoise.....5242.5.20 Wakeup Listen With Header Interference On Both Channels........................................................5262.5.21 Wakeup Listen With Symbol Interference On Both Channels.......................................................5282.5.22 Wakeup Listen With Symbol Interference (SC).............................................................................5302.5.23 WUP With Unknown Collision During Blind................................................................................5322.5.24 WUP With Insignificant Collision During Blind...........................................................................534

2.6 Startup.......................................................................................................................................................5362.6.1 Coldstart Listen................................................................................................................................536

2.6.1.1 Channel Idle............................................................................................................................5362.6.1.2 Permanent Noise On Single Channel......................................................................................5382.6.1.3 Permanent And Intermittent Noise..........................................................................................5402.6.1.4 Permanent Noise On Available Channel(s) Longer Than tStartupNoise................................5422.6.1.5 Permanent Noise On Available Channel(s) Shorter Than tStartupNoise................................5442.6.1.6 CE Start...................................................................................................................................5462.6.1.7 Header Reception (SC)............................................................................................................5482.6.1.8 CAS Reception (SC)...............................................................................................................5502.6.1.9 Startup Frame Reception.........................................................................................................5522.6.1.10 Header Reception (DC).........................................................................................................5542.6.1.11 CAS Reception (DC).............................................................................................................5562.6.1.12 Late Integration Into Running Cluster: Following Coldstarter.............................................558



2.6.1.13 Late Integration Into Running Cluster: Integrating Node.....................................................5602.6.1.14 Late Integration Into Running Cluster: WUDOP Reception.................................................5622.6.1.15 Late Integration Into Running Cluster: WUDOP Reception And Command IMMEDIATE_READY.......................................................................................................................564

2.6.2 Coldstart Collision Resolution.........................................................................................................5662.6.2.1 Channel Idle............................................................................................................................5662.6.2.2 Header Reception....................................................................................................................5682.6.2.3 CAS Reception........................................................................................................................5702.6.2.4 Parallel Startup (CAS Collision): IUT As Leading Coldstarter..............................................5722.6.2.5 Parallel Startup (CAS Collision): IUT As Following Coldstarter...........................................574

2.6.3 Coldstart Consistency Check...........................................................................................................5762.6.3.1 Channel Idle Until Last Coldstart Attempt..............................................................................5762.6.3.2 Channel Idle............................................................................................................................5782.6.3.3 No Startup Frames In Second Cycle.......................................................................................5802.6.3.4 Deviation Outside Bounds.......................................................................................................5822.6.3.5 Less Startup Frames In Second Cycle.....................................................................................5842.6.3.6 Number Of Startup Frames.....................................................................................................5862.6.3.7 Short Noise during Coldstart Consistency Check...................................................................588

2.6.4 Coldstart Gap...................................................................................................................................5902.6.4.1 Header Reception....................................................................................................................5902.6.4.2 CAS Reception........................................................................................................................592

2.6.5 Integration Listen.............................................................................................................................5942.6.5.1 ALLOW_COLDSTART Command (Coldstarter)...................................................................5942.6.5.2 ALLOW_COLDSTART Command (Integrating Node).........................................................5962.6.5.3 Wait For Startup.......................................................................................................................5972.6.5.4 Invalid Startup Frame Reception.............................................................................................599

2.6.6 Initialize Schedule............................................................................................................................6012.6.6.1 Startup Frame Reception (Coldstarter)....................................................................................6012.6.6.2 Startup Frame Reception (Integrating Node)..........................................................................6032.6.6.3 Missing, Incomplete, Or Too Early Startup Frame (Integrating Node)...................................6052.6.6.4 Missing Startup Frame On One Channel................................................................................607 2.6.6.5 Missing, Incomplete, Or Too Early Startup Frame (Following Coldstarter)..........................609

2.6.7 Integration Coldstart Check.............................................................................................................6112.6.7.1 One Startup Frame Per Cycle..................................................................................................6112.6.7.2 Receive Sync Frames But No Startup Frames........................................................................6132.6.7.3 Startup Frames.........................................................................................................................6152.6.7.4 Startup Frame Missing In Reference Slot...............................................................................6172.6.7.5 Missing Or Incomplete Startup Frame....................................................................................6192.6.7.6 Deviation Outside Bounds.......................................................................................................6212.6.7.7 ALLOW_COLDSTART Command........................................................................................623

2.6.8 Coldstart Join...................................................................................................................................6252.6.8.1 Missing Or Incomplete Startup Frame....................................................................................6252.6.8.2 Startup Frames.........................................................................................................................6272.6.8.3 Deviation Outside Bounds.......................................................................................................629

2.6.9 Integration Consistency Check........................................................................................................6312.6.9.1 Deviation Exceeds Clock Correction Bounds.........................................................................6312.6.9.2 Missing Or Incomplete Startup Frames...................................................................................6332.6.9.3 Sync Frames............................................................................................................................6352.6.9.4 Single Startup Frame Or Incomplete Second Startup Frame..................................................6372.6.9.5 Integration Into Starting Cluster..............................................................................................6392.6.9.6 Integration Into Running Cluster.............................................................................................6412.6.9.7 Startup Frame Missing In Reference Slot...............................................................................6432.6.9.8 Integration Into Running Cluster With Missing Startup Frame..............................................645

2.7 Miscellaneous...........................................................................................................................................6472.7.1 Transmission Conflict In Static Segment.........................................................................................6472.7.2 Transmission Conflict In Symbol Window......................................................................................6502.7.3 Traffic In Transmission Slot.............................................................................................................6522.7.4 Clock Sync Startup...........................................................................................................................654

2.7.4.1 Second Startup Frame Missing (1)..........................................................................................6542.7.4.2 Second Startup Frame With Wrong Cycle Count....................................................................656



2.7.4.3 Second Startup Frame In Earlier Slot......................................................................................6572.7.4.4 Sync Frame Counting..............................................................................................................6592.7.4.5 Sync Frame Overflow.............................................................................................................6612.7.4.6 Second Startup Frame Too Late..............................................................................................6632.7.4.7 Clock Synchronization Startup Abortion (1)...........................................................................6652.7.4.8 Clock Synchronization Startup Abortion (2)...........................................................................6672.7.4.9 Clock Synchronization Startup Retrigger................................................................................6692.7.4.10 Startup Frames Violate Accepted Startup Range In Odd Cycle............................................6712.7.4.11 Second Startup Frame Missing (2)........................................................................................6732.7.4.12 Second Valid Startup Frame Too Early.................................................................................6752.7.4.13 Second Odd Startup Frame Too Late....................................................................................677

2.7.5 Frame Format...................................................................................................................................6792.7.6 Transmission Across Slot Boundary Violation................................................................................6822.7.7 Clock Correction Failed Counter Reset In POC:normal active.......................................................6852.7.8 WUDOP Transmission Across Symbol Window Boundary............................................................6862.7.9 Dynamic Segment Robustness.........................................................................................................687

2.7.9.1 Resynchronization Attempt After Single Short Noise.............................................................6872.7.9.2 Resynchronization Attempt After Multiple Short Noise.........................................................6902.7.9.3 Short Noise In Consecutive Minislots (1)...............................................................................6922.7.9.4 Short Noise In Consecutive Minislots (2)...............................................................................6942.7.9.5 Resynchronization Attempt Before Frame Reception (1).......................................................6962.7.9.6 Resynchronization Attempt Before Frame Reception (2).......................................................6982.7.9.7 Resynchronization Attempt Before Frame Reception (3).......................................................7002.7.9.8 Valid Frame Reception After Noise.........................................................................................7022.7.9.9 Frame Reception During Noise (1).........................................................................................7042.7.9.10 Frame Reception During Noise (2).......................................................................................7062.7.9.11 Noise After Frame Reception................................................................................................7082.7.9.12 Frame Transmission After Noise Crossing Segment Boundary............................................7112.7.9.13 Frame Reception After Noise Crossing Segment Boundary.................................................7142.7.9.14 Resynchronization Attempt After Single Short Noise Detected After Valid Frame Reception (1)........................................................................................................................................................7162.7.9.15 Resynchronization Attempt After Single Short Noise Detected After Valid Frame Reception (2)........................................................................................................................................................7232.7.9.16 Resynchronization Attempt After Single Short Noise Detected After Valid Frame Reception (3)........................................................................................................................................................7302.7.9.17 Frame Transmission After Single Short Noise Detected After Valid Frame Reception (1). .7362.7.9.18 Frame Transmission After Single Short Noise Detected After Valid Frame Reception (2). .7412.7.9.19 Frame Transmission After Single Short Noise Detected After Valid Frame Reception (3). .7472.7.9.20 Frame Transmission After Single Short Noise Detected After Valid Frame Reception (4). .7512.7.9.21 Frame Transmission After Single Short Noise Detected After Valid Frame Reception (5). .7542.7.9.22 Frame Transmission After Single Short Noise Detected After Valid Frame Reception (6). .760

2.7.10 Transmission Conflict In The Static And Dynamic Segment........................................................7652.7.11 Transmission Conflict In The Symbol Window.............................................................................768

2.8 Optional TT-E Feature..............................................................................................................................7702.8.1 CHI...................................................................................................................................................770

2.8.1.1 Independent behavior of gateway source and gateway sink...................................................7702.8.2 Clock Synchronization.....................................................................................................................772

2.8.2.1 Cycle Start Supervision...........................................................................................................7722.8.2.2 Offset Correction Inside Bounds.............................................................................................7742.8.2.3 Offset Correction Outside Bounds..........................................................................................7762.8.2.4 Rate Correction Inside Bounds................................................................................................7782.8.2.5 Rate Correction Outside Bounds.............................................................................................780

2.8.3 Startup..............................................................................................................................................7822.8.3.1 External Startup (1).................................................................................................................7822.8.3.2 External Startup (2).................................................................................................................784

2.8.4 Control Of Protocol Operation Control...........................................................................................7862.8.4.1 Command IMMEDIATE_READY.........................................................................................7862.8.4.2 Command FREEZE.................................................................................................................7872.8.4.3 Command DEFERRED_READY...........................................................................................7882.8.4.4 Command DEFERRED_HALT..............................................................................................789



2.9 Preambles..................................................................................................................................................7902.9.1 Preamble I........................................................................................................................................7902.9.2 Preamble II.......................................................................................................................................7922.9.3 Preamble III......................................................................................................................................7942.9.4 Preamble IV.....................................................................................................................................796

3 Configuration.....................................................................................................................................................7983.1 Basic Configuration..................................................................................................................................7983.2 Standard Modifications.............................................................................................................................801

3.2.1 Standard Modification Set 1............................................................................................................8013.2.2 Standard Modification Set 2............................................................................................................802

4 Static Test Cases................................................................................................................................................8034.1 Electrical Interface....................................................................................................................................8034.2 Protocol Parameter....................................................................................................................................805



1 Introduction

1.1 References[PS10] FlexRay Communications System Protocol Specification, Version 3.0.1, FlexRay Consortium,

October 2010.[EPL10] FlexRay Communications System Electrical Physical Layer Specification, Version 3.0.1, FlexRay

Consortium, October 2010.

1.2 Revision History

Version Date Comment

before 3.0.1

N/A For Protocol Specification Version 2.1 and 2.1 Rev A

3.0.1 October 2010 Official version for Protocol Specification Version 3.0.1

1.3 Acronyms, Abbreviations and Notational ConventionsT MicrotickT gdSampleClockPeriod (= Sampletick)BD Bus DriverBSS Byte Start SequenceCAS Collision Avoidance SymbolCC Communication ControllerCE Communication ElementCHI Controller Host InterfaceCHIRP Channel Idle Recognition PointCRC Cyclic Redundancy CodeDC Dual ChannelDTS Dynamic Trailing SequenceFES Frame End SequenceFIFO First In First OutFSS Frame Start SequenceID IdentifierIUT Implementation Under TestLT Lower TesterMT MacrotickMTS Media Access Test SymbolNIT Network Idle TimeNM Network ManagementPE Protocol EnginePOC Protocol Operation ControlRxD Receive data signal from bus driverSC Single ChannelTE Test ExecutionTSS Transmission Start SequenceTT-E Time triggered externalTT-D Time triggered distributedTxD Transmit Data signal from CCTxEN Transmit Data Enable Not signal from CCUT Upper TesterWUDOP Wakeup During Operation PatternWUP Wakeup PatternWUS Wakeup SymboltRC Modification of cycle length due to calculated rate correction



(equal to zRateCorrection, used in figures of Section 2.4)tOC Modification of cycle length due to calculated offset correction

(equal to zOffsetCorrection, used in figures of Section 2.4)Rx, Tx Analog delays (see Section 1.8), IUT Allowed deviation from theoretical results due to LT-IUT jitter

(see Section 1.9)

TruncateTowardsZero This function returns the integer part of a number without its fractionaldigits (= sign(x) * floor(|x|)).

POC states:C POC:configCSCC POC:coldstart consistency checkCSCR POC:coldstart collision resolutionCSG POC:coldstart gapCSJ POC:coldstart joinCSL POC:coldstart listenDC POC:default configH POC:haltICC POC:integration consistency checkICSC POC:integration coldstart checkIL POC:integration listenIS POC:initialize scheduleNA POC:normal activeNP POC:normal passiveR POC:ready

For Notational Conventions refer to [PS10] and [EPL10].

1.4 ScopeThis FlexRay Protocol Conformance Test Specification Version 3.0.1 lists a set of test cases, which verify the conformance of FlexRay communication controllers with respect to the FlexRay Protocol Specification Version 3.0.1 [PS10].

This FlexRay Protocol Conformance Test Specification Version 3.0.1 is not applicable for FlexRay communication controllers which follow the FlexRay Protocol Specification Version 2.1 or 2.1 Rev A only.

Please note that some testability requirements are given in the following Sections 1.6.1.2 and 1.10, which shall be considered by FlexRay communication controllers in order to be able to pass the test cases.

1.5 Test ArchitectureThe FlexRay conformance test specification is based on a test architecture as shown in Figure 1, which follows the ISO 9646 standard. The implementation under test (IUT) is the FlexRay CC. The upper tester (UT) is connected to the FlexRay controller host interface (CHI) of the IUT and the CHI is device specific. The lower tester (LT) is connected to the FlexRay physical layer interface of the IUT and the FlexRay Electrical Physical Layer specification [EPL10] describes this interface. The test coordination procedure controls the UT and the LT.

In a hardware-based test environment (see Section 1.6.1), the FlexRay CC can be an embedded FlexRay CC meaning that CC is embedded in a microcontroller. In this case, the CHI (i.e., the upper tester interface) is between the embedded FlexRay CC and the microcontroller and in order to get access to the CHI, the upper tester may be partly distributed to the microcontroller.



The test architecture shown in Figure 1 is suitable for testing one FlexRay CC. However, there are some optional test cases in this specification which tests the optional TT-E feature by using a pair of FlexRay CCs, namely a source CC and a sink CC, which are connected via the time gateway interface. Here, the IUT is the pair of connected FlexRay CCs. To test the TT-E feature, the test architecture as shown in Figure 2 is proposed: The upper tester and lower tester are connected to both FlexRay CCs and the test coordination procedure controls the upper and lower testers.


Figure 1: Standard test architecture

Lower Tester

Test Coordination

Procedure

Upper Tester

CCIUT

Figure 2: Test architecture for the TT-E option

Lower TesterLower Tester

Test Coordination

ProcedureSource CC Sink CC

Upper TesterUpper Tester

IUT

Time Gateway Interface


1.6 Test ImplementationThe test cases and the proposed test architecture of this specification can be either implemented in a hardware-based environment, or in a simulation-based environment. In the following, both environments are described.

1.6.1 Hardware-based Test ImplementationIn a hardware-based test implementation, the IUT is a physical device. The IUT can be either a standalone FlexRay CC, an embedded FlexRay CC, or a FlexRay CC programmed in an FPGA (field programmable gate array). For testing the optional TT-E feature, the IUT consists of a pair of connected FlexRay CCs.

1.6.1.1 Lower TesterThe electrical characteristics of the lower tester shall follow the electrical characteristics of the interface between the FlexRay CC and the FlexRay Bus Driver on the Bus Driver side. This interface is described in the FlexRay Electrical Physical Layer Specification [EPL10]. The requirements on the lower tester in a hardware-based test environment, including the electrical characteristics, are listed in Table 1. It is not advised to use any extra circuits (e.g., level shifters) between the IUT's FlexRay CC and the lower tester.

Description Relevant signal

Parametername used in the EPL Spec V3.0.1

Min Max Unit

Input capacitance TxD, TxEN C_BDTxD - 10 pFThreshold for detecting logical high TxD, TxEN uBDLogic_1 - 60 %Threshold for detecting logical low TxD, TxEN uBDLogic_0 40 - %Voltage reference for logical high and low TxD, TxEN,

RxDuVDIG same as

IUTV

Sample Rate TxD, TxEN N/A 160 - MHzAsymmetry RxD see Table 6-5 and Figure 6-4 in

[EPL10]. Measured at 50% uVDIG and 25pF load.

- 2 ns

Sum of rise and fall time @ 15pF load RxD dBDRxDR15 + dBDRxDF15 - 13 nsDifference of rise and fall time @ 15pF load

RxD | dBDRxDR15 dBDRxDF15 |

- 5 ns

Sum of rise and fall time @ 25pF load RxD dBDRxDR25 + dBDRxDF25 - 16.5 nsDifference of rise and fall time @ 25pF load

RxD | dBDRxDR25 dBDRxDF25 |

- 5 ns

Frequency of FlexRay clock, provided to IUT

clk N/A - 80 MHz

Precision of FlexRay clock, provided to IUT

clk N/A - 500 ppm

Table 1: Requirements on the lower tester in a hardware-based test environment.

1.6.1.2 Clock SynchronizationSeveral test cases require the synchronization between the IUT and the test environment such that random clock deviations can be excluded and the occurrence time of a sampletick can be determined within one sampletick accuracy.Therefore it is required that the LT provides a clock signal (called FlexRay clock) to the IUT. The LT shall use the FlexRay clock as a basis for FlexRay bus stimuli of the RxD signal and for sampling the TxD and TxEN signals. The IUT shall also use the FlexRay clock for FlexRay transmission and reception. Existing PLLs in the IUT need to be bypassed or programmed not to multiply. However, if the IUT uses an own clock source or an active PLL, then there might be the risk of failing some test cases.Some requirements on the FlexRay clock signal are listed in Table 1. In addition, those frequencies shall be supported, which can be derived from 80 MHz by integer division. The FlexRay clock shall run continuously in



order to be able to test embedded FlexRay CCs, where the FlexRay clock signal is also used to for clocking the host microcontroller.

1.6.2 Simulation-based Test ImplementationIn a simulation-based test implementation, the IUT is described in a hardware description language typically on register transfer level (RTL), e.g., in SystemVerilog code or VHDL code. The IUT is a FlexRay CC, including message buffers and FIFO. For testing the optional TT-E feature, the IUT consists of a pair of connected FlexRay CCs. The test environment (upper tester, lower tester, and test coordination procedure) and the test cases exist as software only. Executing a test case in a simulation-based test implementation means to load all necessary parts (IUT, test environment, test case) in an RTL simulator and then to run the simulation.

In the simulation-based test implementation, the clocks of the IUT and the LT have no deviation from the nominal frequency and also have no jitter. Therefore, no requirements on the clock synchronization between the LT and the IUT (as listed in Section 1.6.1.2 for the hardware-based test implementation) are given for the simulation-based test implementation. However, IUT and (see Section 1.9) have to be considered in the simulation-based test implementation.



1.7 Internal RX DelayThe parameter adInternalRxDelay is implementation specific and has an allowed range between 1 and 4 sampleticks [PS10]. All basic configurations (see Chapter 3) assume adInternalRxDelay to be 4 sampleticks. In order to compensate between the implementation specific value of adInternalRxDelay and the assumed value of 4 sampleticks, a delay compensation shall be integrated in the RxD signal between the LT and the IUT. The delay compensation shall have a delay of 4-dt [sampleticks], and dt is the IUT's actual value of adInternalRxDelay. The delay compensation shall be applied in the hardware-based test implementation and in the simulation-based test implementation. Figure 3 gives an example how to implement the delay compensation in a hardware-based test implementation.Please note that in the test cases, the time interval between IUT's frame and LT's frame are measured at the test points marked in Figure 3. Therefore the delay compensation is not to be considered in test steps like It is verified (LT) that the interval between the IUT's frames in slot 1 and LT's frame slot 2 is x T....

1.8 Analog DelaysAnalog delays of the IUT appear in the signal paths between the physical pads of the device and the flip-flops of the FlexRay CC. In [EPL10], the analog delays are captured in the following parameters: dCCRxD01, dCCRxD10, dCCTxD01, dCCTxD10, dCCTxEN10 or dCCTxEN01. In this conformance test specification, the following two analog delays are defined: Rx is the analog delay on the reception path, and Tx is the analog delay on the transmission path. In the hardware-based test implementation, the analog delays are determined as follows:

Rx [0;max{dCCRxD01, dCCRxD10}]Tx [0;max{dCCTxD01, dCCTxD10, dCCTxEN10, dCCTxEN01}]Here, the parameters dCCRxD01, dCCRxD10, dCCTxD01, dCCTxD10, dCCTxEN10 or dCCTxEN01 have the maximal values as defined in [EPL10].

In the simulation-based test environment, there are no physical pads but only the FlexRay CC itself simulated. Therefore, the analog delays can be set to 0 here:Rx = 0Tx = 0

1.9 Accepted DeviationsDespite the synchronization of the IUT and the test environment described in Section 1.6.1.2 there is a remaining deviation between the LT and the IUT. A sample point at the LT does not necessarily cause a sample point at the IUT at the same moment since the clock signal stemming from the test environment can be delayed within the IUT due to the clock tree. Due to this we have to assume that the IUT's sample point occurs anywhere within two sample points of the LT and could also have a small amount of jitter.


Figure 3: Proposal for compensation of adInternalRxDelay in a hardware-based test implementation.

TestPoints for Measurement

LT IUT

RxD

TxEN

TxD

Sample Clock

F FF F F F

4321

MUX

dt = IUTs actual adInternalRxDelay

Delay Compensation


The figure shows that in the worst case this can lead to a situation where the IUT samples directly on the edges of the LT's signal. In that case even a small amount of jitter can cause a 4 sample signal of the LT to be seen as a 5 sample signal (line 3 of Figure 4) or a 3 sample signal (line 4 of Figure 4) by the IUT. This of course has consequences for the precision test cases can achieve and also on the results of the IUT's clock synchronization algorithm.The imprecision seen in Figure 4 prevents exact testing of the bit strobing point. Sending a 4 sample long pattern can, as has been shown, either be seen at the bit strobing point (sample point 5) or not. Similarly a 5 sample long pat

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