Firmware based array sorting

and Matlab testing suite

midterm presentationmay 4th , 2011

Elad BarzilayUri Natanzon

Supervisor: Moshe Porian

Project Goals

•Building a generic integer array sort firmware on an FPGA board •Develop a comprehensive testing and debugging environment.

The need for HistogramsMany image processing algorithms relay on the use of histograms.

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Project OverviewSystem capabilities & requirements

– Sorting an array of finite integers set.– Zero latency system.– Fully debug-able.– System operation via PC interface.

Design principles– Generic implementation.– Top down design.– Error detection and handling.

System implementation on the DE2 evaluation card. PC GUI implementation on MATLAB.Complete development process: Characterization->

debugging platform.

SORT_TOP – Inputs & OutputsTime Diagram

High-level overview

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SORT_TOP – Block diagramSORT_TOP

DPR_BLOCKDPR_update

F_VAL

DATA

D_VAL

en

Rd_addr

Rd_pipe1 Rd_pipe2 Rd_pipe3

Wr_pipe3 Wr_pipe2 Wr_pipe1 Write_port

Rd_data

Dpr_update_logic

+1

+2

Rd_addr

DPR_reader

F_VAL

DATA

Write

Rd_addr

D_VAL

FSM

St_Frame

Waits for a falling edge on FRAME_V

St_1st_valid

Stores data from DPR address 0 to pipeline 2nd

stage

St_2nd_valid

Stores data from DPR address 1 to pipeline 1st

stage.

St_output

Count down and outputs constant data for several

cycles

St_read_next

Propagates pipeline -rd&wr addr, output data

If address 0 value > 1 If address 0 value = 1,0

Count = 0

Value >1

If read value = 1,0

Pipe stg1 Pipe stg2

Rd_data

DPR1 DPR2

switch

DPR_update

F_VAL

DATA

D_VAL

en

Rd_addr

Rd_pipe1 Rd_pipe2 Rd_pipe3

Wr_pipe3 Wr_pipe2 Wr_pipe1 Write_port

Rd_data

Dpr_update_logic

+1

+2

Rd_addr

DPR_update – Block diagram

DPR_block – Block diagram

DPR_reader – Block diagram

Message Pack StructureSOFID

Data Length

Data (Payload)

CRCEOF

8 bits

1 Byte. Some constant predefined flag1 Byte. For message tracking

2 Bytes. Specifies the length of the data segment in bytes.

1 Byte. The CRC type will be defined later.1 Byte. Some constant predefined flag

address 1 Byte. Specifies the addressed blockaddress 1 Byte. Type options are : set, query, sort

[Data Length] X Bytes. (up to 65535 bytes)Holds the data and control signal to be fed into SORT_TOP

MSG_decoder FSM

UART_Rx

Idle

Store_Addr

Store_ID

Store_Type

Load_tFIFOStore_lengthx2

Store_CRC

Wait4copy(tFIFO to dFIFo)

Error_check

Timout

St_error

Wait4enc

Data = sof

Rx flag = 1

Rx flag = 1

Rx flag = 1

Rx flag = 1

Rx flag = 1Count++

Count = length

Rx flag = 1

CRC err /DATA!=EOF

CRC goodData = EOF

Copy done

After 1 ms

Data = sof

TempFIFO

DataFIFO

Fifocopy

Meta_dataFIFO

Meta_dataRegister

Encoder done

MSG_encoder FSM

UARTTx

Idle

tx_Addr

tx_ID

tx_Type

ReadFIFO

tx_lengthx2

Data_Tx(Count--)

Tx_CRC

Wordupdate

Tx_EOF

Tx done

Copy done

Meta_dataFIFO

DataFIFO

start

Tx done

Data read

1st Data read

Count = 0

Tx done

Tx done

Firmware Testing - simulation• All FW sub-modules were tested in VHDL

TestBenches.– Verification of module behavior by MODELSIM waveform

analysis.– All blocks - Tests included valid operation conditions.– Sorting block - Tests also included “worst case”

scenarios:• Sort_update – repetitions, fast toggling.• Sort_reader – zero repetitions, single repetitions, multiple

repetitions.• Communication path - tested in firmware.

– Error handling and CRC – not yet implemented. Will be tested separately.

Comprehensive tests will be held via “DUDE” – Our Matlab GUI

“DUDE” – Debugging Under Development Environment

MATLAB based GUI for data injection, result validation and status query

“DUDE” – implementation goals achievements

• Send user defined arrays of data to be sorted. -Done• Send random arrays of data to be sorted. -Done• Verify the correctness of the sorted returned data array. –

partially done. Not yet In GUI but capability implemented and used for debug.

• Create fully user generated packets to generate errors. –Not implemented yet.

• View bit representation of the messages sent and received . – Capability exists but not in GUI.

• Logging of out/in-bound messages. –Not implemented yet.

“DUDE” – implementation guidelines

• OOP based GUI.• 2 main classes implemented: • CSettings – holds all the framework data and manages the

messages list• CMessage – holds all the data per one given message and

manages the dynamic data creation such as CRC and data length calculation.

• This modular design allows the GUI to be versatile and parameter independent.

• All non implemented features are easily implemented with small effort.

• Easily adjustable to additional requested features.

project characterization

VHDL sorting code + sim

Exams

VHDL comm code +sim

syn, P&R, HW tests

FPGA - PC conectivity

Matlab GUI

software debug

full system debug

29/10/10 18/12/10 6/2/11 28/3/11 17/5/11 6/7/11

Project Time Line