famu-fsu college of engineering 1 computer architecture eel 4713/5764, spring 2006 dr. michael frank...

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FAMU-FSU College of Engineering

ComputerComputerArchitectureArchitectureEEL 4713/5764, Spring 2006

Dr. Michael Frank

Module #13 – Instruction Execution Steps(in a Single-Cycle MIPS Datapath)

July 2005 Computer Architecture, Data Path and Control Slide 2

Part IVData Path and Control


IV Data Path and Control

Topics in This Part

Chapter 13 Instruction Execution Steps

Chapter 14 Control Unit Synthesis

Chapter 15 Pipelined Data Paths

Chapter 16 Pipeline Performance Limits

Design a simple computer (MicroMIPS) to learn about:• Data path – part of the CPU where data signals flow• Control unit – guides data signals through data path• Pipelining – a way of achieving greater performance


13 Instruction Execution Steps

A simple computer executes instructions one at a time• Fetches an instruction from the loc pointed to by PC• Interprets and executes the instruction, then repeats

Topics in This Chapter

13.1 A Small Set of Instructions

13.2 The Instruction Execution Unit

13.3 A Single-Cycle Data Path

13.4 Branching and Jumping

13.5 Deriving the Control Signals

13.6 Performance of the Single-Cycle Design

(Single-Cycle CPU Design)


13.1 A Small Set of Instructions

Fig. 13.1 MicroMIPS instruction formats and naming of the various fields.

5 bits 5 bits

31 25 20 15 0

Opcode Source 1 or base

Source 2 or dest’n

op rs rt

R 6 bits 5 bits

rd

5 bits

sh

6 bits

10 5 fn

jta Jump target address, 26 bits

imm Operand / Offset, 16 bits

Destination Unused Opcode ext I

J

inst Instruction, 32 bits

Seven R-format ALU instructions (add, sub, slt, and, or, xor, nor)Six I-format ALU instructions (lui, addi, slti, andi, ori, xori)Two I-format memory access instructions (lw, sw)Three I-format conditional branch instructions (bltz, beq, bne)Four unconditional jump instructions (j, jr, jal, syscall)

We will refer to this diagram later


The MicroMIPS Instruction Set

Instruction UsageLoad upper immediate lui rt,imm

Add add rd,rs,rt

Subtract sub rd,rs,rt

Set less than slt rd,rs,rt

Add immediate addi rt,rs,imm

Set less than immediate slti rd,rs,imm

AND and rd,rs,rt

OR or rd,rs,rt

XOR xor rd,rs,rt

NOR nor rd,rs,rt

AND immediate andi rt,rs,imm

OR immediate ori rt,rs,imm

XOR immediate xori rt,rs,imm

Load word lw rt,imm(rs)

Store word sw rt,imm(rs)

Jump j L

Jump register jr rs

Branch less than 0 bltz rs,L

Branch equal beq rs,rt,L

Branch not equal bne rs,rt,L

Jump and link jal L

System call syscall

Copy

Control transfer

Logic

Arithmetic

Memory access

op15

0008

100000

1213143543

2014530

fn

323442

36373839

8

12Table 13.1


13.2 The Instruction Execution Unit

Fig. 13.2 Abstract view of the instruction execution unit for MicroMIPS. For naming of instruction fields, see Fig. 13.1.

ALU

Data cache

Instr cache

Next addr

Control

Reg file

op

jta

fn

inst

imm

rs,rt,rd (rs)

(rt)

Address

Data

PC


13.3 A Single-Cycle Data Path

Fig. 13.3 Key elements of the single-cycle MicroMIPS data path.

/

ALU

Data cache

Instr cache

Next addr

Reg file

op

jta

fn

inst

imm

rs (rs)

(rt)

Data addr

Data in 0

1

ALUSrc ALUFunc DataWrite

DataRead

SE

RegInSrc

rt

rd

RegDst RegWrite

32 / 16

Register input

Data out

Func

ALUOvfl

Ovfl

31

0 1 2

Next PC

Incr PC

(PC)

Br&Jump

ALU out

PC

0 1 2


An ALU for MicroMIPS

Fig. 10.19 A multifunction ALU with 8 control signals (2 for function class, 1 arithmetic, 3 shift, 2 logic) specifying the operation.

AddSub

x y

y

x

Adder

c 32

c 0

k /

Shifter

Logic unit

s

Logic function

Amount

5

2

Constant amount

Variable amount

5

5

ConstVar

0

1

0

1

2

3

Function class

2

Shift function

5 LSBs Shifted y

32

32

32

2

c 31

32-input NOR

Ovfl Zero

32

32

MSB

ALU

y

x

s

Shorthand symbol for ALU

Ovfl Zero

Func

Control

0 or 1

AND 00 OR 01

XOR 10 NOR 11

00 Shift 01 Set less 10 Arithmetic 11 Logic

00 No shift 01 Logical left 10 Logical right 11 Arith right

lui

imm


13.4 Branching and Jumping

Fig. 13.4 Next-address logic for MicroMIPS (see top part of Fig. 13.3). Adder

jta imm

(rs)

(rt)

SE

SysCallAddr

PCSrc

(PC)

Branch condition checker

in c

1 0 1 2 3

/ 30

/ 32 BrTrue / 32

/ 30 / 30

/ 30

/ 30

/ 30

/ 30

/ 26

/ 30

/ 30 4 MSBs

30 MSBs

BrType

IncrPC

NextPC

/ 30 31:2

16

(PC)31:2 + 1 Default option

(PC)31:2 + 1 + imm When instruction is branch and condition is met

(PC)31:28 | jta When instruction is j or jal

(rs)31:2 When the instruction is jr SysCallAddr Start address of an operating system routine

Update options for PC


13.5 Deriving the Control SignalsTable 13.2 Control signals for the single-cycle MicroMIPS implementation.

Control signal 0 1 2 3

RegWrite Don’t write Write

RegDst1, RegDst0 rt rd $31

RegInSrc1, RegInSrc0 Data out ALU out IncrPC

ALUSrc (rt ) imm

AddSub Add Subtract

LogicFn1, LogicFn0 AND OR XOR NOR

FnClass1, FnClass0 lui Set less Arithmetic Logic

DataRead Don’t read Read

DataWrite Don’t write Write

BrType1, BrType0 No branch beq bne bltz

PCSrc1, PCSrc0 IncrPC jta (rs) SysCallAddr

Reg file

Data cache

Next addr

ALU


Control Signal

Settings

Table 13.3

Load upper immediate Add Subtract Set less than Add immediate Set less than immediate AND OR XOR NOR AND immediate OR immediate XOR immediate Load word Store word Jump Jump register Branch on less than 0 Branch on equal Branch on not equal Jump and link System call

001111 000000 100000 000000 100010 000000 101010 001000 001010 000000 100100 000000 100101 000000 100110 000000 100111 001100 001101 001110 100011 101011 000010 000000 001000 000001 000100 000101 000011 000000 001100

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0

op fn

00 01 01 01 00 00 01 01 01 01 00 00 00 00

10

01 01 01 01 01 01 01 01 01 01 01 01 01 00

10

1 0 0 0 1 1 0 0 0 0 1 1 1 1 1

0 1 1 0 1 0 0

00 01 10 11 00 01 10

00 10 10 01 10 01 11 11 11 11 11 11 11 10 10

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

11 0110 00

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 00 01 11

Instruction Reg

Writ

e

Reg

Dst

Reg

InS

rc

ALU

Src

Add

’Sub

Logi

cFn

FnC

lass

Dat

aR

ead

Dat

aWrit

e

BrT

ype

PC

Src


Instruction Decoding

Fig. 13.5 Instruction decoder for MicroMIPS built of two 6-to-64 decoders.

jrInst

norInst

sltInst

orInst

xorInst

syscallInst

andInst

addInst

subInst

RtypeInst

bltzInst jInst jalInst beqInst bneInst

sltiInst

andiInst oriInst

xoriInst luiInst

lwInst

swInst

addiInst

1

0

1 2

3

4 5

10

12 13

14

15

35

43

63

8 o

p D

eco

de

r

fn D

eco

de

r

/ 6 / 6 op fn

0

8

12

32

34

36 37

38

39

42

63


Control Signal Generation

Auxiliary signals identifying instruction classes

arithInst = addInst subInst sltInst addiInst sltiInst

logicInst = andInst orInst xorInst norInst andiInst oriInst xoriInst

immInst = luiInst addiInst sltiInst andiInst oriInst xoriInst

Example logic expressions for control signals

RegWrite = luiInst arithInst logicInst lwInst jalInst

ALUSrc = immInst lwInst swInst

AddSub = subInst sltInst sltiInst

DataRead = lwInst

PCSrc0 = jInst jalInst syscallInst


Putting It All Together

/

ALU

Data cache

Instr cache

Next addr

Reg file

op

jta

fn

inst

imm

rs (rs)

(rt)

Data addr

Data in 0

1

ALUSrc ALUFunc DataWrite

DataRead

SE

RegInSrc

rt

rd

RegDst RegWrite

32 / 16

Register input

Data out

Func

ALUOvfl

Ovfl

31

0 1 2

Next PC

Incr PC

(PC)

Br&Jump

ALU out

PC

0 1 2

Fig. 13.3

Adder

jta imm

(rs)

(rt)

SE

SysCallAddr

PCSrc

(PC)

Branch condition checker

in c

1 0 1 2 3

/ 30

/ 32 BrTrue / 32

/ 30 / 30

/ 30

/ 30

/ 30

/ 30

/ 26

/ 30

/ 30 4 MSBs

30 MSBs

BrType

IncrPC

NextPC

/ 30 31:2

16

Fig. 13.4

Fig. 10.19

AddSub

x y

y

x

Adder

c 32

c 0

k /

Shifter

Logic unit

s

Logic function

Amount

5

2

Constant amount

Variable amount

5

5

ConstVar

0

1

0

1

2

3

Function class

2

Shift function

5 LSBs Shifted y

32

32

32

2

c 31

32-input NOR

Ovfl Zero

32

32

MSB

ALU

y

x

s

Shorthand symbol for ALU

Ovfl Zero

Func

Control

0 or 1

AND 00 OR 01

XOR 10 NOR 11

00 Shift 01 Set less 10 Arithmetic 11 Logic

00 No shift 01 Logical left 10 Logical right 11 Arith right

Control

addInst

subInstjInst

sltInst

. ..

.

. .


13.6 Performance of the Single-Cycle Design

Fig. 13.6 The MicroMIPS data path unfolded (by depicting the register write step as a separate block) so as to better visualize the critical-path latencies.

Instruction access 2 nsRegister read 1 nsALU operation 2 nsData cache access 2 nsRegister write 1 ns Total 8 ns

Single-cycle clock = 125 MHz

P C

P C

P C

P C

P C

ALU-type

Load

Store

Branch

Jump

Not used

Not used

Not used

Not used

Not used

Not used

Not used

Not used

Not used

(and jr)

(except jr & jal)

R-type 44% 6 nsLoad 24% 8 nsStore 12% 7 nsBranch 18% 5 nsJump 2% 3 ns

Weighted mean 6.36 ns

famu-fsu college of engineering 1 computer architecture eel 4713/5764, spring 2006 dr. michael frank...

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