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F-Tile Serial Lite IV Intel® FPGA IPDesign Example User Guide

Updated for Intel® Quartus® Prime Design Suite: 21.2

IP Version: 2.0.0

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Contents

1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide..................... 3

2. Quick Start Guide............................................................................................................42.1. Design Example Block Diagram............................................................................... 42.2. Software Requirements.......................................................................................... 62.3. Generating the Design............................................................................................7

2.3.1. Design Example Parameters........................................................................72.3.2. Directory Structure.................................................................................... 9

2.4. Compiling and Simulating the Design......................................................................112.5. Compiling and Testing the Design...........................................................................12

3. Detailed Description for F-Tile Serial Lite IV Design Example....................................... 133.1. Features............................................................................................................. 133.2. Design Example Components................................................................................ 14

3.2.1. Traffic Generator......................................................................................143.2.2. Traffic Checker.........................................................................................143.2.3. DCFIFO.................................................................................................. 15

3.3. Simulation.......................................................................................................... 163.3.1. Simulation Results for Basic Mode.............................................................. 163.3.2. Simulation Result for Full Mode..................................................................19

3.4. Error Handling.....................................................................................................223.5. Link Debugging Sequence..................................................................................... 223.6. F-Tile Serial Lite IV IP Toolkit.................................................................................24

3.6.1. Setting Up and Running the Toolkit.............................................................253.6.2. Toolkit GUI Settings................................................................................. 26

4. Document Revision History for the F-Tile Serial Lite IV Intel FPGA IP DesignExample User Guide.................................................................................................29

Contents

F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Send Feedback

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1. About the F-Tile Serial Lite IV Intel® FPGA IP DesignExample User Guide

This document provides features, usage guidelines, and functional description of theF-Tile Serial Lite IV Intel® FPGA IP design examples using F-tile transceivers in IntelAgilex® devices.

Intended Audience

This document is intended for the following users:

• Design architects to make IP selection during system level design planning phase.

• Hardware designers when integrating the IP into their system level design.

• Validation engineers during system level simulation and hardware validationphase.

Acronyms and Glossary

Table 1. Acronym List

Acronym Expansion

CW Control Word

RS-FEC Reed-Solomon Forward Error Correction

PMA Physical Medium Attachment

TX Transmitter

RX Receiver

PAM4 Pulse-Amplitude Modulation 4-Level

NRZ Non-return-to-zero

PCS Physical Coding Sublayer

MII Media Independent Interface

XGMII 10 Gigabit Media Independent Interface

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Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of IntelCorporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with Intel's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Intel assumes no responsibility or liability arising out of theapplication or use of any information, product, or service described herein except as expressly agreed to inwriting by Intel. Intel customers are advised to obtain the latest version of device specifications before relyingon any published information and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

ISO9001:2015Registered


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2. Quick Start GuideThe F-Tile Serial Lite IV Intel FPGA IP provides the ability to generate design examplesfor selected configurations.

The F-Tile Serial Lite IV Intel FPGA IP design example for Intel Agilex devices featuresa simulation testbench and a hardware design that supports compilation and hardwaretesting. The design example demonstrates loopback mode designs in basic or fullmode for duplex configurations.

Figure 1. Development Stages for the Design Example

DesignExample

Generation

Compilation(Simulator)

FunctionalSimulation

Compilation(Quartus Prime)

2.1. Design Example Block Diagram

Figure 2. High-Level Block Diagram for Intel Agilex Design Examples

DemoManagement

DemoControl

JTAGInterface

SystemConsole

TrafficChecker

DCFIFO

TrafficGenerator

DCFIFO

IOPLLF-tile Serial Lite IV

Duplex

System PLL

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Table 3. Design Example Components

Component Description

F-Tile Serial Lite IV Intel FPGA IP The F-Tile Serial Lite IV Intel FPGA IP in this design example supportsstreaming or packet transfer mode with the following features:• For FHT transceiver type:

— 56.1 Gbps per lane with a maximum of four PAM4 lanes.— 28.05 Gbps per lane with a maximum of four NRZ lanes.

• For FGT transceiver type:— 22 Gbps to 58 Gbps per lane with a maximum of 12 PAM4 lanes.— 10 Gbps to 28.05 Gbps per lane with a maximum of 16 NRZ lanes

for duplex design and single lane for simplex design.The F-Tile Serial Lite IV Intel FPGA IP accepts data from the trafficgenerator and formats the data for transmission.The F-Tile Serial Lite IV Intel FPGA IP also receives data from the link,strips the headers, and sends it to the traffic checker for analysis.You generate the IP using the parameter editor in the Intel Quartus®

Prime Pro Edition software.

System Console The System Console is an Intel Quartus Prime tool that provides a user-friendly interface for you to do first-level debugging and monitor thestatus of the IP, and the traffic generator, and checker.

Demo control The demo control module consists of Avalon® memory-mapped pipelinebridges connected to the transceiver reconfiguration and the demomanagement interfaces. The design also instantiates the JTAG master,parallel input/output (PIO), and ISSP (In-system Source and Probe)modules for System Console debugging purposes.

Demo management The demo management module implements control and status registers(CSRs) to control, monitor the design operation, and log errors thatoccur during the operation.

User clock—IOPLL For Intel Agilex F-tile devices, the design example uses an IOPLL togenerate a user clock to transmit data to the F-Tile Serial Lite IV IP.The design uses the iopll_ref_clk clock signal as an IOPLL referenceclock to connect to the clock generator.Important: The iopll_ref_clk should have the same frequency as

the pll_refclk and come from the same clock module.

Traffic generator The traffic generator generates traffic in a deterministic format to verifythat the link transmits data correctly.

Traffic checker The traffic checker performs inspections to verify that the received datais in the expected format.

Dual-clock FIFO (DCFIFO) The DCFIFO blocks handle data streaming and control signals for clockcrossing between different clock domains.

System PLL The system PLL drives the F-Tile Serial Lite IV Duplex and Simplexmodule and is driven to the same frequency as the iopll_ref_clkclock signal.

Related Information

• Traffic Generator on page 14

• Traffic Checker on page 14

• DCFIFO on page 15

2. Quick Start Guide

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2.2. Software Requirements

Intel uses the following software to test the design examples in a Linux system:

• Intel Quartus Prime Pro Edition software version 21.1

• VCS*/VCS MX simulator


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2.3. Generating the Design

You can use the IP parameter editor in the Intel Quartus Prime Pro Edition software togenerate the design example.

Figure 3. Generating the Design Flow

Start ParameterEditor

Specify IP Variationand Select Device

SelectDesign Parameters

InitiateDesign Generation

Specify Example Design

To generate the design example from the IP parameter editor:

1. In the Tools ➤ IP Catalog, locate and select F-Tile Serial Lite IV Intel FPGAIP. The IP parameter editor appears.

2. Specify the parameters for your design.

3. Click the Generate Example Design button.

The software generates all design files in the sub-directories. You need these files torun simulation and compilation..

Related Information

Directory Structure on page 9

2.3.1. Design Example Parameters

The F-Tile Serial Lite IV Intel FPGA IP parameter editor includes an Example Designtab for you to specify parameters before generating the design example.


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Figure 4. Example Design Tab

Table 4. Parameters in the Example Design Tab

Parameter Description

Generate Files for The IP generates the necessary design example files for simulation andcompilation.Simulation—select this option to generate the necessary designsimulation files.Synthesis—select this option to generate the necessary design synthesisfiles. Use these files to compile the design in the Intel Quartus Prime ProEdition software for hardware testing.

Generate Files for Synthesis When selected, the IP generates the synthesis files. Use these files tocompile the design in the Intel Quartus Prime Pro Edition software forhardware testing.

Generate File Format The format of the RTL files for simulation—Verilog or VHDL.

Select Board Supported hardware for design implementation. When you select anIntel FPGA development board, the Target Device is the one thatmatches the device on the Development Kit.

continued...


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Parameter Description

If this menu is grayed out, there is no supported board for the optionsthat you select.No Development Kit: This option excludes the hardware aspects forthe design example.

Change Target Device Select a different device grade for Intel FPGA IP development kit. Fordevice-specific details, refer to the device datasheet on the Intel FPGAwebsite.

2.3.2. Directory Structure

The Intel Quartus Prime Pro Edition software generates the design example files in thefollowing folders:

• <user_defined_design_example_directory>/ed_sim

• <user_defined_design_example_directory>/ed_synth

The following diagrams show the directories that contain the generated files for thedesign example.


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Figure 5. Directory Structure for Intel Agilex F-Tile Serial Lite IV Design Example

<Design Example>

ed_sim

cadence

common

mentor

qdb

seriallite4_system_pll

synopsis

demo_control

demo_control.qsys

gen_qsys_seriallite4_dcfifo.tcl

gen_qsys_seriallite4_dup.tclgen_qsys_seriallite4_dup.tcl

gen_sim_verilog.tcl

ip

reset_release_ip

seriallite4_dcfifo

seriallite4_dup

seriallite4_io_pll

seriallite4_system_pll

gen_qsys_seriallite4_io_pll.tcl

seriallite_iv_streaming_demo.qpf

seriallite_iv_streaming_demo.qsf

seriallite_iv_streaming_demo.sdc

seriallite4_dcfifo.qsys

reset_release_ip.qsys

quartus.ini

gen_qsys_seriallite4_reset_release_ip.tcl

gen_qsys_seriallite4_sys_pll.tcl

gen_synth_verilog.tcl

log_generate_eds.txt

run_vcs.sh

seriallite4_dup

seriallite4.done

seriallite4_dup.ip

aldec

ed_synth

tb_components

xcelium

gen_qsys_seriallite4_sys_pll.tcl

log_generate_eds.txt

quartus.ini

seriallite4_tiles.qip

seriallite4_tiles.spd

seriallite4_tiles.v

seriallite4_tiles_z1577a_x0_y0_n0.mif

seriallite4_tiles.bcm.txt

seriallite4.sv

seriallite4.qsf

seriallite4.spd

seriallite4.qpf

seriallite4_dup.ip

seriallite4_system_pll.ip

seriallite4_tiles_ip_instances.json

src

seriallite4_io_pll.ip

seriallite4_system_pll.ip

seriallite4_tiles_ip_instances.json

seriallite4_tile_placement.json

tile.spd

Table 5. Design Example Generated Directory and File Descriptions

Directory/File Description

ed_sim/tb_components The directory that contains the testbench files.

ed_sim/common The directory that contains the .tcl scripts for all thesimulators.

ed_sim/cadence The directories that contain the simulation scripts. Thesedirectories also serve as a working area for the simulators.

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Directory/File Description

ed_sim/mentor

ed_sim/xcelium

ed_sim/synopsys/vcs

For simplex Tx/Rx mode:ed_sim/seriallite4_tx_0

ed_sim/seriallite4_rx_0

For duplex mode:ed_sim/seriallite4_dup

The directory that contains the design example simulationsource files.

ed_sim/seriallite4_tx_0.ip

ed_sim/seriallite4_rx_0.ip

ed_sim/seriallite4_dup.ip

ed_sim/seriallite4_system_pll.ip

IP-XACT representation of the design.

ed_synth/seriallite_iv_streaming_demo.qpf Intel Quartus Prime Pro Edition project file.

ed_synth/seriallite_iv_streaming_demo.qsf Intel Quartus Prime Pro Edition settings file.

ed_synth/seriallite_iv_streaming_demo.sdc Synopsys Design Constraints (SDC) file.

ed_synth/src The directory that contains the design examplesynthesizable components.

ed_synth/src/seriallite_iv_streaming_demo.v Design example top-level HDL.

ed_synth/demo_control The directory for each synthesizable component includingPlatform Designer-generated IPs, such as DemoManagement and Demo Control modules.

Related Information

Generating the Design on page 7

2.4. Compiling and Simulating the Design

The design example testbench simulates your generated design.

Change to Testbench Directory

Run<Simulation Script>

AnalyzeResults

1. Change the working directory to <example_design_directory>/ed_sim/<simulator>

2. Run the simulation script for the simulator of your choice.

Table 6. Testbench Simulation Scripts

Simulator File Directory Command

VCS <variation name>seriallite4_0_example_design/ed_sim sh run_vcs.sh

3. When the simulation is complete, you can now analyze the results and verify thedesign. A successful simulation ends with the following message, "Test Passed."

# ****************************** Data Forwarding Test Completed ****************************# # ************************************** Test Completed


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************************************# # End time = 534579600# # Total words tranferred = 10000# # Number of bursts = 0# # Random number generator seed = 1756255697# # Link Latency = 434 ns# # *************************************** Test Passed **************************************

2.5. Compiling and Testing the Design

Follow these steps to compile and test the design:

1. Launch the Intel Quartus Prime Pro Edition software and change the directory toexample_design_dir/ed_synth/ and open theseriallite_iv_streaming_demo.qpf file.

2. Click Processing> Start Compilation to compile the design.

The Intel Quartus Prime Pro Edition software automatically loads the timingconstraints for the design example and the design components during compilation.

The design includes a Synopsys Design Constraints File (.sdc) and an Intel QuartusPrime Pro Edition Settings File (.qsf) with verified constraints in loopback mode. Ifyou use the design example with another device or development board, you may needto update the device settings and constraints in the .qsf file.


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3. Detailed Description for F-Tile Serial Lite IV DesignExample

This design example demonstrates the functionality of data streaming using basic andfull mode.

You can specify the parameter settings of your choice and generate the designexample.

The design example is available only in duplex mode.

3.1. Features

You can use the design example to test the following features of the F-Tile Serial LiteIV Intel FPGA IP:

• Basic and full transmission modes:

— Basic mode—This is a pure streaming mode where data is sent without thestart-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IPtakes the first valid data as the start of a burst.

— Full mode—This is a packet transfer mode. This mode sends a burst and async cycle at the start and end of a packet as delimiters.

• Transceiver data rate:

— For PAM4 mode (1):

• FHT supports only 56.1 Gbps per lane with a maximum of 4 lanes.

• FGT supports up to 58 Gbps per lane with a maximum of 12 lanes.

— For NRZ mode (1):

• FHT supports only 28.05 Gbps per lane with a maximum of 4 lanes.

• FGT is supporting up to 28.05 Gbps per lane with a maximum of 16 lanes.

• Data error reporting including PCS errors, loss of alignment, CRC errors, and datainvalid errors on the RX datapath.

• Traffic checker for data verification and lane deskew verification.

(1) The maximum data rate that the IP can achieve depends on the device speed grade. Refer to Intel Agilex Device Data Sheet for more information about maximum data rate for each devicespeed grade.

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3.2. Design Example Components

3.2.1. Traffic Generator

The traffic generator generates traffic in a deterministic format to verify that data istransmitted correctly across the link. The traffic consists of sets of sample words, onefor each lane on the link, that the traffic checker transmits to the source userinterface.

If you configure the F-Tile Serial Lite IV IP in full mode, the traffic generator alsoasserts the tx_is_usr_cmd signal at random to specify the packet is from user datafor testing purposes. The F-Tile Serial Lite IV IP asserts the num_valid_bytes_eobcontrol signal to signify the number of valid bytes of the burst packet.

Figure 6. Traffic Generator Sample Word FormatThis figure shows the format of the sample words generated for each lane.

Word ID Burst Count Word Count

Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0

Table 7. Traffic Generator Sample Word Fields

Field Bits Description

Word ID 63–59 Contains a static value to distinguish which 64-bit word on the user interface that thissample was presented on. The Word ID value ranges from 0 to (lanes – 1).

Burst Count 58–32 Tracks the number of bursts used to transfer the sample data. This field value starts withone after reset and is incremented each time the start_of_burst signal asserts on thesource user interface.

Word Count 31–0 Tracks the number of valid sample words that the traffic generator transfers, across allbursts, to the source user interface.

3.2.2. Traffic Checker

The traffic checker performs the following inspections to verify that the received dataare in the expected format:

• Checks each sample word to verify that the traffic checker receives the expectedword ID.

• Checks each sample word to verify that the word count value is higher than theword count value from the last valid sample word.

• Verifies that lane de-skew is working correctly by validating that the word countand burst count values from the sample word are the same as the values receivedfrom the adjacent lane.

• If the start_of_burst signal asserts on the user interface, verifies that theburst count value in the current sample word is higher than the burst count valuefrom the last valid sample word. Otherwise, it verifies that the burst count valuehas not changed.

3. Detailed Description for F-Tile Serial Lite IV Design Example

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3.2.3. DCFIFO

The design uses two DCFIFO blocks at both TX and RX paths. The DCFIFO blockshandle data streaming and control signals for clock crossing between different clockdomains.

Table 8. TX and RX DCFIFO Configuration

Parameter Value

lpm_width (Number of lanes x 64)+32

lpm_numwords 64

The format of the data that transmits through the FIFO is similar to the formatgenerated by the traffic generator.

Figure 7. Data Format

Word ID Burst Count Word Count

Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0

Table 9. Control SignalsThe table lists how the IP concatenates the TX and RX control signals with the data bus signals and passesthrough the data.

Control DCFIFO DataOut Bit

Signal Description

[20] tx_valid

rx_valid

Indicates TX or RX data is valid for Full and Basicmodes.

[19] tx_start_of_packet

rx_start_of_packet

Indicates the start of a TX or RX data packet.For Full mode only.

[18] tx_end_of_packet

rx_end_of_packet

Indicates the end of a TX or RX data packet.For Full mode only.

[17:10] tx_channel

rx_channel

The channel number for data being transmitted orreceived on the current cycle number.For Full mode only.

[9:5] tx_empty

rx_empty

Indicates the number of non-valid words in the finalburst of the TX or RX data.For Full mode only.

[4:1] tg_tx_num_valid_bytes_eob

tc_rx_num_valid_bytes_eob

Indicates the number of valid bytes in the last wordof the final burst.For Full mode only.

[0] tg_tx_is_usr_cmd

tc_rx_is_usr_cmd

Initiates a user-defined information cycle.• Full mode: Must coincide with

tx_startofpacket or rx_startofpacket• Basic mode: Not supported.

Related Information

FIFO Intel FPGA IP User Guide


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3.3. Simulation

Figure 8. Example Testbench (Duplex) for Intel Agilex F-Tile Devices

Testbench

F-tile Serial Lite IV Intel FPGA IP

TrafficGenerator

TrafficChecker

DCFIFO TX MAC

RX MAC SkewInsertion

Device Under Test (Duplex Mode)Test Environment

DCFIFO

F-tileHard

IP

The simulation test cases demonstrate streaming of 10,000 sample words from thetraffic generator to the F-Tile Serial Lite IV TX core, and externally loopback to the RXcore. The words are either separated into different bursts or continuously transferredin a single burst. The transfer modes are randomized by the testbench.

The simulation test case performs the following steps:

1. Initializes and configures F-Tile Serial Lite IV Intel FPGA IP, traffic generator, andtraffic checker.

2. Traffic generator generates data and starts data transmission.

3. Logs and displays link up status and burst information.

4. Traffic checker verifies received data and stops transmission.

5. Testbench logs and displays test results and test information.

3.3.1. Simulation Results for Basic Mode

The generated example testbench is dynamic and has the same configuration as theIP.

In basic or pure streaming mode, the traffic generator generates 10,000 words andtransmits to the IP once the TX and RX links are established. The words are thenlooped back to the RX MAC. The RX MAC then sends the words to the traffic checkerfor data verification. In the simulation results, you can find the following information:

• TX and RX link status

• Configuration settings of the IP

• Number of words transferred per burst

• Test results with the total number of words transferred and link latency value

The following are samples of simulation results for each design example variant.


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PAM4 with RS-FEC Enabled in Basic Transfer Mode Simulation Result

Note: NRZ with RS-FEC enabled variant has similar simulation result as PAM4 with RS-FECenabled variant.

# Waiting for TX Link Up# # Phy TX Lanes Stable asserted at time 354081776# # Phy EHIP ready asserted at time 475222181# # TX link_up asserted at time 475228320# TX user_clock frequency = 3.731343e+02 MHz# RX user_clock frequency = 3.731343e+02 MHz# # *************************************** Test Started *************************************# # Tests started at time 475239040# # LANES = 4# # Streaming Mode = BASIC# # SRL4 Align Period = 128# # RSFEC Enable = 1# # PER LANE CRC ENABLE Enable = 0# # ******************************* Data Forwarding Test Initialize *****************************# # Waiting for RX Link Up# # Phy block lock asserted at time 495699771# # Phy RX PCS Ready asserted at time 495731094# # RX link_up asserted at time 495786600# # ******************************* Data Forwarding Test Started *****************************# # Test Mode: Burst# User Stall Insertion: Disabled# # # Traffic Generator: 98 sample burst started at time 495797320# # Traffic Generator: 17 sample burst started at time 496110880...# Traffic Generator: 96 sample burst started at time 533156520# # Traffic Generator: 85 sample burst started at time 533515640# # ****************************** Data Forwarding Test Completed ****************************# # ************************************** Test Completed ************************************# # End time = 534579600# # Total words tranferred = 10000# # Number of bursts = 0


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# # Random number generator seed = 1756255697# # Link Latency = 434 ns# # *************************************** Test Passed **************************************

NRZ without RS-FEC Enabled in Basic Transfer Mode Simulation Result

# Waiting for TX Link Up# # Phy TX Lanes Stable asserted at time 3007624010# # Phy EHIP ready asserted at time 4397012810# # TX link_up asserted at time 4397112640# TX user_clock frequency = 3.511236e+02 MHz# RX user_clock frequency = 3.511236e+02 MHz# # *************************************** Test Started *************************************# # Tests started at time 4397226560# # LANES = 2# # Streaming Mode = BASIC# # SRL4 Align Period = 128# # RSFEC Enable = 0# # PER LANE CRC ENABLE Enable = 0# # ******************************* Data Forwarding Test Initialize *****************************# # Waiting for RX Link Up# # Phy block lock asserted at time 4423739210# # Phy RX PCS Ready asserted at time 4424123210# # RX link_up asserted at time 4425564160# # ******************************* Data Forwarding Test Started *****************************# # Test Mode: Continuous# User Stall Insertion: Disabled# # # Traffic Generator: 10000 sample continuous transfer started at time 4425678080# # ****************************** Data Forwarding Test Completed ****************************# # ************************************** Test Completed ************************************# # End time = 4814401600# # Total words tranferred = 10000# # Number of bursts = 0# # Random number generator seed = 1221861777


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# # Link Latency = 2900 ns# # *************************************** Test Passed **************************************

3.3.2. Simulation Result for Full Mode

In full mode or packet transfer mode, the traffic generator generates 10,000 words ina random number of bursts and transmits to the IP once the TX and RX links areestablished. The words are looped back to the RX MAC. The RX MAC then sends theburst to the traffic checker for data verification. In the simulation results, you can findthe following information:

• TX and RX link status

• Configuration settings of the IP

• Number of sample words sent per burst

• Test results with the total number of words transferred, number of bursts, and linklatency value

The following are samples of simulation results for each design example variant.

PAM4 with RS-FEC Enabled in Full Transfer Mode Simulation Result

Note: NRZ with RS-FEC enabled variant has similar simulation result as PAM4 with RS-FECenabled variant.

# Waiting for TX Link Up# # Phy TX Lanes Stable asserted at time 354081776# # Phy EHIP ready asserted at time 475222181# # TX link_up asserted at time 475228320# TX user_clock frequency = 3.731343e+02 MHz# RX user_clock frequency = 3.731343e+02 MHz# # *************************************** Test Started *************************************# # Tests started at time 475239040# # LANES = 4# # Streaming Mode = FULL# # SRL4 Align Period = 128# # RSFEC Enable = 1# # PER LANE CRC ENABLE Enable = 0# # ******************************* Data Forwarding Test Initialize *****************************# # Waiting for RX Link Up# # Phy block lock asserted at time 495699771# # Phy RX PCS Ready asserted at time 495731094# # RX link_up asserted at time 495786600#


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# ******************************* Data Forwarding Test Started *****************************# # Test Mode: Burst# User Stall Insertion: Disabled# # # Traffic Generator: 98 sample burst started at time 495797320# # Traffic Generator: 17 sample burst started at time 496110880...# Traffic Checker: Burst start descriptor read at time 534212440# Sync value 242# Sample number 9907# # Traffic Checker: Burst end descriptor read at time 534534040# Inter-burst interval 7# Empty value 0# Sample number 10000# # ****************************** Data Forwarding Test Completed ****************************# # ************************************** Test Completed ************************************# # End time = 534810080# # Total words tranferred = 10000# # Number of bursts = 196# # Random number generator seed = 1756255697# # Link Latency = 0 ns# # *************************************** Test Passed **************************************

NRZ without RS-FEC Enabled in Full Transfer Mode Simulation Result

# Waiting for TX Link Up# # Phy TX Lanes Stable asserted at time 3007624010# # Phy EHIP ready asserted at time 4397012810# # TX link_up asserted at time 4397112640# TX user_clock frequency = 3.511236e+02 MHz# RX user_clock frequency = 3.511236e+02 MHz# # *************************************** Test Started *************************************# # Tests started at time 4397226560# # LANES = 2# # Streaming Mode = FULL# # SRL4 Align Period = 128# # RSFEC Enable = 0# # PER LANE CRC ENABLE Enable = 0# # ******************************* Data Forwarding Test Initialize *****************************


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# # Waiting for RX Link Up# # Phy block lock asserted at time 4423739210# # Phy RX PCS Ready asserted at time 4424123210# # RX link_up asserted at time 4425564160# # ******************************* Data Forwarding Test Started *****************************# # Test Mode: Continuous# User Stall Insertion: Disabled# # # Traffic Generator: 10000 sample continuous transfer started at time 4425678080# # Traffic Checker: Burst start descriptor read at time 4428412160# Sync value 125# Sample number 1# # Traffic Checker: Burst end descriptor read at time 4811468160# Inter-burst interval 0# Empty value 0# Sample number 10000# # ****************************** Data Forwarding Test Completed ****************************# # ************************************** Test Completed ************************************# # End time = 4814401600# # Total words tranferred = 10000# # Number of bursts = 1# # Random number generator seed = 1221861777# # Link Latency = 2900 ns# # *************************************** Test Passed **************************************


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3.4. Error Handling

The F-Tile Serial Lite IV IP detects error conditions and the behaviors in response tothese error conditions.

Table 10. Error Condition BehaviorIn this table, N represents the number of lanes.

Signal Width Location Direction Clock Domain Error Indication

tx_error 5 Top-levelsignal

Output tx_core_clkout Not used.

rx_error (N*2*2)+3(PAM4mode)

(N*2)*3(NRZ mode)

Top-levelsignal

Output rx_core_clkout When asserted, indicatesan error condition on theRX datapath.• [(N*2+2):N+3] =

Indicates PCS error fora specific lane.

• [N+2] = Indicatesalignment error. Re-initialize lanealignment if this bit isasserted.

• [N+1]= Indicates datais forwarded to theuser logic when userlogic is not ready.

• [N] = Indicates loss ofalignment.

• [(N-1):0] = Indicatesthe data contains CRCerror.

tx_adaptation_fifo_full

1 Top-level TXDCFIFOsignal

Output TX user clock This vector indicates thewrite domain TX buffer isfull and cannot acceptdata.

rx_adaptation_fifo_full

1 Top-level TXDCFIFOsignal

Output TX user clock This vector indicates thewrite domain RX buffer isfull and cannot acceptdata.

readfull 1 Top-level RXDCFIFOsignal

Output RX user clock This vector indicates theread domain buffer is fulland cannot accept data.

Related Information

FIFO Intel FPGA IP User Guide

3.5. Link Debugging Sequence

The F-Tile Serial Lite IV IP provides a link debugging sequence for TX and RX that youcan use when debugging your design.


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https://www.intel.com/content/www/us/en/programmable/documentation/eis1414462767872.html#eis1414462854553


Figure 9. TX Link Debugging Flowchart

Start

No

Yes Yes

No

Yes Note: If rx_link_up status = 0, you need to debug the RX link.

No

tx_link_upAsserted?

* Resets = tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, and reconfig_reset

Check Transceiver Reference Clock

Check if tx_serial_data and rx_serial_data are connected

Check if the resets* are out of reset for at least 10 clock cycles

Check rx_link_up Status

No

pll_lockedAsserted?

phy_tx_lanes_stableAsserted?

phy_ehip_readyAsserted?

Table 11. TX Link Debugging Signals

Signal Location Description

tx_link_up Top-level TX signal The IP asserts this signal to indicate that theinitialization sequence is complete and the IP is readyto transmit the data.

tx_pll_locked Top-level PHYsignal

This active-high signal indicates that the transceiversare locked to the reference clock.

phy_tx_lanes_stable Top-level PHYsignal

The IP asserts this signal when TX datapath is readyto send data.

phy_ehip_ready[(n*2)-1:0] Top-level PHYsignal

The IP asserts this signal after thetx_pcs_fec_phy_reset_n andrx_pcs_fec_phy_reset_n signals deassert toindicate that the custom PCS has completed internalinitialization and is ready for transmission.


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Figure 10. RX Link Debugging Flowchart

Start

No

Yes Yes

No No

rx_link_upAsserted?

* Resets = tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, reconfig_sl_reset, and reconfig_reset

Check Transceiver Reference Clock

Check if tx_serial_data and rx_serial_data are connected

Check if the resets* are out of reset for at least 10 clock cycles

No

phy_rx_pcs_readyAsserted?

phy_rx_block_lockAsserted?

phy_ehip_readyAsserted?

Yes RX Ready to Receive Data

Table 12. RX Link Debugging Signals

Signal Location Description

rx_link_up Top-level RX signal The IP asserts this signal to indicate that theinitialization sequence is complete, and the IP isready to receive data.

phy_rx_pcs_ready[(n*2)-1:0] Top-level PHYsignal

The IP asserts this signal when RX datapath is readyto receive data.

phy_rx_block_lock[(n*2)-1:0] Top-level PHYsignal

The IP asserts this signal to indicate the 66b blockalignment has completed for the lanes.

3.6. F-Tile Serial Lite IV IP Toolkit

The F-Tile Serial Lite IV IP toolkit is an inspection tool that monitors the status of a F-Tile Serial Lite IV IP link and provides a step-by-step guide for the IP link initializationsequences.

The F-Tile Serial Lite IV IP toolkit mainly monitors the following:


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• MAC link up status

• Hardened Custom PCS lane alignment status

• Clock data recovery (CDR) lock

• Traffic generator and checker statistics

The IP link initialization sequences guide also includes CSRs to monitor and log errorsthat occur during the operation.

Note: The toolkit uses hardened customer PCS core and MAC output ports to provide real-time link status. Therefore, the toolkit can only work with the design files with thesettings you set during the design example generation. Any modifications to thegenerated design files may cause the toolkit to work incorrectly.

3.6.1. Setting Up and Running the Toolkit

To enable the F-Tile Serial Lite IV IP toolkit, you must download and run the toolkit.

To run the toolkit, follow these steps:

1. Generate the design example after you specify the parameters.

2. Compile the design example to generate a .sof file.

3. In the Intel Quartus Prime Pro Edition software, select Tools ➤ SystemDebugging Tools ➤ System Console to launch the system console.

4. In the system console, click Load Design abnd select the .sof file for the designexample.

5. Under the list of Instances, select sliv_ip_toolkit_1.0.

6. Under the Details pane, select F-Tile Serial Lite IV IP Toolkit and click OpenToolkit to launch the toolkit.

Figure 11. Launch the F-Tile Serial Lite IV IP Toolkit

When the toolkit is up and running, set JTAG master by following the instructionsgiven in the display window.


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Figure 12. Setting JTAG Master

Ensure that you specify the same setting as your design example

Related Information

Analyzing and Debugging Designs with System Console

3.6.2. Toolkit GUI Settings

The F-Tile Serial Lite IV IP toolkit offers an easy-to-manage user interface.

The F-Tile Serial Lite IV IP toolkit user interface has three tabs.

• The MAC and PHY tab implements various control and status registers (CSR) forboth the hardened custom PCS core and the MAC soft logic.

• The Traffic Statistics tab implements various Control and Status Registers (CSR)for the Demo Management module to configure the traffic generator and checker.

• The Help tab provides useful next-step troubleshooting information based on theassertion and deassertion of specific status registers or output ports if any errorshappen after the link initialization is executed.

The MAC and PHY tab shows a step-by-step guide for link initialization and real-timestatus monitoring of a F-Tile Serial Lite IV IP link.

The toolkit continuously reads and displays all of the essential status registers relatedto the F-Tile Serial Lite IV IP link after you execute the following stages:

1. Click Assert Full System Reset to perform a full system reset.

2. Click Link Initialization to perform link initialization.

3. Click Read PCS Status to poll all corresponding status registers and output portsfrom both hardened custom PCS and MAC soft logic.


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Figure 13. MAC and PHY Tab

Note: The toolkit user interface changes dynamically to illustrate each execution stage.

In case of any failure, the toolkit narrows down to the type of failure based on thevarious status bits, which are based on the register bank or output port from thehardened custom PCS core or MAC soft logic. The corresponding next-step debugginginformation is displayed in the Help tab.

Figure 14. Traffic Statistics Tab


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The Traffic Statistics tab enables you to configure both the traffic generator andchecker in the design example to run in the user-specified traffic mode, and readstraffic statistics. You can also read the traffic statistics in this tab.

Figure 15. Help Tab

The Help tab provides useful next-step debugging information based on the errors orstatus registers reported from the MAC and PCS status in the MAC and PHY tab.


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4. Document Revision History for the F-Tile Serial Lite IVIntel FPGA IP Design Example User Guide

Document Version Intel QuartusPrime Version

IP Version Changes

2021.08.18 21.2 2.0.0 Initial release.

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