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External Port DMA Engine for 2137x

Why Discuss DMA Engine for 2137x

DMA Engine for 2137x adds new features such as Delay line DMA (enhanced from 21369) and Tap list DMA.

The description is not yet available in the manual or any of the External documents published.

Bring awareness regarding the Delay line feature.

This presentation gives the outline of these features. An application note is in progress to discuss the feature implementation in detail.

DMA Features for 2137x

Two DMA channels Internal - Internal memory DMA( Reads and writes) Internal - External memory DMA( Writes) External – Internal memory DMA(Reads) Supports toggling DMA direction from one descriptor to other

Types of DMA

Normal DMA Circular Buffer DMA Tap list DMA Circular Buffered Tap list DMA Delay Line DMA

DMA registers for 21375

Registers DescriptionEIEPx Destination Index EMEPx Destination modifyECEPx Destination count IIEPx Internal Index IMEPx Internal modify ICEPx Internal count CPEPx Chain pointer EBEPx Circular buffer pointerTPEPx Tap list pointerELEPx Circular buffer lengthEPTCx Tap count

Normal Chaining DMA TCB

Address Register valueCPEPx[18:0] IIEPx (Internal Index)CPEPx[18:0] – 0x1 IMEPx (Internal modify)CPEPx[18:0] – 0x2 ICEPx (Internal count)CPEPx[18:0] – 0x3 EIEPx (Destination Index)CPEPx[18:0] – 0x4 EMEPx (Destination modify)CPEPx[18:0] – 0x5 CPEPx (Chain pointer)

Note :- During TCB loading, ECEPx is loaded with ICEPx. For normal DMA’s without chaining ECEPx must be explicitly given a value for DMA to operate correctly.

Circular Buffer DMA chaining TCB

Address Register value CPEPx[18:0] IIEPx (Internal index) CPEPx[18:0] – 0x1 IMEPx (Internal modify) CPEPx[18:0] – 0x2 ICEPx (Internal count) CPEPx[18:0] – 0x3 EIEPx (Destination Index) CPEPx[18:0] – 0x4 EMEPx (Destination modify) CPEPx[18:0] – 0x5 EBEPx (Circular buffer pointer) CPEPx[18:0] – 0x6 ELEPx (Circular buffer length) CPEPx[18:0] – 0x7 CPEPx (Chain pointer)

Tap list DMA (Reads)

Tap list DMA TCB

Address Register value CPEPx[18:0] IIEPx (Internal Index) CPEPx[18:0] – 0x1 IMEPx (Internal modify) CPEPx[18:0] – 0x2 ICEPx (Internal count) CPEPx[18:0] – 0x3 EIEPx (Destination Index) CPEPx[18:0] – 0x4 EMEPx (Destination modify) CPEPx[18:0] – 0x5 EPTCx (Tap list count) CPEPx[18:0] – 0x6 TPEPx (Tap list pointer) CPEPx[18:0] – 0x7 CPEPx (Chain pointer)

Circular Buffer Tap list DMA (Writes)

Circular Buffered Tap list DMA

Address Register value CPEPx[18:0] IIEPx (Internal Index) CPEPx[18:0] – 0x1 IMEPx (Internal modify) CPEPx[18:0] – 0x2 ICEPx (Internal count) CPEPx[18:0] – 0x3 EIEPx (Destination Index) CPEPx[18:0] – 0x4 EMEPx (Destination modify) CPEPx[18:0] – 0x5 EPTCx (Tap list count) CPEPx[18:0] – 0x6 TPEPx (Tap list Pointer) CPEPx[18:0] – 0x7 EBEPx (Circular buffer pointer) CPEPx[18:0] – 0x8 ELEPx (Circular buffer length) CPEPx[18:0] – 0x9 CPEPx (Chain pointer)

Delay Line DMA Features

Supports Normal DMA writes followed by tap list DMA reads with limited core interaction.

Useful for filter implementation.

For Filter implementations usually circular buffer DMA writes followed by circular buffer DMA reads are used.

Delay Line DMA Access

Writes to Destination buffer(EIEPx)

Registers used

IIEPx – Internal index IMEPx – Internal modify ICEPx - Internal count EIEPx – Destination index EMEPx – Destination modify EBEPx – Circular buffer pointer (optional) ELEPx - Circular buffer length (optional)

When the writes are done (ICEPx =zero), EIEPx(write pointer) is written back to the internal memory location of the TCB .

write pointer serves two purposesDestination Index for writes for next DMA in chainingSource Index for reads for current Delay line DMA

Delay Line DMA Access cont.

Reads from External memory

Read Registers used (Destination)EPRI – Destination index physically same as IIEPx during readsEPRC – Read count for every tap same as ICEPxIMEPx - Destination modifier for reads

EPTCx - number of Taps.EPTC* EPRC – Total number of reads per Delay line DMA

Delay Line DMA Access cont.

Read Registers used (source)EIEPx - Source index for reads. Reads start from where writes

ended.

TPEPx - Tap list pointer

EBEPx – Circular buffer pointer (optional)

ELEPx - Circular buffer length (optional)

EPRMx – Source read modifiers same as (EMEPx) used in pre-modify addressing mode along with Tap list values.

Delay Line DMA Access cont.

For each Tap External read index is EIEPx + TL[N] - the first read address for tap N EIEPx + TL[N] + 1*EPRM - the second read address for tap N EIEPx + TL[N] + 2*EPRM - the third read address for tap N … EIEPx + TL[N] + EPRC-1 * EPRM - the final read address for tap N

EIEPx + TL[N+1] -the first read address for tap N+1 EIEPx+ TL[N+1] + 1*EPRM -the second read address for tap N+1

TL[N] is the first Tap List entry in the internal memory as pointed by TPEPx – the Tap List Pointer. Tap list values can be negative.

When both ECEPx and EPTCx become zero the delay line DMA access is over. Interrupts occur at the end of Delay line DMA access or the end of DMA chain based on PCI bit CPEPX register.

Delay Line DMA Access cont.

Delay line DMA TCB

Address Register value

CPEPx[18:0] IIEPx (Internal Index) CPEPx[18:0] – 0x1 IMEPx (Internal modify) CPEPx[18:0] – 0x2 ICEPx (Internal count) CPEPx[18:0] – 0x3 EIEPx (Destination Index) CPEPx[18:0] – 0x4 EMEPx (Destination modify) CPEPx[18:0] – 0x5 EBEPx (Circular buffer pointer) CPEPx[18:0] – 0x6 ELEPx (Circular buffer length) CPEPx[18:0] – 0x7 EPRI (Read Index (IIEPx)) CPEPx[18:0] – 0x8 EPRC (Read Block Size (ICEPx)) CPEPx[18:0] – 0x9 EPRM (Read Modifier (EMEPx)) CPEPx[18:0] – 0xa EPTCx ( Tap list count) CPEPx[18:0] – 0xb TPEPx (Tap list pointer) CPEPx[18:0] – 0xc CPEPx (Chain pointer)

Delay Line DMA Example

Initializing Delay Line DMA

Configure AMICTL or SDCTL .

Intialize Delay line TCB in internal memoy. Initialize CPEPx register .Set PCI bit in CPEPx if interrupts are needed after the end of each Delay Line DMA block.

Enable DMA (DMAEN), Delay Line DMA (DLEN), chaining (CHEN) in EPDMACTL. Advisable that the DMA FIFO (6 deep) is flushed (DFLSH) along with enabling of DMA. If Circular Buffering is needed (which is normally the case) enable it by setting CBEN.

Note : DL DMA can be enabled only with chaining and all the chained DMA blocks will follow the DL DMA Access procedure. It is not possible to mix normal DMA with Delay Line DMA in the chained DMA .

External port DMA differences between ADSP-21375 and ADSP-21369

The main difference between the Delay line DMA for the two processors occurs during reads.

For 21369 , the number of reads per tap is one whereas for 21375 the number of reads per tap is equal to EPRC (read count) value.

The total number of reads for 21375 is EPRC*EPTC whereas for 21369 it is EPRC per single Delay line transfer.

21369 does not explicitly support Tap list DMA

On the fly modification of DMA direction between TCBs in chaining is not supported in 21369

21375 chain pointer register includes a bit CPDR (bit 20) for determining the direction for the TCB it points to. Setting OFCEN bit in the DMACx register enables the CPDR bit.

DMACx register for the two processors is different due to the enhancement to external port DMA in 21375

External port DMA differences between ADSP-21375 and ADSP-21369

DMACx register control bits for 21375 =============================DEN (BIT_0)TRAN (BIT_1)CHEN (BIT_2)DLEN (BIT_3)CBEN (BIT_4)DFLSH (BIT_5)WRBEN (BIT_7)OFCEN (BIT_8)TLEN (BIT_9)INTIRT (BIT_12)DFS (BIT_17|BIT_16)DMAS (BIT_20)CHS (BIT_21)TLS (BIT_22)WBS (BIT_23)EXTS (BIT_24)DIRS (BIT_25)

DMACx register control bits for 21369=============================DEN (BIT_0)TRAN (BIT_1)CHEN (BIT_2)DLEN (BIT_3)CBEN (BIT_4)DFLSH (BIT_5)TFLSH (BIT_6)FIFO_EMPTY (0x00000000)FIFO_PARTIAL (BIT_7)FIFO_FULL (BIT_7|BIT_8)TFIFO_EMPTY (0x00000000)TFIFO_PARTIAL (BIT_9)TFIFO_FULL (BIT_9|BIT_10)DMAS (BIT_11)CHS (BIT_12)TLS (BIT_13)WBS (BIT_14)EXTS (BIT_15)DIRS (BIT_16)

DMACx registers