experiment 2
DESCRIPTION
VHDL code for gates,FFsTRANSCRIPT
![Page 1: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/1.jpg)
Experiment 2 Name : Rohan Makwana (12MECV16)
Title :Design, simulate and synthesize the following components using all
different possible modelling styles.
A. All gates
B. All latches
C. All flipflops
D. Master- slave flipflops.
A. All gates :
• VHDL CODE:
• RTL Schematics:
![Page 2: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/2.jpg)
• Timing Diagram:
2
B. All latches:
• D Latch :
• VHDL Code for D latch:
• a
• RTL Schematics:
![Page 3: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/3.jpg)
• Timing Diagram:
• SR Latch:
• VHDL CODE FOR SR LATCH (Behaviour Model):
• RTL Schematic :
![Page 4: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/4.jpg)
• Timing Diagram:
1
S R Q(+)
0 0 Remains same (previous)
state
0 1 0
1 0 1
1 1 Invalid State
A : S=0 and R=0 so, output should remains on same state.
B: S= 1 and R= 1 so, we get Q= 0 and also Q' = 0 -- Invalid operation.
C: S = 0 and R= 1 so, Output Q=0 and Q' = 1.
D: S=1 and R=0 so, Q=1 and Q'=0.
A B C D
![Page 5: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/5.jpg)
• VHDL Code for SR Latch (Structural):
• RTL Schematic:
![Page 6: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/6.jpg)
• Timing diagram:
• D Flipflops :
• VHDL Code :
![Page 7: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/7.jpg)
• RTL Schematic:
![Page 8: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/8.jpg)
• Timing diagram:
1. Simple D FF (not considering preset and clear state)
2. If Preset = 1 then Q = 1 and Q' = 0.
3. If Clear = 1 then Q = 0 and Q' = 1.
![Page 9: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/9.jpg)
• SR flipflop :
• RTL Schematic:
![Page 10: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/10.jpg)
• Timing diagram:
• JK flipflop :
• VHDL Code:
![Page 11: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/11.jpg)
• RTL Schematic:
• Timing diagram:
![Page 12: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/12.jpg)
• T flipflop:
• VHDL Code:
• RTL Schematic :
![Page 13: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/13.jpg)
• Timing diagram:
• Master Slave JK flipflop :
• VHDL Code :
![Page 14: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/14.jpg)
• RTL Schematic :
![Page 15: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/15.jpg)
• Timing Diagram :
• Master slave D flip flop :
• VHDL Code :
![Page 16: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/16.jpg)
• RTL Schematic :
• Timing Diagram :
![Page 17: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/17.jpg)
• Master slave D flip flop (Structural)
• VHDL Code :
![Page 18: Experiment 2](https://reader030.vdocuments.us/reader030/viewer/2022012401/544dd000b1af9fc8078b4b12/html5/thumbnails/18.jpg)
• RTL Schematic :
• Timing Diagram :