EX.NO:13 IMPLEMENTATION AND STUDY OF STOP AND WAIT PROTOCOL

Aim: To implement and test the stop and wait protocol using LAN trainer kit and ViRtSim.

Theory: Stop and wait protocol is an efficient way of dealing errors during transmission. The stop and wait protocol stops the transmission of packets when the loss of data or any other error causes a negative acknowledgement to reach the transmitting computer (ie) the transmitting computer waits for a kind of acknowledgement from the receiving computer. If the receiving computer acknowledges the sent data, the transmitting computer sends the next data. If the receiver sends a negative acknowledgement then the transmitter retransmits the data. This way the transmission is reliable. Requirements:

1. System installed with ViRtSim software and Xilinx for IMPACT application. 2. ViLAN02 Trainer kit 3. Power cable – 1 4. Parallel cable – 1 5. Serial cable – 1 6. LAN cable – 1 (long), 4 – (short)

Connections:

Note: The connection is made with the NIC 1 ,hence the parallel cable and serial cable should be connected to the ports available for NIC 1 in the kit, which is just behind it.

Procedure: 1. Give the connections between System and Trainer kit as mentioned above. 2. First set the kit to “Programming mode”

i) Downloading ARM: 1. Open ViRtSim software either from desktop or from Start menu or from “C Program Files Network Simulator ViRtSim”. 2. Select “Utilities ARM Downloader” . 3. “LPC 2000 Flash Utilities” window will appear. Click “Read Device ID”. Then a window will appear with the message “Please reset your LPC 2000 board now and then press OK”. 4. So press “A RST” button in the Trainer kit of the corresponding NIC once and click OK in the system. In the left bottom corner you will get the display as “Read part ID successfully”. 5. Then select the required file by clicking browse button in the “File name:”. That is “D Hexbit(3s400) Stop-and-Wait 120 ARM LAN-stop_wait-120.hex” and click “Open”. 6. After selecting the particular file press “Upload to Flash”. The Progress bar gets Blue color as the data is being sent to RAM. If sent, “File upload successfully completed” message will be displayed in the left bottom corner of that window. 7. Now minimize this window. In the Trainer kit change the mode to “Execution” of the corresponding NIC and press “A RST” once.

i) Downloading FPGA: 1. Open “Impact” from Start menu directly or Start Xilinx ISE.92 Accessories Impact.

2. Select D (ViLAN) Hexbit(3s400) Stop-and-Wait-120 FPGA stopandwait.bit and click “Open”. So that the Main window’s chip diagram color changes to grey. 3. Then again “Progress Dialog” window will execute the command and display as “Program Succeeded”.

iii) Simulating Stop-and-Wait: 1. Open OSI Lan Trainer Protocols Stop and Wait. 2. “Stop and Wait” window will appear. 3. Enter the data in the “Data to be sent” box. 4. Click “Ping”, thus the Connection Status will be displayed as “Connected”. 5. Then click “Connect” so that the bulb picture in that window will glow (Yellow color). 6. Then click “Send” button in the system. 7. Thus you get the details of “Transmit” and “Receive” columns in the system window.

Output:

Result: Thus stop and wait protocol was implemented and simulated using VI-LAN trainer kit and ViRtSim software.