esd design.pdf

8/14/2019 ESD design.pdf

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ELE863/EE8501 VLSI Systems

Electrostatic Discharge Protection

BONDPAD

SOURCE

GATE

Fei Yuan, Ph.D, P.Eng.Department of Electrical & Computer Engineering

Ryerson UniversityCopyright c 2006

Copyright (c) F. Yuan 2006 (1)


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OUTLINE

Introduction to ESD

Principle Sources of ESD in ICs

ESD Models

ESD Protection Mechanisms

ESD Protection Devices

ESD Protection Circuits

Layout of ESD Protection Circuits



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Introduction to ESD

What is ESD ?

ESD - Electro-Static Discharge.

ESD is a transient discharge of static charge that arises from eitherhuman handling or a machine contact.

Although ESD is the result of a static potential in a charged object,

the energy dissipated and damage made are mainly due to thecurrent in ICs during discharge.

Most ESD damage is thermally initiated in the form of device /interconnect burn-out or oxide break-down. The basic phenomenonis for sufficient heat to be generated in a localized volumesignificantly faster than it can be removed, leading to a temperaturein excess of the materials safe operating limits.

pn-junction may melt.

Gate oxide may have void formation.

Metal interconnects & Vias may melt or vaporization, leading toshorts or opens.

Gate-oxide breakdown is another form of ESD damage.



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Introduction to ESD (contd)

Why is ESD Critical ?

ESD accounts for more than 10% total failure of integrated circuits.

The aggressive decrease in physical dimensions and increase indoping in modern CMOS technology result in a significant decreasein gate-oxide thickness and pn-junction width Require lessenergy and lower voltages to destroy MOS devices.

0 0.5 1 1.5 2 2.5 30.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Lmin

[m]

Junctiondepth[m]

Figure 1: Scaling of gate oxide thickness of MOS transistors.



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Introduction to ESD (contd)

0 0.5 1 1.5 2 2.5 30.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Lmin

[m]

Junctiondepth[m]

Student Version of MATLAB

Figure 2: Scaling of junction depth of MOS transistors.

20 40 60 80 1005

10

15

20

Gate oxide thickness, tox

[A]

Vt1,V

ox

[V]

Vt1

Vox

Figure 3: Scaling of the breakdown voltage of gate oxide and the avalanche breakdown voltage.

The level of ESD stress, however, does not scale down with thetechnology.



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Principle Sources of ESD in ICs

Human Handling

A person walking on a synthetic floor can accumulated up to 20 kV.This voltage is discharged when the person touches an object that issufficiently at ground. Charge exchange occurs between the personand the object in a very short time duration (10 ns - 100 ns). Thecharging current is approximately 1A - 10A, depending upon thetime constant.

Test and Handling Systems

Equipment can accumulate static charge due to impropergrounding. The charge is transmitted through ICs when it is pickedup for placement in test sockets.

IC Itself is Charged During Transport / Contact

With Charged Objects

ICs remain charged until they come into contact with a groundedsurface (large metal plates /test sockets). Charge is dischargedthrough the pins of ICs. Large currents in the internal interconnectscan result in high voltage inside the devices which can causedamage to thin dielectrics and insulators.



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ESD Models

Human Body Model (HBM)

HBM models the ESD of a human body.

Peak current 1.3A, rise time 10-30ns.

DUT

R=1.5k

C=100pFV (0 )C-

Human body model

Figure 4: Equivalent circuit for the human body model of ESD. The switch closes upon an ESD event.



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ESD Models (contd)

Machine Model (MM)

MM models the ESD of manufacturing / testing equipment.

Peak current 3.7A, rise time 15-30ns, bandwidth 12 MHz.

DUT

C=200pF

V (0 )C-

Machine model

Figure 5: Equivalent circuit for the machine model of ESD. The switch closes upon an ESD event.

ESD stress caused by charged machines is sever because of zerobody resistance.



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ESD Models (contd)

Charge Device Model (CDM)

CDM models the ESD of charged integrated circuits.

Peak current 10A, rise time 1ns.

Gate oxide breakdown is the signature failure of CDM stress, incontrast to the thermal failure signature of HBM and MM stress.

CDM stress has the fastest transient and has the max. peak current.

CDM stress is the most difficult ESD stress to protect against.

DUT

R


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ESD Protection Mechanisms (contd)

Current Limiting Characteristics of n-well Resistors

Impact Ionization

Avalanche Multiplication of pn-junctions

First Breakdown (Avalanche Breakdown) of nMOS

Second Breakdown (Thermal Breakdown) of nMOS



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Current Limiting Characteristics of n-well Resistors

Conductivity

Majority charge carriers are free electrons.

At low voltages, the velocity of free electrons (majority chargecarriers) and that of holes (minority charge carriers) in a n-well

resistor are linearly proportional to the field intensity of the appliedelectric field a linear resistor with a constant resistance.

vn=nE, vp=pE, (1)

where vn andvp are the velocity of free electrons and that of holes,respectively, n andp are the bulk mobility of free electrons andholes, respectively.

The total charge crossing a cross-section of area Aper second isgiven by

Q= (vnn+vpp)Aq, (2)

where nandp are the concentration of free electrons and holes,

respectively, andq is the charge of an electron.

The current densityis obtained from

J=Q

A= (nn+pp)qE=E, (3)



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where

= (nn+pp)q (4)

is the conductivity.

Current Density

For n-type, the concentration of free electronics is approximately

the doping of the donors, i.e. nnn, wherenn is the doping ofdonors, we have vnnE. Consequently

JJn= (nnnE)q=nnvnq=E (5)

Jis linearly proportional to Eor equivalently the voltage across thesemiconductors.



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Velocity Saturation

At high voltages, the velocity of free electrons saturates due to theincreasing collision with silicon lattices. As a result, the currentthrough n-well resistors remains nearly constant regardless ofvoltage increase

Jsat=nnvn,satq (6)

vn,sat107cm/s,nn= 10

17/cm3 Jsat= 1.6105A/cm2.

E

vn

vsat

104

V/cm0

Ohmic region Saturation region

(10 cm/s)7

Figure 7: Velocity saturation

n-well resistors exhibit a large resistance in the saturation regionshow above.

n-well resistors in the saturation region can be used ascurrent-limiting devices for ESD protection by limiting the amountof ESD discharging current.



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Avalanche Multiplication in pn-junctions

When a pn-junction is reverse biased, the reverse current (leakagecurrent) is solely due to (i) the movement of thermally generatedcharge carriers in the depletion region and (ii) the diffusion ofcharge carriers in the neutral regions.

When the reverse biasing voltage exceeds Vsat= 105V/cm, the

carriers in the depletion region can impart enough energy in thecollision with the silicon lattices to generate electron-hole pairs,which become free charge carriers. These charge carriers are thenaccelerated, collide with the silicon lattices, and create more freecharge carriers Avalanche Multiplication.

Si Si

Si

Si

Si

Si Si Si

Si

Si

Covalent bonds

Si Si

Si

Si

Si

Si Si Si

Si

Si

Si Si

Si

Si

Si

Si Si Si

Si

Si-

Free electron

Hole

-

-

Holes

Covalent bonddestroyed

Strike the covalent bondand destroy it

Figure 8: Avalanche multiplication



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Avalanche Breakdown of nMOS

Parasitic Lateral Bipolar Transistor in nMOS

p+

PAD

n+ n+

Rsub

Isub

p-substrate

D

G

S

VB

Figure 9: Parasitic lateral BJT in nMOS transistors.

nMOS is used as ESD protection devices.

Gate is grounded to ensure nMOS is off under normal operationconditions.

Drain-substrate/source-substrate pn-junctions are reverse biased.

A parasitic lateral BJT as shown exists in the substrate.

Under normal operation conditions, this parasitic BJT is off becauseboth the pn-junctions of the nMOS transistor are reverse biased.



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Avalanche Breakdown of Drain pn-junction of nMOS

WhenVD increases, the electric field across the drain-substratedepletion region becomes high enough such that avalanchemultiplication occurs at the drain-substrate junction electron-hole pairs are generated.

The generated free electrons go to the drain due to its high

potential, whereas the generated holes go to substrate due to its lowpotential It gives rise toIsub The base potentialVB =RsubIsubis increased subsequently.

WhenVB is sufficiently high, the source-substrate pn-junctionbecomes forward biased electrons in the source (emitter) areemitted to the substrate (base) the parasitic lateral BJT is ONAvalanche Breakdown.

The turn-on time of the parasitic BJT is determined by the basetransit time (b= 250ps for 1 m channel length).

Note the fundamental differences between the parasitic BJT andnormal BJTs. The base width of the parasitic BJT equals to thechannel length of the nMOS transistor (in the range ofm),whereas that of a normal BJT is very small (in the range ofA).



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Snapback

VD

I D

Vsh

(V , I )t2 t2

Snapback region(ESD protectionoperation region)

Thermalbreakdownregion

Avalanchebreakdown

Thermalbreakdown

Slope=1/Rsh

(V , I )t1 t1

Figure 10: Avalanche breakdown, snap back, and thermal breakdown of nMOS transistors.

When the BJT is ON, more electrons flows from the source to thedrain IDandVD decreases sharply until the snapback holdingvoltageVsp is reached. The snapback holding voltage is mainlyacross the drain-substrate pc-junction. The marginal increase of thedrain voltage is due to voltage drop across the drain diffusion,source diffusion, and contact resistance.

During snapback, the resistance has positive temperature

coefficients. This implies that if the current in any region increases,the temperature of the region will increase, thereby increasing theresistance, which encourages the current to flow elsewhere current is conducted uniformly by all figures of nMOS transistors.



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Thermal Breakdown of nMOS

During snapback, the current of nMOS increases with the externalvoltageVDS.

IfVDScontinues to increase, the device enters the thermalbreakdown with the onset of the thermal breakdown, theresistance of the current path has negative temperature coefficients,

encourages current to concentrates in certain localized fingers ofnMOS and eventually destroys the fingers.

The concentration of ESD current into a few fingers indicates thatno matter how many fingers are used, only a few will be activatedin case of an ESD strike ESD current capability of the devicedoes not scale with its size.

To enhance the self-protection of ESD protection devices, thecurrent must flow UNIFORMLY among all fingers of ESDprotection devices.



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Avalanche Breakdown versus Thermal Breakdown

If the avalanche breakdown voltage of ESD protection devices isLESS THAN their thermal breakdown voltage, then the avalanchebreakdown occurs before the thermal breakdown ESD stresswill be released by the avalanche breakdown and the devices willnot enter the thermal breakdown.

If the avalanche breakdown voltage of ESD protection devices isGREATER THAN their thermal breakdown voltage, the avalanchebreakdown will occur at a voltage higher than the thermalbreakdown voltage. After the avalanche breakdown occurs, VDS willstill higher than the thermal breakdown voltage the devices willenter thermal breakdown and concentrate currents in a localizedarea due to negative temperature coefficients device will bedestroyed.

VD

I D

Vsp VD

I D

Vsp VD

I D

Vsp

Avalanchebreakdown

Thermalbreakdown

Thermalbreakdown

Avalanchebreakdown

VV < Vt1 t2 VV < Vt2 t1

(A) Avalanche breakdown voltage is less thanthermal breakdown voltage

(B) Avalanche breakdown voltage is greater thenthermal breakdown voltage

Figure 11: Avalanche breakdown/thermal breakdown voltages



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ESD Protection Devices

n-well Resistors

Gated-Grounded nMOS Transistors (GGNMOS)

Gated-Coupled nMOS Transistors (GCNMOS)

Silicon Controlled Rectifiers (SCR)

Medium Voltage Triggered SCR



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ESD Protection Devices (contd)

n-well Resistors

P-substrate

SiO2

PolySiO2

M1 M1

P-substrate

M1 M1

SiO2

N-well

n+

Poly-resistor N-well resistor

Figure 12: Poly and n-well resistors

Poly-resistors should not be used as ESD protection devices due totheir poor heat dissipation capability (Poly resistors are isolatedfrom the substrate by the SiO2 layer). Note that the heat generatedby ICs are taken away via two paths (i) PADs/traces/pins and (ii)substrate/ground plate.

n-well resistors have good contact with the substrate. They areused as primary current-limiting devices.

When a n-well resistor is used as the current-limiting device,together with a nMOS (primary ESD protection device), it isessential to make sure that the n-well resistor will not enter itsthermal breakdown when the nMOS is in its avalanche breakdown.



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Diodes

p-substrate

n-well

p+ n+

PADInternalcircuits

Rn-well

p-substrate

p-welln+ p+

Rp-well

(a) p+/n-well diodes

(b) n+/p-well diodes

p+/n-well diode

n+/p-well diode

pn-junction

Figure 13: Diodes in CMOS. (a) p+/n-well diodes; (b) n+/p-well diodes; (c) ESD protection usingdiodes.

Two main types of diodes : n+/p-well diodes and p+/n-well diodes.p+/n-well diodes have a pn-junction between the n-well andp-substrate whereas there is no isolation between the diode and thep-substrate inn+/p-well diodes.

When forward-biased, diodes can sustain a large current with asmall device dimension.



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Gate-Grounded nMOS Transistors

PAD

p-substrate

n+

DS SS

D G S

RD

RS

Rsub

Figure 14: Drain contact-gate spacing (DS) and source contact-gate spacing (SS) of ESD protectionnMOS transistors.

During a ESD strike, the pn-junction at the drain undergoes anavalanche breakdown. Holes flow to the substrate, resulting in anincrease inVB parasitic BJT will be turned on ESDcurrent flows from the collector the (drain of nMOS) to the emitter(the source of nMOS that is connected to the ground) ESDstress at the drain of the nMOS transistor (PAD) is released.

The dimensions of ESD nMOS should be large enough to handlelarge ESD currentsmultiple fingers structure is used to

implement ESD nMOS.

The main design parameters of nMOS are (i) channel length, (ii)drain contact-to-gate spacing, and (iii) device width. The sourcecontact-to-gate spacing is not critical and is kept at its minimumdesign value.



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i) The minimum channel length is good for efficient turn-on but thepunch-through limit will be reduced.

ii) Drain contact-to-gate spacing affects the resistance of ballastresistors. For silicided processes, the minimum drain contact-to-gatespacing is used.

iii) Device width determines the maximum current that the devicecan conduct.



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Gated-Grounded nMOS Transistors (contd)

G

S

D

n+1 2 3 4

Metal-1Metal-2

Contact/via

n-well ballastingresistor

Figure 15: Lumped ballast resistors are added at the drains to ensure a uniform ESD current distri-bution among the fingers of ESD protection transistors.

During an avalanche breakdown, the current flowing through the

drain increases. However, the positive temperature coefficient of theresistance ofn+-diffusion (calledBallast Resistors) at the drainprevents current from concentrating in a localized region itforces the ESD current to flow into other fingers uniformcurrent distribution is achieved.

The effect ofn+-diffusion resistance is virtually eliminated insilicided CMOS processes because in these processes n+ is silicidedand the resistance of silicided n+ is small (a few ohms).

To preserve the current-limiting ability of ballast resistors, explicitn-well ballast resistors at the drain are added. Note that the sheetresistance of n-well is much higher than that ofn+-diffusion.



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Gate-Coupled nMOS Transistors

In most applications, the gate of ESD nMOS is grounded to ensurethat the ESD nMOS will not cause any extra leakage at the pinduring normal operation (Without ESD).

The avalanche breakdown voltage is reduced if the gate of nMOS isproperly biased during a ESD strike.

The gate voltage helps reduce the width of the pn-junction at thedrain increase the electric field in the junction and lower theavalanche breakdown voltage of the junction.

The value ofC andR must be such that (i) they have no effect onthe operation of the circuit when there is no ESD stress, (ii) theymust couple a sufficient voltage to the gate during a ESD strike

such that the avalanche breakdown voltage of nMOS is effectivelyreduced.



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Gate-Coupled nMOS Transistors (contd)

VD

ID

Vsp

Avalanche breakdown

Thermal breakdown

Reduced avalanche breakdown

Internal

circuitsC

R

PAD

VG

VDS

(Avalanchebreakdown

voltage)

Figure 16: Gate-coupled nMOS



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Drawbacks of nMOS-based ESD Protection

Effective for non-silicided processes. Less effective for silicidedprocesses.

Need additional ballast n-well resistors to increase ESD protection.

Need gate-coupling circuitry to improve ESD protection.



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Silicon-Controlled Rectifiers (SCR)

p+

PAD

Rsub Ic2

p-substrate

n+ n+ p+

Internalcircuits

T1 T2n-well

Rnwell

pn-junction

Figure 17: Silicon-controlled rectifiers (SCRs).

Under normal operation, the pn-junction between n-well andp-substrate is reverse biased and SCR has no effect on the operationof the protected circuits.

During a ESD strike, the pn-junction undergoes an avalanchebreakdown currents flow from n+ throughRnwell to thesubstrate a sufficient voltage drop acrossRnwellturns on T2 a large current flows from p+-diffusion throughRsubto the groundT1 turns on T1 and T2 latch up to release ESD stress.

SCR has a high ESD breakdown voltage (40V with the latch-uptime 1ns) as compared with that of nMOS because the breakdownvoltage of n+/p-sub is lower than that of n-well/p-sub (large

pn-junction width) internal circuits might have already beendestroyed even before ESD protection circuits are activated.

SCR is not affected by silicidation attractive for modern CMOSprocesses where silicidation is common.



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Medium-Voltage Triggered SCR

An additional n+ is added at the edge of the n-well to reduce thejunction width.

p+

PAD

Rsub Ic2

p-substrate

n+ n+ p+

Internalcircuits

T1 T2n-well

Rnwell

n+

n+-diffusionis added

Figure 18: Modified silicon-controlled rectifiers (MSCRs).

During an ESD strike, pn-junction in this region undergoes anavalanche breakdown at a LOWER voltage.

Breakdown voltage : 25V for 0.35CMOS (40V for conventionalSCR).



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Low-Voltage Triggered SCR

An additional n+ is added at the edge of the n-well to reduce thejunction width.

p+

PAD

Rsub Ic2

p-substrate

n+ n+ p+

Internalcircuits

T1 T2n-well

Rnwell

n+

Grouded-gateis added

Figure 19: Low-voltage silicon-controlled rectifiers (LVTSCRs).

The added gate-grounded nMOS enters avalanche breakdown first.

Avalanche voltage is similar to gate-grounded nMOS (10Vapproximately).



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Requirements of ESD Protection Circuits :

Provide a low-impedance path from input pads to the ground duringan ESD strike to release the static charge accumulated on the pads.

Clamp the voltage of the pads at a level that is below the dielectricbreakdown voltage of thin transistors during an ESD strike.

Provide a very high impedance and a low capacitance duringnormal operation such that it has a little effect on the operation ofthe protected circuits.



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Basic Configuration

Primary ESDElements

Currentlimitingresistor

Secondary ESDElementsPAD Internal

circuits

Figure 20: Configuration of ESD protection circuits

Primary ESD protection elements shunt most of ESD currents.

Primary ESD protection elements have large width and need moretime to turn on.

Secondary ESD protection elements serve to limit the voltage at thecircuit being protected until the primary ESD protection devices arefully operational. Secondary ESD protection devices have smallerwidth.

The effectiveness of the primary ESD protection devices isdetermined by the secondary protection stage. Note that due to thesmall dimensions, the secondary protection devices enter avalanchebreakdown before the primary protection devices are activated. It iscritical to ensure that the avalanche breakdown of the primaryprotection devices is activated before the secondary protectiondevices enter their thermal breakdown so that the secondary ESDprotection devices will not be destroyed by ESD stress.

Current-limiting resistor has two functions (i) limit the currentflowing into the internal circuits. (ii) withstand some ESD voltageso that the secondary protection circuit will not be damaged in anESD strike.



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ESD Protection Circuits (contd)

Basic Circuits

PAD Internalcircuits

R

Primary ESD elements Secondary ESD elements

Current-limitingresistor

Figure 21: Basic ESD protection circuits

Both nMOS and pMOS are used for positive and negative ESDstrikes.

Under normal operation conditions, ESD devices are off

minimize the leakage current of these devices.



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ESD of 0.35 CMOS Processes

In sub-micron CMOS, the onset of damage has been observed atbetween 1 kV and 2kV.

Design rules are set for 2 kV HBM and 200V MM.

Min. resistance of the isolation n-well resistor : 200 .

Soft-pull is used to balance the breakdown voltage and the speed of

I/O fingers under ESD zapping.



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Distributed ESD Protection Circuits

De-centralize a large capacitance into a set of small capacitancesseparated by inductors - a transmission line is constructed capable of transmitting high-frequency signals.



zo

zozo zozo

C

zo

C

zo

C

zo

C

zin

Figure 22: Top - Distributed ESD protection with equal sections; Bottom - small-signal equivalentcircuit.



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Multi-Finger Turn-On (MFT)

Thermal breakdown voltage of each finger of a large ESD protectiontransistor is made higher than the avalanche breakdown voltage ofthe finger.

Lumped resistors are added at source and drain. The one at drainfunctions as ballast resistors while the one at source sense the ESD

current and generates a voltage that is applied to the gate of theadjacent finger behave as a gate-coupled nMOS transistor.

PAD InternalcircuitsRd Rd Rd Rd

RsRsRsRs

Figure 23: Equivalent circuit of poly back-end ballast with segmentation.



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Soft-Ground-Gate nMOS MFT

Based on substrate pick-up technique when an ESD strikeoccurs, the potential of substrate increases. The gate potentialincreases as well behaves as gate-coupled nMOS transistor thathave a low avalanche breakdown voltage (better ESD protection).

PAD Internal

circuitsRd Rd Rd Rd

RsRsRsRs

Figure 24: Equivalent circuit of a soft-grounded-gate nMOS MFT.



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Domino nMOS MFT

Lumped resistors are added at source and drain. The one at drainfunctions as ballast resistors while the one at source sense the ESDcurrent and generates a voltage that is applied to the gate of theadjacent finger behave as a gate-coupled nMOS transistor.

PAD Internal

circuitsRd Rd Rd Rd

Rs1Rs1Rs1Rs1

Rs2Rs2Rs2Rs2

Macro-ballastingresistors

Figure 25: Equivalent circuit of domino nMOS MFT.

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