epc2024 – enhancement mode power transistor...j = 25 c unless otherwise stated) parameter test...

eGaN® FET DATASHEET EPC2024

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1

EFFICIENT POWER CONVERSIONG

D

SHAL

Maximum Ratings

PARAMETER VALUE UNIT

VDS

Drain-to-Source Voltage (Continuous) 40V

Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 48

ID

Continuous (TA = 25°C, RθJA = 6°C/W) 90A

Pulsed (25°C, TPULSE = 300 µs) 560

VGS

Gate-to-Source Voltage 6V

Gate-to-Source Voltage -4

TJ Operating Temperature -40 to 150°C

TSTG Storage Temperature -40 to 150

Thermal Characteristics

PARAMETER TYP UNIT

RθJC Thermal Resistance, Junction-to-Case 0.4

°C/W RθJB Thermal Resistance, Junction-to-Board 1.1

RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 42Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.

All measurements were done with substrate connected to source.

Static Characteristics (TJ = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITBVDSS Drain-to-Source Voltage VGS = 0 V, ID = 1.1mA 40 V

IDSS Drain-Source Leakage VGS = 0 V, VDS = 32 V 0.1 0.9 mA

IGSSGate-to-Source Forward Leakage VGS = 5 V 1 9 mA

Gate-to-Source Reverse Leakage VGS = -4 V 0.1 0.9 mA

VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 19 mA 0.8 1.4 2.5 V

RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 37 A 1.2 1.5 mΩ

VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.8 V

EPC2024 – Enhancement Mode Power Transistor

VDS , 40 VRDS(on) , 1.5 mΩID , 90 A

EPC2024 eGaN® FETs are supplied only inpassivated die form with solder bumps. Die Size: 6.05 mm x 2.3 mm

Applications: • High Frequency DC-DC Conversion

• Motor Drive

• Industrial Automation

• Synchronous Rectification

• Inrush Protection

• Point-of-Load (POL) Converters

Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.

https://www.epc-co.com


https://www.epc-co.com/epc/Products/ eGaNFETsandICs/EPC2024.aspx

http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf

https://www.epc-co.com/epc/Products/ eGaNFETsandICs/EPC2024.aspx

eGaN® FET DATASHEET


EPC2024

Dynamic Characteristics (TJ = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CISS Input Capacitance

VDS = 20 V, VGS = 0 V

1920 2300

pF

COSS Output Capacitance 1620 2430

CRSS Reverse Transfer Capacitance 29

COSS(ER) Effective Output Capacitance, Energy Related (Note 2)VDS = 0 to 20 V, VGS = 0 V

2050

COSS(TR) Effective Output Capacitance, Time Related (Note 3) 2240

RG Gate Resistance 0.3 Ω

QG Total Gate Charge VDS = 20 V, VGS = 5 V, ID = 37 A 18 24

nC

QGS Gate-to-Source Charge

VDS = 20 V, ID = 37 A

5.1

QGD Gate-to-Drain Charge 2.4

QG(TH) Gate Charge at Threshold 3.8

QOSS Output Charge VDS = 20 V, VGS = 0 V 45 68

QRR Source-Drain Recovery Charge 0All measurements were done with substrate connected to source.Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.

500

400

300

200

100

00 0.5 1.0 1.5 2.0 2.5 3.0

I D – D

rain

Curre

nt (A

)

VDS – Drain-to-Source Voltage (V)

VGS = 5 VVGS = 4 VVGS = 3 VVGS = 2 V

Figure 1: Typical Output Characteristics at 25°C

4

3

2

1

02.5 3.0 3.5 4.0 4.5 5.0

R DS(o

n) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ)

VGS – Gate-to-Source Voltage (V)

ID = 35 AID = 70 AID = 140 AID = 210 A

Figure 3: RDS(on) vs. VGS for Various Drain Currents

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

25°C125°C

VDS = 3 V

I D – D

rain

Curre

nt (A

)


Figure 2: Transfer Characteristics

500

400

300

200

100

0

25°C125°C

ID = 37 A

R DS(o

n) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ)


Figure 4: RDS(on) vs. VGS for Various Temperatures

4

3

2

1

02.5 3.0 3.5 4.0 4.5 5.0




EPC2024

All measurements were done with substrate shortened to source.

1000

100

10

Figure 5b: Capacitance (Log Scale)

Capa

citan

ce (p

F)


COSS = CGD + CSDCISS = CGD + CGSCRSS = CGD

0 10 20 30 40

500

400

300

200

100

0

I SD –

Sour

ce-to

-Dra

in Cu

rrent

(A)

VSD – Source-to-Drain Voltage (V)

Figure 7: Reverse Drain-Source Characteristics

25°C125°C

0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.60 25 50 75 100 125 150

Norm

alize

d Th

resh

old

Volta

ge

TJ – Junction Temperature (ºC)

ID = 19 mA

Figure 9: Normalized Threshold Voltage vs. Temperature

3500

3000

2500

2000

1500

1000

500

00 10 20 30 40

Capa

citan

ce (p

F)


COSS = CGD + CSDCISS = CGD + CGSCRSS = CGD

Figure 5a: Capacitance (Linear Scale)

5

4

3

2

1

00 5 10 15 20

V GS –

Gat

e-to

-Sou

rce V

olta

ge (V

)

QG – Gate Charge (nC)

ID = 37 AVDS = 20 V

Figure 6: Gate Charge

2.0

1.8

1.6

1.4

1.2

1.0

0.80 25 50 75 100 125 150

Norm

alize

d On

-Sta

te R

esist

ance

– R

DS(o

n)

TJ – Junction Temperature (ºC)

ID = 37 A

VGS = 5 V

Figure 8: Normalized On-State Resistance vs. Temperature




EPC2024

Figure 11: Transient Thermal Response Curves

Duty Factors:0.5

0.10.050.020.01

Single Pulse

1

0.1

0.01

0.001

0.000110-5 10-4 10-3 10-2 10-1 1 10

Transient Thermal Response Curves (Junction-to-Board)

tp, Rectangular Pulse Duration, seconds

Z θJB

, Nor

mal

ized T

herm

al Im

peda

nce

Notes:Duty Factor: D = t1/t2Peak TJ = PDM x ZθJB x RθJB + TB

PDM

t1t2

Duty Factors:

Notes:Duty Factor: D = t1/t2Peak TJ = PDM x ZθJC x RθJC + TB

PDM

t1t2

0.5

0.10.2

0.050.020.01

Single Pulse

1

0.1

0.01

0.001

0.000110-6 10-5 10-4 10-3 10-2 10-1 1

Transient Thermal Response Curves (Junction-to-Case)

tp, Rectangular Pulse Duration, seconds

Z θJC

, Nor

mal

ized T

herm

al Im

peda

nce

80

60

40

20

00 1 2 3 4 5 6

I G – G

ate C

urre

nt (m

A)


Figure 10: Gate Leakage Current

25°C125°C




EPC2024

2024

YYYY

ZZZZ Die orientation dot

Gate Pad bump is under this corner

Part Number

Laser Marking

Part #Marking Line 1

Lot_Date CodeMarking Line 2

Lot_Date CodeMarking Line 3

EPC2024 2024 YYYY ZZZZ

DIE MARKINGS

2024YYYYZZZZ

TAPE AND REEL CONFIGURATION4 mm pitch, 12 mm wide tape on 7” reel

7” reel

a

d e f g

c

b

Note 1: MSL 1 (moisture sensitivity level 1) classied according to IPC/JEDEC industry standard.Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.

Dieorientationdot

Gatesolder bar isunder thiscorner

Die is placed into pocketsolder bar side down(face side down)

Loaded Tape Feed Direction

Dimension (mm) target min max a 12.00 11.70 12.30 b 1.75 1.65 1.85

c (note 2) 5.50 5.45 5.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10

f (note 2) 2.00 1.95 2.05 g 1.5 1.5 1.6

EPC2024 (note 1)

Figure 12: Safe Operating Area

0.1

1

10

100

1000

0.1 1 10 100

VDS – Drain Voltage (V)

Limited by RDS(on)

I D –

Drai

n Cu

rrent

(A)

Pulse Width 100 ms 10 ms 1 ms 100 µs




EPC2024

RECOMMENDEDLAND PATTERN (units in µm)

RECOMMENDEDSTENCIL DRAWING (units in µm)

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

6050

180

700

X30

2300

400

2030

X30

X28

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

6050

400X34

2300

1330

2050

720

200X35

R601 3 5 7 9 11 13 15 17 19 21 23 25 27 29

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

Information subject to change without notice.

Revised August, 2019

Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing.

Intended for use with SAC305 Type 3 solder, reference 88.5% metals content.

Additional assembly resources available at https://epc-co.com/epc/DesignSupport/ AssemblyBasics.aspx

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

eGaN® is a registered trademark of Efficient Power Conversion Corporation.EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx

Land pattern is solder mask definedSolder mask opening is 180 µmIt is recommended to have on-Cu trace PCB vias

Pad 1 is Gate;Pads 2, 5, 6, 9,10,13,14, 17, 18, 21, 22, 25, 26, 29 are Source;Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23, 24, 27, 28 are Drain;

Pad 30 is Substrate.*

*Substrate pin should be connected to Source

DIE OUTLINESolder Bump View

(685

)

Seating plane

(785

)

100 ±

20

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

A

f

d X30

B

gX4e

c

X30

X28

Pad 1 is Gate;Pads 2 ,5, 6, 9, 10, 13, 14, 17, 18, 21, 22, 25, 26, 29 are Source;Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23, 24, 27, 28 are Drain;

Pad 30 is Substrate.*

*Substrate pin should be connected to Source

DIM

Micrometers

MIN Nominal MAX

A 6020 6050 6080B 2270 2300 2330c 2047 2050 2053d 717 720 723e 210 225 240f 195 200 205g 400 400 400

Side View


https://www.epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

https://www.epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

https://www.epc-co.com/epc/AboutEPC/Patents.aspx

epc2024 – enhancement mode power transistor...j = 25 c unless otherwise stated) parameter test...

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