eonic bv laurens bierens, chief technology officer [email protected] digitally mastering the...

Eonic BVLaurens Bierens, chief technology [email protected]

Digitally Mastering The Spectrum

From Deep Space to Deep SeaDigitally Mastering The Spectrum

Reconfigurable firmware for high-end data flow processing systems

16 October 2003Reconfigurable firwmware for high-end data flow processing systems

2

Outline

• Objective of the presentation

• Eonic BV : the company

• FFT data flow processing

• Connectivity FPGA : Switch Fabric

• SAR: an FFT data flow processing case

• SAR algorithm requirement analysis

• Example system architecture and components

• Conclusions


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Objective of the presentation


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Objective of the presentation

• Introduce the concept of (FFT) data flow processing

• Elaborate on the key reconfigurable firmware item in the data flow driven application : the connectivity FPGA

• Show the necessity of reconfigurable firmware in high-end application fields

• Work out a case example : SAR processing, a high-end data flow driven application


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Eonic BV : the company


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Eonic BV : the company• Result of merger in May 2003 between :

• Eonic Solutions GmbH, focusing on the Atlas Universal DSP Computer• doubleBW Systems BV, spin-off of TNO

• Focus : „Digitally Mastering the Spectrum“

• Products :• PowerFFT : fastest FFT-centric floating point DSP in the world• Digitizing Systems :

• 1.0 to 1.5 Gsps (8bit)• 105 Msps (14bit)• Data recording at up to 180 Mb/sec/channel to RAID disks

• Atlas :• scalable multi-DSP system for back-end processing and system

architecture• based on PowerFFT, ADI TS101S, ADI 21160, Altera Stratix• LVDS point-to-point communication links• Supported by Real-Time System Software


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What markets do we address?

Medical ImagingMedical ImagingMedical ImagingMedical Imaging

TelecomsTelecomsDigital RadioDigital RadioSoftware Defined RadioSoftware Defined Radio

TelecomsTelecomsDigital RadioDigital RadioSoftware Defined RadioSoftware Defined Radio

DefenseDefenseAerospaceAerospace

Embedded

DSP

Computing


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High-end applications• Radar & SAR

• Software Defined Radio

• COMINT & ELINT

• Medical Imaging

• Visual inspection

• Instrumentation

• Sonar & active noise control

• DNA sequencing


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Eonic‘s Total Value Proposition

DigitizingFront-endcomputing

Back-endcomputing

Signal User / info

Eonic covers from front-end to back-end


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FFT data flow processing


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FFT applications• Estimated that 30 to 50 % of all clock cycles in high-end

DSP are used for nothing else than calculating an FFT

• Simplest applications :• calculate frequency power spectrum• analyse signal in its frequency components• recreate signal from its frequency components

• Derived :• correlation, (de)volution• beam forming (far field)• radar, SAR (image forming radar)• communication intelligence, ...• pattern matching :

• visual inspection, object tracking, DNA sequencin• image manipulation (e.g. image rotation)• ...


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Requirements for embedded FFT engine

• Act as co-processor for FFT based algorithms in

programmable environments• Perform FFT based processing in the front-or back-end

datastream• Perform user controlled multidimensional FFT algorithms

in a scaleable way• Integrate easily in embedded environments• Allow bursty and asynchronous data sources and sinks• Allow multiple data input and output formats


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PowerFFT processor• World’s Fastest Stand-Alone FFT Processor

• 1K complex floating point FFT in 10 sec

• What‘s an FFT ? • Transforms time-domain signal into frequency domain• and vise-versa• Basis for many derived algorithms• Most DSP algorithms are defined in frequency domain


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PowerFFT features / benefits

• Sustained 1K complex FFT in 10 microsec, incl. windowing (5.7 GFLOPS on a single chip!) • Additional I/O ports for 4 SDRAM bank extension:

• long FFTs, FFT based multi-dimensional algorithms• overlapped algorithms and (double buffered) corner turn

• Programmable Address Generator FPGA:• cost-effective memory use (SDRAM vs SRAM)• easy upgrades to larger memories• specialized memory use (space / mil applications)

• Extensive data format support:• parallel and sequential I&Q• IEEE floating point, integer 32/16• sign inv. int. 32/16, 2×24+9 / 2×16+8 hybrid f.p.


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Technical Data• 100 MHz I/O clock, 128 MHz internal clock, 3.3/1.8 V

• Power dissipation : max. 2 W, typically 1W

• Manufactured in 0.18 µm standard CMOS

• Data types : 32bit IEEE floating point, 32bit, 16bit

Applications

Radar, SAR, ultrasound, seismic processing, software defined radio, COMINT, ELINT, EW, image processing, beamforming, pattern matching, DNA sequencing, ...

1W1W in operation

suitablesuitable for embedded systems

PowerFFT characteristics


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PowerFFT : a true FFT data flow processor

• PowerFFT is first in new class of programmable DATA FLOW PROCESSOR

• Best system performance by co-design with FPGA and DSP for general purpose applications and higher system-level efficiency

• Data flow processor architecture better adapted to DSP algorithms than classical „von-Neumann“ DSP

• PowerFFT delivers :• fastest 1K Complex FFT• sustained performance at 100 Msps• programmable• low power consumption : 1 W• resulting in small system cost

• DSP (clusters) and FPGA (macro‘s) can also be described as data flow processors, dependent on the application


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The connectivity FPGA : Switch Fabrics


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Connectivity : the key in data flow processing

• A massive data flow processing exploits a «network» of data flow processing nodes

• System performance grows linearly with size

• Every data flow processor node contributes with its own communication links, its own RAM, its own logic-rich FPGA, and its own I/O capabilities

• Application re-maps easily from one to many nodes

From single data From single data flow processor flow processor node ...node ...

... to a network ... to a network of data flow of data flow processing processing nodes...nodes...

... To a complete ... To a complete

Atlas™Atlas™ system system


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Connectivity FPGA : Switch Fabric

• Connectivity is guaranteed by using high speed Switch Fabrics with very fast reconfigurability (5 - 10 clock cycles)

• Two or more controllers are then attached to this Switch Fabric

• Controllers are either “sinks”, “sources”, or “processes”

• Examples are outputs, inputs, a multiplier, an FFT (ADC, DSPs, PowerFFT)

• Controllers are essentially simple autonomous processors - we try to process the data flow in real time

• We basically have a simple, very high speed distributed computing network, one that can usually fit within one FPGA

• It is a flexible and efficient means of bulk processing


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Switch Fabric

PFFTInput

OutputADC

DSP Memory Controllers

LocalPCI

Operation A

Operation B

Example data flow module : connectivity


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One command line …

sets required controllers and Switch Fabric

Switch Fabric

PFFTInput

OutputADC

DSP Memory

LocalPCI

Setting up a configuration


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Subsequent command lines can start immediately if its required controllers are free

Switch Fabric

PFFTInput

OutputADC

DSP Memory

LocalPCI

Setting up the next configuration


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All sequencing is performed by the module’s own sequencer.

Switch Fabric

PFFTInput

Output

ADC

DSPMemory

LocalPCI

Instruction Sequencer

Sequencing the data flows


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Data flow programming concepts

• To best serve the programming of data flow processors we require a new approach:

• We need to explicitly state on which sink and source controller our data resides…

• …and via which processes to flow

• Eonic’s data flow compiler concept : a means for optimum connectivity• There is no need for the flexibility of a normal DSP therefore a new and more

efficient means of compiling data flow instructions is required• The compiler is capable of being modified rapidly to match new hardware

configurations

• Currently embedded in the PowerFFT SDE, porting to generic data flow processors is ongoing


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SAR: an FFT data flow processing case


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What is SAR?• Synthetic Aperture Radar (SAR) is a side looking imaging radar

mounted on an aircraft

• A SAR transmits radar pulses and receives the reflections of the ground

• An image of the illuminated surface of the Earth can be generated by FFT processing the radar data in 2 directions: range (the “look” direction), and azimuth (the “flight” direction)

• SAR processing is characterized by:• Data streams sampled at very high sampling rates• Enormous (FFT) processing requirements, up to TerraFLOPS• Huge multi-dimensional data sets, >> 10k X 10k samples• Multi-dimensional FFT processing “on the fly” in the data flow

• Eonic data flow processing technology and concepts are extremely applicable in SAR processing


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RAMSES multi-frequency SAR from ONERA

Transall C160RAMSES platform

RAMSESKu-band SAR image

• RAMSES is a multi-frequency SAR system operated by ONERA, the French’ leading aerospace establishment


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RAMSES Pre-Processing Unit (RPPU)

• Eonic developed the RAMSES Pre-Processing Unit (RPPU), a high-end real-time SAR data acquisition, processing and storage system• 4 x 1.5 Gsps (8bit) channel, 360 MBytes/sec to raid-0 disk• Prefilter up to 1.5 Gsps, multi-channel sync• 8 x 105 Msps (14bit) + post processing (DSP, PowerFFT, FPGA)


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General system concept

SwitchNetwork

DigitalFront-End

RF Receiver Digital

Analysis

Storage

Off-LineComputer

Operator


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SAR algorithm requirements analysis


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Range compression

ADC

ADC

RangeCompression

I

Q

Sample frequency <=1.5GHz8bit resolution I and Q

2x8bit percomplexsample

Range lines

Nr samples

PRF

Pulse replicaM samples

Nr-M samples

Range compression throughput: PRF X Nr



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Exploit parallelism in azimuth compression

Nr-M samples

Na samples

50%

ove

rlap

AzimuthCompression


Cor

ner

turn

½Na samples

Na samples

AzimuthCompression

2x32bitper realsample

Corne

r tur

n

Na samples

AzimuthCompression


Corner turn

½Na samples

Na samples

AzimuthCompression

2x32bitper realsample

Corner turn

DSP cluster 1

DSP cluster 2

DSP cluster 3

DSP cluster 4


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Algorithm decomposition: processes

DataAcquistion

RangeCompression

1st OrderMotion Comp

CornerTurn

AzimuthCompression

2nd OrderMotion Comp

2D FFT

CornerTurn

AzimuthCompression

2nd OrderMotion Comp

2D FFT

Slant toGround

Conversion

ImageConstruction

1 N

N NN111


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Mapping on data flow processor clustersProcesses Cluster #

Digitizing Digitizer 1

Range Compression PowerFFT 1

1st Order Motion Comp TigerSHARC 1

Corner Turn

Azimuth Compression TigerSHARC N

2nd Order Motion Comp

2D FFT PowerFFT N

Slant-to-Ground Conv

Image construction TigerSHARC 1


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Example system architecture and components


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System architecture

ADC1.5GSPS

Buffer /pre-proc

2 x 8bit

Buffer /pre-proc

2 x 8bit

Analog I

Analog Q

ADC1.5GSPS

clocktrig

reset

RAIDFibreChannel

AtlasPowerFFT

board

AtlasTigerSHARC

board

RAIDinterface

cPCI-host(Pentium)

LIN

K N

ertw

ork P

CIb

us

Monitor


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Atlas 6U dual ADC CompactPCI

Test connect.

JTAG

Temp monitor

Hot swap

PCI64bridge

Com

pact

PC

I bac

kpla

ne

ADCAnalog in A

Synclogic

StratixFPGA

Su

b-D

128MBSDRAM

ADCAnalog in B

Clock

Trigger

Reset

StratixFPGA

128MBSDRAM

clock

res

trig

clk

clock

res

trig

clk

Under Development


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Atlas 6U PowerFFT / 4xTS101S CompactPCI

StratixFPGA

StratixFPGA

TS101S

TS101S TS101S

TS101S 256MBSDRAM

Flash

J1-J

3

J4

J1-J

3

J4

PMC-site 1

PMC-site 2

Com

pact

PC

I bac

kpla

ne

PowerFFT64MB

SDRAM

64MBSDRAM

64MBSDRAM

64MBSDRAM

PCI64bridge

Test connect.

JTAG

Temp monitor

Hot swap

Under Development


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TS101S

TS101S TS101S

TS101S256MBSDRAM

TS101S

TS101S TS101S

TS101S 256MBSDRAM

Flash

J1-J

3

J4

J1-J

3

J4

PMC-site 1

PMC-site 2

Flash

Com

pact

PC

I bac

kpla

ne

StratixFPGA

StratixFPGA

PCI64bridge

Test connect.

JTAG

Temp monitor

Hot swap

Atlas 6U 8xTS101S CompactPCI

Under Development


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PowerFFT Connectivity FPGA

PowerFFTInput data bus

customer specificinterface

LINK interfacesand

communication FIFOs

PowerFFTOutput data bus

CommunicationBlock

“Switch Fabric”

LINK interfacesand

communication FIFOs

4x

PowerFFTSDRAM

Controller

pre- and postprocessing

2 links to backplane


(option: PCI64 macro)

direct J4 connection

Address bus 3

2 links from TS

direct J1 - J3 connection 64bit data busFPGA to FPGA

64bit data bus

64bit data bus

Address bus 1

Address bus 2

Address bus 4


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Trigger bus

64bit local-PCImemory-mapped I/O


LINK interfacesand

communication FIFOs

Trigger-BusTrigger, Sync, Clock

Temperaturemonitor as inother Atlas

Boards

CommunicationBlock

“Switch Fabric”

LINK interfacesand

communication FIFOs

memory mappedinterface to

TigerSHARCand SDRAM-

Controller

Watchdog,programmable clock generators

pre- and postprocessing

2 links to backplane


(option: PCI64 macro)

direct J4 connection

64bit

Address bus

2 links from TS

direct J1 - J3 connection 64bit data busFPGA to FPGA

TigerSHARC Connectivity FPGA


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• True data flow processors have• A high speed switch-fabric at their heart• Paths within the switch-fabric that can reconfigure extremely quickly (5-10 clock cycles)• An instruction sequencer and distributor that issues the correct instructions to each controller• Two or more controllers attached to switch-fabric

• Controllers are either a “process”, “sink”, “source”, or “both sink and source”• Controllers include I/O, memory addressing (often multiple banks), arithmetic logic units,

duplicators, data compressors, FFTs, data generators, multiplexers, etc, etc• True concurrency: operations (command lines) using different controllers can take place at the

same time (no time-slicing)

• Eonic truly applies its data flow processors in high-end FFT driven stream based DSP architectures

• Case example shown in typical high-end data flow application: SAR data acquisition,

processing and storage• PowerFFT, (TigerSharc) DSP (clusters), FPGA macros, can all considered as data flow

processors in this application

Conclusions

eonic bv laurens bierens, chief technology officer [email protected] digitally mastering the...

Documents

reconfigurable firwmware

sar processing

end processing

data recording

highend dsp

end slide

presentation slide

highend application