eng_ss_oem-hms-sp1-01_0397

PAIRGAIN TECHNOLOGIES, INC.HDSL OEM MODULE (HOM) FAMILY

ETSI OEM MODULESHOM-1168-L1 HOM-ETSI-L1

PRODUCT SPECIFICATIONOEM-HMS-SP1-01

MARCH 12, 1997

March 12, 1997 OEM-HMS-SP1-01

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CONTENTS PAGE

GENERAL DESCRIPTION ........................................................................................................................1

FEATURES..................................................................................................................................................2

FUNCTIONAL DESCRIPTION .................................................................................................................3Overall Operation ...................................................................................................................................3HDSL Range..........................................................................................................................................4Loopbacks ..............................................................................................................................................6

ETSI OEM Module Loopbacks ........................................................................................................6System Loopbacks ...........................................................................................................................7Loopback Access .............................................................................................................................7

Network Management.............................................................................................................................8Provisioning.....................................................................................................................................8Performance Monitoring ..................................................................................................................8Host Management Interface Protocol (HMI) ....................................................................................9Craft Port Interface ..........................................................................................................................9

Power Consumption................................................................................................................................9

ELECTRICAL HOST INTERFACE ......................................................................................................... 10

APPLICATIONS ........................................................................................................................................ 15E1 Applications ..................................................................................................................................... 15FE1 Applications ................................................................................................................................... 16Line Powering ....................................................................................................................................... 16

MECHANICAL DESCRIPTION ............................................................................................................... 17

ORDERING INFORMATION ................................................................................................................... 18

Copyright 1997. PairGain Technologies, Inc. All rights reserved.

This document contains proprietary information which is protected by copyright. No part of this document may be reproduced or transmitted inany form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, ortranslated into another language, without prior written consent of PairGain Technologies, Inc., Tustin, California, USA

PairGain is a registered trademark, and HiGain, SPAROW, and CopperOptics are trademarks of PairGain Technologies, Inc.

PAIRGAIN TECHNOLOGIES, INC.

14402 Franklin Avenue, Tustin, CA 92780-7013 U.S.A.

(714) 832-9922 FAX (714) 832-9924 WEB Site: http://www.pairgain.com

OEM-HMS-SP1-01 March 12, 1997

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GENERAL DESCRIPTION

The PairGain family of ETSI OEM modules provides a fully integrated, High-bit-rate Digital Subscriber Line (HDSL)transmission system designed for easy integration into new or existing products. The ETSI OEM module, Figure 1, utilizesPairGains field-proven, industry-leading CopperOptics technology to transport data over one or two pairs ofunconditioned, non-loaded copper wires at Fractional E1 (FE1) or full E1 data rates. The module provides reliabletransmission without cable pair conditioning, pair separation, or bridge tap removal. In typical cable environments, themodule transmits over a range up to 4.1 Km (13.5 Kft) on 0.51 mm (24 AWG) cable with transmission quality equivalentto a BER of 10-8.

Each module contains all the hardware circuits and software code necessary to perform the complex data formatting, signalprocessing, and communication protocols required in implementing a HDSL modem. A 32-pin connector connects themodule to a host board via mezzanine mounting. In addition to the CMOS logic level interface for data, clock, andsynchronization pulses, optional connections provide status indications capable of driving LEDs. A Host ManagementInterface (HMI) provides the host board a communication path for configuring, monitoring, or testing a HDSL system.

The ETSI OEM module complies with European Telecommunications Standards Institute (ETSI) recommendationETR-152. This recommendation defines the transmission specifications, data formatting requirements, and operations andmaintenance protocols for full or fractional E1 operation on twisted-pair wires. This compliance along with the use ofPairGain-standard software ensures that the ETSI OEM module is fully inter-operable with other products in PairGainsHiGain International Series product line, including line units, remote units, regenerators, and network managementplatforms.

Figure 1. ETSI OEM Module

Table 1. ETSI OEM Module Family

ModelNumber

WirePairs

PayloadRate(Kbps)

HDSLRate(Kbps)

Mount

HOM-1168-L1 1 1024 1168 Mezzanine

HOM-ETSI-L1 2 2048 1168 Mezzanine


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FEATURES

Small size: 2.5" x 3.25" x 0.44"

Low power: FE1 2.4 Watts (typical) E1 3.2 Watts (typical)

Configurable as LTU or NTU

Flash memory program storage

CMOS logic level interface

Industrial temperature range: -40C to +85C

High performance: > 6 dB margin relative to BER of 10-7 (equivalent to BER of 10-10 or better)

Inter-operable with HiGain International Series LTU and NTU

Transports framed or unframed data

Host Management Interface for local and remote unit management

ASCII terminal, menu-driven interface via separate Craft port for management of local and remote units

Status outputs: (capable of driving LED)

HDSL Loop 1 Synchronization

HDSL Loop 2 Synchronization

HDSL alarm

Loopback

Dual Mode Host Management Channel

Local Mode (9600 bps - 8-O-1)

Thru Mode (1200 bps - 8-N-1)

Network management features

User-configurable alarm thresholds

5-minute, 24-hour, and 7-day-performance histories

Loopback support

Local digital, local analog, and remote digital loopbacks

BER pattern generation and checking

Configurable loopback time-out

Extensive self-test diagnostics

32-pin connector to host board


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FUNCTIONAL DESCRIPTION

Overall Operation

Figure 2 shows a top-level functional block diagram of the ETSI OEM module. The module incorporates two full-duplextransmission channels using PairGains field-proven 2B1Q HDSL transceiver design. The module may be configured foroperation as either the LTU or NTU end of a circuit, as defined by ETSI recommendation ETR-152. The module has twomodes of operation: Structured and Unstructured. Structured Mode is used for applications requiring that time slots bemapped to specific HDSL payload bytes. Unstructured Mode is used when the system does not use or cannot determinecompatible time slot or frame boundaries. In either mode, the sampling edge of the input clock and output clock can beindividually set to rising or falling edge.

Figure 2. Functional Block Diagram

In Structured Mode, input data is fed to the module at a 2.048 Mbps rate in a G.704-framed E1 data stream (RSER) with anaccompanying clock signal (RCLK) and sync pulse (RSYNC). The ETSI HDSL framer divides the input data into twoequal data streams, routes the data per a device mapping table, and adds overhead information from the channel fortransmission via the HDSL transceivers. At the far-end of the circuit, the HDSL transceivers recover the HDSL data fromthe loops feeding the data stream to the ETSI HDSL framer. The framer combines the two HDSL streams from the


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transceivers into a single data stream at 2.048 Mbps (TSER) accompanied by a clock signal (TCLK) and sync pulse(TSYNC) for output to the host board.

Structured Mode has two modes of operation: framed or multi-framed. In framed operation, the input sync signal RSYNCis input once every 125 usec and defines bit 0 of each frame. Separate transmit and receive bit-delay parameters specifythe bit delay between the rising edge of RSYNC (or TSYNC on output) and bit 0 of the frame.

In contrast, with multi-framed operation, the input sync signal, RSYNC is input once every 2 msec and defines bit 0 offrame 0 of a CRC-4 multi-frame. As in framed operation, separate transmit and receive bit delay parameters specify thebit delay between the rising edge of RSYNC (or TSYNC on output) and bit 0 of frame 0. The maximum bit delay is 511bits. In either Structured Mode of operation, the module has no effect on the data stream.

In Unstructured Mode, the input data stream enters the module at a 2.048 Mbps rate (RSER) with an accompanying clocksignal (RCLK). The frame synchronizing signal (RSYNC) is not used in this mode. The ETSI HDSL framer divides thedata into two separate data streams alternately distributing modulo 8-bits with channel overhead information fortransmission by each HDSL transceiver. At the far-end of the circuit, the HDSL transceivers recover the HDSL data fromthe loops. The recovered data is passed to the ETSI HDSL Framer where the data is combined into a single data stream at2.048 Mbps. This data stream (TSER) is output with an accompanying clock signal (TCLK) to the host board. The signal(TSYNC) should be ignored in this mode.

Each HDSL Transceiver contains a PairGain SPAROW II Digital Signal Processing (DSP) chip, an integrated AnalogFront End (AFE) chip, and miscellaneous timing generation and control circuits. Line interface transformers and secondaryprotection devices are not included on the module, but a recommended circuit and components are illustrated later in thisdocument.

The ETSI OEM module implements the HDSL framing functions with a flexible framing device whose design is wellsuited for a variety of E1 applications. Time slots to or from the framed E1 data stream are selected for transmissionthrough a configured device mapping table. The module software automatically maps these time slots to slots in the HDSLframe. The HDSL overhead channel is maintained at 16 Kbps on each pair.

The CPU circuit includes a Zilog Z180 microcontroller, 32 Kbytes of RAM, 2 Mbits of flash memory for program storage,and miscellaneous support and I/O functions that are implemented in a single device. The CPU manages the HDSL startuproutine, EOC operation, and communication with the host processor via a set of commands over the asynchronous, serial(HMI) interface. An optional Craft port is available via a separate connector for accessing the ASCII terminal consolemenu and displays.

HDSL Range

Figure 3 and Tables 2, 3, and 4 show HDSL transmission ranges for various cable sizes operating at ETSI transmissionrates over unconditioned, non-loaded copper pairs. Transmission ranges at ETSI rates are limited by cross-talk noise andBER rate performance. Table 2 indicates transmission ranges in low or no noise environments while Table 3 indicatestransmission ranges in a typical environment. A typical environment consists of a cable group with 3 or 4 other HDSLservices operating in the same group. Table 4 indicates transmission ranges in a cable group with all other pairs carryingHDSL service characterizing a worse case environment. In each table, each transmission range is determined at a Bit ErrorRate (BER) performance of 10-8. In a typical environment, the range on 0.51 mm (24 AWG) cable is 4.1 Km or 13.5 Kft.

Each table also indicates the resistance of each cable size at a transmission range of 10-8 BER performance. Thetransmission ranges provided in these tables indicate the type of performance that one may expect in real world operation.However, individual experience may vary depending on specific cable characteristics and environment.


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Figure 3. HDSL Transmission Range.

Table 2. ETSI HDSL Maximum Range Line Specification (PIC Cable 21C (70F))

CableGaugemm (AWG)

Max Rangeat 10-8 BERKm (Kft)

OhmsperKm (Kft)

Ohmsat MaxLength

0.4 (26) 3.4 (11.2) 273.3 (83.3) 929

0.51 (24) 4.4 (14.4) 170.3 (51.9) 749

0.61 (22) 5.7 (18.7) 106.3 (32.4) 606

0.91 (19) 8.1 (26.6) 52.8 (16.1) 428

Table 3. ETSI HDSL Typical Range Line Specification (PIC Cable 21C (70F))

CableGaugemm (AWG)


OhmsperKm (Kft)

Ohmsat MaxLength

0.4 (26) 3.2 (10.5) 273.3 (83.3) 875

0.51 (24) 4.1 (13.5) 170.3 (51.9) 698

0.61 (22) 5.3 (17.4) 106.3 (32.4) 563

0.91 (19) 7.6 (24.9) 52.8 (16.1) 401


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Table 4. ETSI HDSL Minimum Range Line Specification (PIC Cable 21C (70F))

CableGaugemm (AWG)


OhmsperKm (Kft)

Ohmsat MaxLength

0.4 (26) 2.4 (7.9) 273.3 (83.3) 696

0.51 (24) 3.2 (10.5) 170.3 (51.9) 545

0.61 (22) 4.1 (13.5) 106.3 (32.4) 436

0.91 (19) 5.8 (19.0) 52.8 (16.1) 306

Loopbacks

ETSI OEM Module Loopbacks

The module contains three loopbacks, Local Digital Loopback (LDL), Local Analog Loopback (LAL), and Remote DigitalLoopback (RDL). The module activates LAL and RDL from hardware interface signals LLRQ- and RLRQ-, respectively,or activates any of the three loopbacks via HMI software-based commands. When LAL loopback is activated, the inputsignals RSER, RCLK, and RSYNC at the local module are looped back at the analog front end and returned to the hostboard as TSER, TSYNC and TCLK, respectively. Alternately, when RDL loopback is activated, the far-end unit outputsignals TSER, TSYNC, and TCLK, normally transmitted to its host board, are looped back at its digital interface replacinginput signals RSER, RSYNC, and RCLK, respectively, from its host board. Figure 4 illustrates how these loopbacks areused in a system. For instance, when the hardware interface lead LLRQ- is activated, a LAL loopback is activated at therequesting unit; when RLRQ- is activated, a RDL loopback is activated at the far-end module. In both instances, theLOOP- status line at the far-end module is activated, thus indicating to the far-end host that its TSER signal contains testpatterns that may need to be blocked.

Figure 4. OEM Module Loopbacks


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System Loopbacks

Loopbacks are provided in the ETSI OEM module to assist in testing data transport systems in both private networks andpublic (Telco or PTT) networks. Loopbacks are designated according to their direction (towards NETwork or towardsCUStomer) and interface position (LTU-I/F, LTU-HDSL, NTU-HDSL, or NTU-I/F). The combination of direction andposition determines the specific loopback activated. Figure 5 illustrates these loopbacks in an ETSI OEM module and/orHiGain International Series system. The ETSI OEM module uses the same loopback terminology as the HiGainInternational Series Line Terminating Units (LTU) and Network Terminating Unit (NTU) and inter-operates with theseunits. (Note: Neither a NET-NTU-HDSL nor a CUS-LTU-HDSL loopback is available in either system.)

Loopback Access

There are three methods of activating loopbacks, depending on the sophistication of the host board. The ETSI OEMmodule supports manual activation via hardware interface signals (previously described), via Host Management Interfacesoftware commands, or via an optional Craft port used mainly during debugging.

In more sophisticated systems, the host board controls all loopbacks by issuing loopback commands through thebit-mapped Host Management Interface (HMI). These commands select the loopback location and interface position aspreviously described. The HMI commands and responses are described in a separate document.

For debugging environments, loopbacks can also be controlled through the Craft port interface (Figure 7). This interfacepresents a full screen, menu-driven terminal interface for the local operator. The Craft port interface has a separateconnector on the module. All loopbacks, as previously described, are available via this interface.

Figure 5. System Loopbacks.


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Network Management

The ETSI OEM module provides provisioning, performance monitoring, and testing capability via either of two serial,asynchronous interfaces known as the Host Management Interface (HMI) and Craft Port Interface. The HMI interfaceprovides a proprietary bit-mapped protocol for rapid CPU-to-CPU communication between the host board and the module.The Craft port provides an interactive, human-readable, menu-driven interface for easy access to the module forprovisioning, monitoring, or testing.

Provisioning

All system settings are stored in NVRAM at the unit designated master. The master unit downloads these settings to therest of the system during synchronization. The NVRAM is guaranteed to have a capability of 1,000 write cycles. Thecurrent state of loopbacks is not considered a system setting, and an active loopback becomes inactive during systemsynchronization. Provisioning is available at a slave unit only when the loops are synchronized with the master unit. Thefollowing system settings are available:

Errored Second Threshold: 0 to 255 seconds per 24 hours

Loopback Time-out: NONE, 20, 120 minutes

Alarm Notification: ENABLE or DISABLE

Margin Alarm Threshold: 0 to 15 dB, 1 dB increments

Performance Monitoring

From any end unit in a system, HDSL performance data may be accessed for each HDSL span in the circuit, including upto two HDSL doublers (three total HDSL spans). Any unit provides access to the following:

HDSL Span Current Status: Alarms Loopbacks Margins HDSL Pulse Attenuation 24-hour HDSL Errored Seconds 24-hour HDSL Unavailable Seconds

HDSL Span History: 15 min, 24-hour, 7-day HDSL Errored Seconds 15 min, 24-hour, 7-day HDSL Unavailable Seconds

HDSL Alarm History: LOSW, HDSL1 - Loss of Sync on Loop 1 LOSW, HDSL2 - Loss of Sync on Loop 2 ES, HDSL1 - Exceeded ES Threshold on Loop 1 ES, HDSL2 - Exceeded ES Threshold on Loop 2 Margin, HDSL1 - Exceeded Threshold on Loop 1 Margin, HDSL2 - Exceeded Threshold on Loop 2


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Host Management Interface Protocol (HMI)

The HMI protocol provides commands and responses for machine-level management of the ETSI OEM module and remoteunit. The host board sends commands and receives responses via RDATA and TDATA interface leads. The module onlyresponses to commands from the host board and does not generate any unsolicited responses. The ETSI ManagementInterface Specification, document number OEM-HMS-SW1-00, describes the HMI protocol and details the individualcommands and responses for the preceding information.

Craft Port Interface

The Craft port is a serial, asynchronous interface (see Figure 7) separate from the main connector that provides an ASCIImenu format for configuring, monitoring, and testing the module. The interface autobauds from 1200 bps to 19,200 bpswith 8 data bits, odd parity, and 1 stop bit. An ASCII terminal or PC operating in VT-100 mode accesses the modulewithout an HMI interface program during host board development and testing. The interface provides +5V DC to power aRS-232 interface chip. When a terminal is connected to the interface, hitting the space bar several times causes the moduleto autobaud on the space character and output the main menu for display on the terminal. The Management InterfaceSpecification, document number OEM-HMS-SW1-00, includes a discussion of the Craft port menus and parameters.

Power Consumption

Table 5 indicates the typical and maximum power consumption for each module that the +5V power source needs toprovide.

Table 5. Power Consumption

Module Typical Power Maximum Power

HOM-1168 2.4 watts 3.0 watts

HOM-ETSI 3.2 watts 4.0 watts


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ELECTRICAL HOST INTERFACE

The electrical and signal interface with the host board is via a 32-pin connector. Figure 6 shows the pinout for thisconnector and Tables 6 and 7 describe the required interface signals and optional interface signals, respectively.

Figure 6. Module Connector Pinout

Figure 7. 8-Pin Craft Port Connector


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Table 6. Required Interface Signals

Pin Name I/O Type Definition

Power Input

7, 25 +5V I Power +5V 5%.

3, 4 GND I Ground Signal and Power Ground

18 RESET I CMOS Active high resets all registers within the module, and clearsperformance history and loopbacks. Must be held active for a minimumof 50 msec following application of +5V or when activated duringnormal operation. Upon release of reset, the module automaticallysynchronizes with a far-end unit.

22 M/S- I CMOS Master/Slave mode select, read once during system initialization. Ahigh level designates master or LTU. For each HDSL span, one endmust be designated as master, the other end as slave or NTU. Bothmaster and slave units provide Host Management Interface access forprovisioning and monitoring of the system. The master unit controlsHDSL startup and synchronization. Each unit records its configurationin NVRAM.

HDSL interconnect

1 TIP1 I/O Analog HDSL Loop 1 connection to tip of wire pair 1. Output level is 13.50.5dBm into 135 ohms at the wire interconnect point, using the HDSLtransformer and protection resistance specified in the applicationsection of this document.

2 RING1 I/O Analog HDSL Loop 1 connection to ring of wire pair 1.

19 TIP2 I/O Analog HDSL Loop 2 connection to tip of wire pair 2. (Not used on FE1)

20 RING2 I/O Analog HDSL Loop 2 connection to ring of wire pair 2. (Not used on FE1)

Digital Data

14 RSER I CMOS Receive Serial accepts payload data at 2048 Kbps. In normal clockmode, signal must be stable on falling edge of RCLK.

10 RCLK I CMOS Receive Clock for input payload data. Frequency must be 2048 kHz250 Hz Falling edge samples are normal, rising RCLK edge isselectable.

11 TSER O CMOS Transmit Serial outputs payload data 2048 Kbps. In normal clockmode, signal is stable on falling edge of TCLK.

13 TCLK O CMOS Transmit Clock for output payload data. Frequency will be identicalwith RCLK received at the far-end, within 2048 kHz 250 Hz. Signal issquare wave with 40% - 60% duty cycle. Rising edge or falling edgeoutputs are selectable.

5, 6, 8 NC Reserved for factory test. Leave these pins unconnected.


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Table 7. Optional Interface Signals


Data Sync

12 RSYNC I CMOS Receive Sync for input payload data. In Structured Mode, the low to high input transitiondefines the start of bit 0 of frame 0. This pulse occurs every 125 usec in Framed operationand every 2 msec in multi-framed operation. A configurable bit and frame delay enablesthe module to offset RSYNC with the RSER and INSDAT sample location of bit 0, frame0. RSYNC is ignored in Unstructured or asynchronously mapped applications. If notused, connect to ground. RSYNC is required for FE1 operation.

9 TSYNC O CMOS Transmit Sync for output payload data. TSYNC pulses high for one TCLK coincidentwith TSER output of bit 0, frame 0 for Framed or Multi-framed operation. Programmablebit and frame delays allow TSYNC to mark any desired TSER bit. TSYNC is unusedduring unstructured or asynchronously mapped applications.

Digital Data

27 INSERT O CMOS Active high output indicates when specific INSDAT time slots are sampled. INSERT ishigh for 8 bits coincident with each marked time slot. Any combination of time slots canbe marked.

29 DROP O CMOS Active high output indicates when specific time slots are present on TSER. DROP is highfor 8 bits coincident with each marked time slot. Any combination of time slots can bemarked.

31 INSDAT I CMOS Alternate source of input serial data. INSDAT is sampled by RCLK and replaces RSERwhen INSERT is active. INSDAT and RSER use the same frame format. INSDAT can beprogrammed to replace RSER data on a time slot basis.

Management Interface

28 SYNC1- O CMOS Active low when Loop 1 is in sync. Capable of driving an LED directly.

30 SYNC2- O CMOS Active low when Loop 2 is in sync. Capable of driving LED directly. (Note: Not used inFE1 applications)

17 ALARM- O CMOS Active low if any of the following HDSL alarm conditions occur and the condition isconfigured to be a MAJOR alarm. All conditions default to MAJOR alarm. Capable ofdriving LED directly. Alarm thresholds are stored in NVRAM, and may be altered usingserial Host Management Interface. Conditions that activate this alarm are:

HDSL errored seconds above threshold. Default value is 170Errored Seconds per 24 hours.

HDSL Margin below threshold. Default value is 4 dB.

Loss of HDSL sync.

16 RDATA I CMOS Receive data input for Host Management Interface. Asynchronous format, uses 8 databits, odd parity, one stop bit. If not used, connect to +5V.

15 TDATA O CMOS Transmit data output for Host Management Interface. Asynchronous format, uses 8 databits, odd parity, one stop bit.

Table continued on next page


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Table 7. Optional Interface Signals (continued)


21 L/T- I CMOS Local/Thru flag for Host Management Interface. High level selects LOCAL mode. It ispermissible to toggle between these modes during operation.

Local mode or HMI mode: The HMI mode enables a protocol of get and set commandsfrom the host board. Data is sent and received on RDATA and TDATA in asynchronousformat of 8 data bits, odd parity, and one stop bit with the interface speed fixed at 9600 bps.

Thru mode: Enables 1200 bps, clear channel, full duplex communication with a far-endhost board. Data is sent and received in asynchronous format of 8 data bits, no parity, andone stop bit. Data input at RDATA appears at the far-end as TDATA, and data input atfar-end RDATA appears locally as TDATA. If this pin is not used, connect it to +5V.

32 THRU_ACK- O CMOS Thru Mode Acknowledge: Active low signal upon activation of L/T signal at a far-endETSI OEM module. It indicates that the far-end module is switching to Thru Mode eitherin response to a request initiated locally or from a request at the far-end.

23 LLRQ- I CMOS Local Loopback Request: When low, causes an analog loopback at the analog front endsection of the module. This loopback causes data received at RSER to be output at TSER.If this pin is not used, connect it to +5V.

24 RLRQ- I CMOS Remote Loopback Request: When low, requests loopback at far-end unit essentiallycausing TSER, TSYNC, and TCLK to be looped back to RSER, RSYNC, and RCLK,respectively. If this pin is not used, connect it to +5V.

26 LOOP- O CMOS Active low indicates that the far-end unit has requested a loopback; TDATA could containtest pattern data and may need to be blocked.

Table 8. Craft Port Interface Signals


2 RDATA2 I CMOS Received data input for Craft Port Interface. Asynchronous format, uses8 data bits, no parity, and one stop bit.

4 +5V O Power +5V available as an output on interface to power an external RS-232 interface device.

6 GND O Ground Ground available on interface to provide return path for powering external RS-232interface device.

8 TDATA2 O CMOS Transmit data output for Craft Port Interface. Asynchronous format, uses8 data bits, no parity, and one stop bit.

1, 3,5, 7

NC Reserved for future use. Leave these pins unconnected.


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Table 9. Electrical Characteristics

Parameter Minimum Nominal Maximum Units

ABSOLUTE MAXIMUM RATINGSOperation at or beyond these limits may result in permanent damage to the module.

DC Supply, +5V (Vcc) -0.5 6.0 V

DC Supply Ripple 20 mV

Input Voltage, any Pin -0.5 Vcc+0.5 V

Input Current, any pin -10 10 mA

Ambient Operating Temperature -40 85 C

Storage Temperature -55 125 C

DC ELECTRICAL CHARACTERISTICSTamb = -40C to 85C, Vcc =5V 5%

Logic Input Low-Level Voltage 0.8 V

Logic Input High-Level Voltage 2.0 V

Logic Input Leakage Current -75 75 A

Logic Output Low-Level Voltage Iout = 1.6 mA(for SYNC1-, SYNC2-, ALARM-, Iout = 6.0 mA)

0.45 V

Logic Output High-Level Voltage Iout = -60 A(for SYNC1-, SYNC2-, ALARM-, Iout = 4.0 mA)

2.4 V

Power Supply Current, +5V Input HOM-1168HOM-ETSI

480

640

610

800

mA

AC ELECTRICAL CHARACTERISTICSTamb = -40C to 85C

Setup time ,RSER, RSYNC to falling edge of RCLK 35 nsec

Hold time, falling edge of RCLK to RSER, RSYNC 10 nsec

Pulse Width, RCLK, high or low 200 nsec

Pulse Width, RSYNC, high or low 100 nsec

Frequency, RCLK E1, FE1 2.048 MHz

Frequency Offset, RCLK E1, FE1 -250 250 ppm

Delay, Gating edge of TCLK to TSER or TSYNC 25 nsec

Frequency, TCLK (Note 1) E1, FE1 2.048 MHz

Duty Cycle, TCLK 40 60 %

Jitter, TCLK 0.75 unit interval

Wander, TCLK 1.1 unit interval

HDSL Symbol Rate E1, FE1 292 kHz

HDSL Output Level into 135 (Note 2) 13.0 13.5 14.0 dBm

Notes:1. TCLK frequency is locked to far-end received RCLK frequency.2. HDSL output at wire line interface, using 1:2.142 ratio transformer


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APPLICATIONS

E1 Applications

Figure 8 illustrates a typical application circuit for secondary surge protection and loop interface. Components and layoutof the line interface circuitry are critical to meet the safety standards for AC power faults and lightning surges (see Table9). PairGain recommends 50 mil traces for all circuitry between the line and the transformers, with 25 mil line spacing oninner layers, 80 mil spacing on outer layers. The Midcom transformer is custom to PairGain and is available to PairGainLicensees. To shorten time-to-market, a kit of line interface components is available from PairGain containing 5 sets ofthe line interface components listed in Table 10.

Figure 8. Typical Application Circuit

Table 10. Recommended Components

ID (see Figure 8) Manufacturer and Part Number Description

CR4, CR6 SGS-ThompsonGeneral SemiMicro Semi

SM6T15CA*SMBJ15CSMBJ15C

15-volt surge suppresser

CR1, CR2, CR3, CR5 TeccorHarris

P2300SB* (SMT)SGT27B13 (thru hole)

270-volt Surge suppresser

FR1, FR2, FR3, FR4 Raychem TR600-160-RA-B-0.5* Polyswitch, 5.6 Ohm

T1, T2 MidcomPremier Magnetics

671-7920 Rev 04*TSD-912

HDSL Transformer, 1:2.142

* Available in small volume Kits. All components are available commercially.


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FE1 Applications

Fractional E1 operates the same as E1, except that the module requires RSYNC as an input. HDSL Loop 1 is the only loopused to transfer data. Time slots 0 and 16 are always passed on this loop along with any number of consecutive time slotsfrom 1 to 15. Consecutive time slots from 1 to 15 are selected by selecting the starting time slot and the number of timeslots to be transported. In FE1 operation, time slots 17-31 are not transported.

Line Powering

It is important to maintain both AC and DC longitudinal balance when providing line power for a remote HDSL unit.Recommended circuits are shown in Figures 9 and 10 for providing two-pair (E1) and one-pair (FE1) line power.

The recommended HDSL transformer is supplied with a secondary winding split at the center to facilitate line powering.Split the secondary with a 1.0 uf capacitor and apply the line power DC voltage across it.

If a switching power supply is used, care must be taken to filter out the power supply frequency components that interferewith the HDSL pulse fundamental and harmonics. The pulse fundamental is 292 kHz for E1.

Refer to local safety standards for the maximum line voltage and current that the power converter can provide.

Figure 9. Two Pair Line Powering

Figure 10. One Pair Line Powering


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MECHANICAL DESCRIPTION

The mechanical dimensions of the ETSI OEM module are shown in Figure 11. Components are placed on both sides of thePCB. The interface connector is a standard dual-row female header with two rows of 16 sockets each on 0.1 inch centers(SAMTEC CES-116-01-S-D O or SSW-116-02-S-D-RA). The sockets are intended to mate with 0.025 inch square pins(SAMTEC TSW-116-23-S-D or similar).

Figure 11. ETSI OEM Module Mechanical Drawing.


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ORDERING INFORMATION

ModelNumber

PartNumber Description

HOM-1168-L1 150-1460-02 FE1 ETSI OEM module, 1-pair, 1168 Kbps fixed line rate, Mezzanine Mount

HOM-ETSI-L1 150-1460-01 E1 ETSI OEM module, 2-pair, 1168 Kbps fixed line rate, Mezzanine Mount

HOL-Line-L2 130-1040-02 HDSL Line Interface Kit for ETSI OEM module (Parts for 5 x 2-pair modules)


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CONTENTSGENERAL DESCRIPTIONFEATURESFUNCTIONAL DESCRIPTIONOverall OperationHDSL RangeLoopbacksETSI OEM Module LoopbacksSystem LoopbacksLoopback Access

Network ManagementProvisioningPerformance MonitoringHost Management Interface Protocol (HMI)Craft Port Interface

Power Consumption

ELECTRICAL HOST INTERFACEAPPLICATIONSE1 ApplicationsFE1 ApplicationsLine Powering

MECHANICAL DESCRIPTIONORDERING INFORMATION

eng_ss_oem-hms-sp1-01_0397

Documents

oem module loopbacks

port interface

host interface

mechanical description

15e1 applications

15fe1 applications

l1 hometsi

l1product specificationoemhms