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Central processing unit
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An Intel 80486DX2 CPU fromabove.
An Intel 80486DX2 frombelow
From Wikipedia, the free encyclopedia
"CPU" redirects here. For other uses, see CPU (disambiguation).
"Computer processor" redirects here. For other uses, see Processor (computing).
A central processing unit (CPU), also referred to as a central processor unit,[1] is thehardware within a computerthat carries out the instructions of a computer program byperforming the basic arithmetical, logical, and input/output operations of the system. The termhas been in use in the computer industry at least since the early 1960s.[2] The form, design,and implementation of CPUs have changed over the course of their history, but theirfundamental operation remains much the same.
In older computers, CPUs require one or more printed circuit boards. With the invention of themicroprocessor, a CPU could be contained within a single silicon chip. The first computers touse microprocessors were personal computers and small workstations. Since the 1970s themicroprocessor class of CPUs has almost completely overtaken all other CPUimplementations, to the extent that even mainframe computers use one or moremicroprocessors. Modern microprocessors are large scale integrated circuits in packagestypically less than four centimeters square, with hundreds of connecting pins.
A computer can have more than one CPU; this is called multiprocessing. Somemicroprocessors can contain multiple CPUs on a single chip; those microprocessors arecalled multi-core processors.
Two typical components of a CPU are the arithmetic logic unit (ALU), which performsarithmetic and logical operations, and the control unit (CU), which extracts instructions frommemory and decodes and executes them, calling on the ALU when necessary.
Not all computational systems rely on a central processing unit. An array processor or vectorprocessorhas multiple parallel computing elements, with no one unit considered the "center".In the distributed computing model, problems are solved by a distributed interconnected set ofprocessors.
Contents [hide]
1 History1.1 Transistor and integrated circuit CPUs
1.2 Microprocessors
2 Operation
3 Design and implementation3.1 Control unit
3.2 Integer range
3.3 Clock rate
3.4 Parallelism3.4.1 Instruction level parallelism
3.4.2 Thread-level parallelism
3.4.3 Data parallelism
4 Performance
5 See also
6 References7 External links
History
Main article: History of general purpose CPUs
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EDVAC, one of the first stored programcomputers.
CPU, core memory, and external businterface of a DECPDP-8/I. Made of medium-scale integrated circuits.
,caused these machines to be called "fixed-program computers." Since the term "CPU" isgenerally defined as a device forsoftware (computer program) execution, the earliest devicesthat could rightly be called CPUs came with the advent of the stored-program computer.
The idea of a stored-program computer was already present in the design ofJ. Presper Eckertand John William Mauchly's ENIAC, but was initially omitted so that it could be finishedsooner. On June 30, 1945, before ENIAC was made, mathematician John von Neumanndistributed the paper entitled First Draft of a Report on the EDVAC. It was the outline of astored-program computer that would eventually be completed in August 1949. [3] EDVAC wasdesigned to perform a certain number of instructions (or operations) of various types. Theseinstructions could be combined to create useful programs for the EDVAC to run. Significantly,
the programs written for EDVAC were stored in high-speed computer memory rather thanspecified by the physical wiring of the computer. This overcame a severe limitation of ENIAC,which was the considerable time and effort required to reconfigure the computer to perform anew task. With von Neumann's design, the program, or software, that EDVAC ran could bechanged simply by changing the contents of the memory.
Early CPUs were custom-designed as a part of a larger, sometimes one-of-a-kind, computer.However, this method of designing custom CPUs for a particular application has largely givenway to the development of mass-produced processors that are made for many purposes. This standardization began in the era of discretetransistormainframes and minicomputers and has rapidly accelerated with the popularization of the integrated circuit (IC). The IC hasallowed increasingly complex CPUs to be designed and manufactured to tolerances on the order ofnanometers. Both the miniaturizationand standardization of CPUs have increased the presence of digital devices in modern life far beyond the limited application of dedicatedcomputing machines. Modern microprocessors appear in everything from automobiles to cell phones and children's toys.
While von Neumann is most often credited with the design of the stored-program computer because of his design ofEDVAC, othersbefore him, such as Konrad Zuse, had suggested and implemented similar ideas. The so-called Harvard architecture of the Harvard MarkI, which was completed before EDVAC, also utilized a stored-program design using punched paper tape rather than electronic memory.The key difference between the von Neumann and Harvard architectures is that the latter separates the storage and treatment of CPUinstructions and data, while the former uses the same memory space for both. Most modern CPUs are primarily von Neumann in design,but elements of the Harvard architecture are commonly seen as well.[citation needed]
Relays and vacuum tubes (thermionic valves) were commonly used as switching elements; a useful computer requires thousands or tensof thousands of switching devices. The overall speed of a system is dependent on the speed of the switches. Tube computers likeEDVAC tended to average eight hours between failures, whereas relay computers like the (slower, but earlier) Harvard Mark I failed veryrarely.[2] In the end, tube based CPUs became dominant because the significant speed advantages afforded generally outweighed thereliability problems. Most of these early synchronous CPUs ran at low clock rates compared to modern microelectronic designs (seebelow for a discussion of clock rate). Clock signal frequencies ranging from 100 kHz to 4 MHz were very common at this time, limitedlargely by the speed of the switching devices they were built with.
Transistor and integrated circuit CPUsThe design complexity of CPUs increased as various technologies facilitated building smallerand more reliable electronic devices. The first such improvement came with the advent of thetransistor. Transistorized CPUs during the 1950s and 1960s no longer had to be built out ofbulky, unreliable, and fragile switching elements like vacuum tubes and electrical relays. Withthis improvement more complex and reliable CPUs were built onto one or several printedcircuit boards containing discrete (individual) components.
During this period, a method of manufacturing many interconnected transistors in a compactspace was developed. The integrated circuit (IC) allowed a large number of transistors to bemanufactured on a single semiconductor-based die, or "chip." At first only very basic non-specialized digital circuits such as NOR gates were miniaturized into ICs. CPUs based uponthese "building block" ICs are generally referred to as "small-scale integration" (SSI) devices.SSI ICs, such as the ones used in theApollo guidance computer, usually contained up to a
few score transistors. To build an entire CPU out of SSI ICs required thousands of individualchips, but still consumed much less space and power than earlier discrete transistor designs. As microelectronic technology advanced,an increasing number of transistors were placed on ICs, thus decreasing the quantity of individual ICs needed for a complete CPU. MSIand LSI (medium- and large-scale integration) ICs increased transistor counts to hundreds, and then thousands.
In 1964 IBM introduced its System/360 computer architecture which was used in a series of computers that could run the sameprograms with different speed and performance. This was significant at a time when most electronic computers were incompatible withone another, even those made by the same manufacturer. To facilitate this improvement, IBM utilized the concept of a microprogram(often called "microcode"), which still sees widespread usage in modern CPUs. [4] The System/360 architecture was so popular that itdominated the mainframe computermarket for decades and left a legacy that is still continued by similar modern computers like the IBMzSeries. In the same year (1964), Digital Equipment Corporation (DEC) introduced another influential computer aimed at the scientific andresearch markets, the PDP-8. DEC would later introduce the extremely popularPDP-11 line that originally was built with SSI ICs but waseventually implemented with LSI components once these became practical. In stark contrast with its SSI and MSI predecessors, the firstLSI implementation of the PDP-11 contained a CPU composed of only four LSI integrated circuits.[5]
Transistor-based computers had several distinct advantages over their predecessors. Aside from facilitating increased reliability and lowerpower consumption, transistors also allowed CPUs to operate at much higher speeds because of the short switching time of a transistorin comparison to a tube or relay. Thanks to both the increased reliability as well as the dramatically increased speed of the switchingelements (which were almost exclusively transistors by this time), CPU clock rates in the tens of megahertz were obtained during thisperiod. Additionally while discrete transistor and IC CPUs were in heavy usage, new high-performance designs like SIMD (SingleInstruction Multiple Data) vector processors began to appear. These early experimental designs later gave rise to the era of specializedsupercomputers like those made b Cra Inc.
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wiki/Piranti_Pamros%C3%A9san_Sentralhttp://he.wikipedia.org/wiki/%D7%9E%D7%A2%D7%91%D7%93http://it.wikipedia.org/wiki/CPUhttp://is.wikipedia.org/wiki/Mi%C3%B0verkhttp://en.wikipedia.org/wiki/Cray_Inc.http://en.wikipedia.org/wiki/Supercomputerhttp://en.wikipedia.org/wiki/Vector_processorhttp://en.wikipedia.org/wiki/SIMDhttp://en.wikipedia.org/wiki/PDP-11http://en.wikipedia.org/wiki/PDP-8http://en.wikipedia.org/wiki/Digital_Equipment_Corporationhttp://en.wikipedia.org/wiki/ZSerieshttp://en.wikipedia.org/wiki/Mainframe_computerhttp://en.wikipedia.org/wiki/Microprogramhttp://en.wikipedia.org/wiki/System/360http://en.wikipedia.org/wiki/IBMhttp://en.wikipedia.org/wiki/Apollo_guidance_computerhttp://en.wikipedia.org/wiki/NOR_gatehttp://en.wikipedia.org/wiki/Die_(integrated_circuit)http://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Printed_circuit_boardhttp://en.wikipedia.org/wiki/Relayhttp://en.wikipedia.org/wiki/Vacuum_tubehttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/PDP-8http://en.wikipedia.org/wiki/External_bushttp://en.wikipedia.org/wiki/Magnetic_core_memoryhttp://en.wikipedia.org/wiki/File:PDP-8i_cpu.jpghttp://en.wikipedia.org/wiki/File:PDP-8i_cpu.jpghttp://en.wikipedia.org/w/index.php?title=Central_processing_unit&action=edit§ion=2http://en.wikipedia.org/wiki/Hertzhttp://en.wikipedia.org/wiki/Clock_ratehttp://en.wikipedia.org/wiki/Harvard_Mark_Ihttp://en.wikipedia.org/wiki/EDVAChttp://en.wikipedia.org/wiki/Vacuum_tubehttp://en.wikipedia.org/wiki/Relayhttp://en.wikipedia.org/wiki/Wikipedia:Citation_neededhttp://en.wikipedia.org/wiki/Punched_tapehttp://en.wikipedia.org/wiki/Harvard_Mark_Ihttp://en.wikipedia.org/wiki/Harvard_architecturehttp://en.wikipedia.org/wiki/Konrad_Zusehttp://en.wikipedia.org/wiki/EDVAChttp://en.wikipedia.org/wiki/Cell_phonehttp://en.wikipedia.org/wiki/Automobilehttp://en.wikipedia.org/wiki/Nanometerhttp://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Minicomputerhttp://en.wikipedia.org/wiki/Mainframe_computerhttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/EDVAChttp://en.wikipedia.org/wiki/Memory_(computers)http://en.wikipedia.org/wiki/EDVAChttp://en.wikipedia.org/wiki/John_von_Neumannhttp://en.wikipedia.org/wiki/ENIAChttp://en.wikipedia.org/wiki/John_William_Mauchlyhttp://en.wikipedia.org/wiki/J._Presper_Eckerthttp://en.wikipedia.org/wiki/Stored-program_computerhttp://en.wikipedia.org/wiki/Softwarehttp://en.wikipedia.org/wiki/EDVAChttp://en.wikipedia.org/wiki/File:Edvac.jpghttp://en.wikipedia.org/wiki/File:Edvac.jpg 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Dieof an Intel 80486DX2 microprocessor(actual size: 126.75 mm) in its packaging
Intel Core i5 CPU on a Vaio Eseries laptopmotherboard (on the right, beneath the heatpipe).
Microprocessors
Main article: Microprocessor
In the 1970s the fundamental inventions by Federico Faggin (Silicon Gate MOS ICs with selfaligned gates along with his new random logic design methodology) changed the design andimplementation of CPUs forever. Since the introduction of the first commercially availablemicroprocessor (the Intel 4004) in 1970, and the first widely used microprocessor(the Intel8080) in 1974, this class of CPUs has almost completely overtaken all other centralprocessing unit implementation methods. Mainframe and minicomputer manufacturers of thetime launched proprietary IC development programs to upgrade their oldercomputer
architectures, and eventually produced instruction set compatible microprocessors that werebackward-compatible with their older hardware and software. Combined with the advent andeventual success of the ubiquitous personal computer, the term CPUis now applied almostexclusively[according to whom?] to microprocessors. Several CPUs can be combined in a singleprocessing chip.
Previous generations of CPUs were implemented as discrete components and numeroussmall integrated circuits (ICs) on one or more circuit boards. Microprocessors, on the otherhand, are CPUs manufactured on a very small number of ICs; usually just one. The overallsmaller CPU size as a result of being implemented on a single die means faster switchingtime because of physical factors like decreased gate parasitic capacitance. This has allowedsynchronous microprocessors to have clock rates ranging from tens of megahertz to severalgigahertz. Additionally, as the ability to construct exceedingly small transistors on an IC hasincreased, the complexity and number of transistors in a single CPU has increased many
fold. This widely observed trend is described by Moore's law, which has proven to be a fairlyaccurate predictor of the growth of CPU (and other IC) complexity.[6]
While the complexity, size, construction, and general form of CPUs have changed enormouslysince 1950, it is notable that the basic design and function has not changed much at all.Almost all common CPUs today can be very accurately[according to whom?] described as von Neumann stored-program machines. As theaforementioned Moore's law continues to hold true[according to whom?], concerns have arisen about the limits of integrated circuit transistortechnology. Extreme miniaturization of electronic gates is causing the effects of phenomena like electromigration and subthresholdleakage to become much more significant. These newer concerns are among the many factors causing researchers to investigate newmethods of computing such as the quantum computer, as well as to expand the usage ofparallelismand other methods that extend theusefulness of the classical von Neumann model.
Operation
The fundamental operation of most CPUs, regardless of the physical form they take, is to execute a sequence of stored instructions
called a program. The program is represented by a series of numbers that are kept in some kind ofcomputer memory. There are foursteps that nearly all CPUs use in their operation: fetch, decode, execute, and writeback.
The first step, fetch, involves retrieving an instruction (which is represented by a number or sequence of numbers) from program memory.The location in program memory is determined by a program counter(PC), which stores a number that identifies the current position inthe program. After an instruction is fetched, the PC is incremented by the length of the instruction word in terms of memory units.[7]
Often, the instruction to be fetched must be retrieved from relatively slow memory, causing the CPU to stall while waiting for theinstruction to be returned. This issue is largely addressed in modern processors by caches and pipeline architectures (see below).
The instruction that the CPU fetches from memory is used to determine what the CPU is to do. In the decode step, the instruction isbroken up into parts that have significance to other portions of the CPU. The way in which the numerical instruction value is interpreted isdefined by the CPU's instruction set architecture (ISA).[8] Often, one group of numbers in the instruction, called the opcode, indicateswhich operation to perform. The remaining parts of the number usually provide information required for that instruction, such as operandsfor an addition operation. Such operands may be given as a constant value (called an immediate value), or as a place to locate a value: aregisteror a memory address, as determined by some addressing mode. In older designs the portions of the CPU responsible for
instruction decoding were unchangeable hardware devices. However, in more abstract and complicated CPUs and ISAs, a microprogramis often used to assist in translating instructions into various configuration signals for the CPU. This microprogram is sometimesrewritable so that it can be modified to change the way the CPU decodes instructions even after it has been manufactured.
After the fetch and decode steps, the execute step is performed. During this step, various portions of the CPU are connected so they canperform the desired operation. If, for instance, an addition operation was requested, the arithmetic logic unit (ALU) will be connected to aset of inputs and a set of outputs. The inputs provide the numbers to be added, and the outputs will contain the final sum. The ALUcontains the circuitry to perform simple arithmetic and logical operations on the inputs (like addition and bitwise operations). If theaddition operation produces a result too large for the CPU to handle, an arithmetic overflow flag in a flags register may also be set.
The final step, writeback, simply "writes back" the results of the execute step to some form of memory. Very often the results are writtento some internal CPU register for quick access by subsequent instructions. In other cases results may be written to slower, but cheaperand larger, main memory. Some types of instructions manipulate the program counter rather than directly produce result data. These aregenerally called "jumps" and facilitate behavior like loops, conditional program execution (through the use of a conditional jump), andfunctions in programs.[9] Many instructions will also change the state of digits in a "flags" register. These flags can be used to influence
how a program behaves, since they often indicate the outcome of various operations. For example, one type of "compare" instructionconsiders two values and sets a number in the flags register according to which one is greater. This flag could then be used by a laterjump instruction to determine program flow.
After the execution of the instruction and writeback of the resulting data, the entire process repeats, with the next instruction cyclenormally fetching the next-in-sequence instruction because of the incremented value in the program counter. If the completed instructionwas a jump, the program counter will be modified to contain the address of the instruction that was jumped to, and program execution
http://en.wikipedia.org/wiki/Instruction_cyclehttp://en.wikipedia.org/wiki/Subroutinehttp://en.wikipedia.org/wiki/Control_flow#Loopshttp://en.wikipedia.org/wiki/Random_access_memoryhttp://en.wikipedia.org/wiki/Bitwise_operationshttp://en.wikipedia.org/wiki/Arithmetic_logic_unithttp://en.wikipedia.org/wiki/Microprogramhttp://en.wikipedia.org/wiki/Addressing_modehttp://en.wikipedia.org/wiki/Processor_registerhttp://en.wikipedia.org/wiki/Program_counterhttp://en.wikipedia.org/wiki/Instruction_(computer_science)http://en.wikipedia.org/wiki/Memory_(computers)http://en.wikipedia.org/w/index.php?title=Central_processing_unit&action=edit§ion=4http://en.wikipedia.org/wiki/Parallel_computinghttp://en.wikipedia.org/wiki/Quantum_computerhttp://en.wikipedia.org/wiki/Subthreshold_leakagehttp://en.wikipedia.org/wiki/Electromigrationhttp://en.wikipedia.org/wiki/Wikipedia:Avoid_weasel_wordshttp://en.wikipedia.org/wiki/Wikipedia:Avoid_weasel_wordshttp://en.wikipedia.org/wiki/Moore%27s_lawhttp://en.wikipedia.org/wiki/Parasitic_capacitancehttp://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Wikipedia:Avoid_weasel_wordshttp://en.wikipedia.org/wiki/Personal_computerhttp://en.wikipedia.org/wiki/Instruction_sethttp://en.wikipedia.org/wiki/Computer_architecturehttp://en.wikipedia.org/wiki/Intel_8080http://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Intel_4004http://en.wikipedia.org/wiki/Federico_Fagginhttp://en.wikipedia.org/wiki/Heat_pipehttp://en.wikipedia.org/wiki/Intelhttp://en.wikipedia.org/wiki/File:EBIntel_Corei5.JPGhttp://en.wikipedia.org/wiki/Intel_80486DX2http://en.wikipedia.org/wiki/Die_(integrated_circuit)http://en.wikipedia.org/wiki/File:80486dx2-large.jpghttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/w/index.php?title=Central_processing_unit&action=edit§ion=3 -
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MOS 6502 microprocessor in a dual in-line package, an extremely popular 8-bitdesign.
continues normally. In more complex CPUs than the one described here, multiple instructions can be fetched, decoded, and executedsimultaneously. This section describes what is generally referred to as the "classic RISC pipeline", which in fact is quite common amongthe simple CPUs used in many electronic devices (often called microcontroller). It largely ignores the important role ofCPU cache, andtherefore the access stage of the pipeline.
Design and implementation
Main article: CPU design
The basic concept of a CPU is as follows:
Hardwired into a CPU's design is a list of basic operations it can perform, called an instruction set. Such operations may include adding
or subtracting two numbers, comparing numbers, or jumping to a different part of a program. Each of these basic operations isrepresented by a particular sequence ofbits; this sequence is called the opcode for that particular operation. Sending a particular opcodeto a CPU will cause it to perform the operation represented by that opcode. To execute an instruction in a computer program, the CPUuses the opcode for that instruction as well as its arguments (for instance the two numbers to be added, in the case of an additionoperation). A computer program is therefore a sequence of instructions, with each instruction including an opcode and that operation'sarguments.
The actual mathematical operation for each instruction is performed by a subunit of the CPU known as the arithmetic logic unit or ALU. Inaddition to using its ALU to perform operations, a CPU is also responsible for reading the next instruction from memory, reading dataspecified in arguments from memory, and writing results to memory.
In many CPU designs, an instruction set will clearly differentiate between operations that load data from memory, and those that performmath. In this case the data loaded from memory is stored in registers, and a mathematical operation takes no arguments but simplyperforms the math on the data in the registers and writes it to a new register, whose value a separate operation may then write tomemory.
Control unit
Main article: Control unit
The control unit of the CPU contains circuitry that uses electrical signals to direct the entire computer system to carry out storedprogram instructions. The control unit does not execute program instructions; rather, it directs other parts of the system to do so. Thecontrol unit must communicate with both the arithmetic/logic unit and memory.
Integer range
The way a CPU represents numbers is a design choice that affects the most basic ways in which the device functions. Some early digitalcomputers used an electrical model of the common decimal (base ten) numeral system to represent numbers internally. A few othercomputers have used more exotic numeral systems like ternary (base three). Nearly all modern CPUs represent numbers in binary form,with each digit being represented by some two-valued physical quantity such as a "high" or "low" voltage.[10]
Related to number representation is the size and precision of numbers that a CPU can
represent. In the case of a binary CPU, a bitrefers to one significant place in the numbers aCPU deals with. The number of bits (or numeral places) a CPU uses to represent numbers isoften called "word size", "bit width", "data path width", or "integer precision" when dealing withstrictly integer numbers (as opposed to floating point). This number differs betweenarchitectures, and often within different parts of the very same CPU. For example, an 8-bitCPU deals with a range of numbers that can be represented by eight binary digits (each digithaving two possible values), that is, 28 or 256 discrete numbers. In effect, integer size sets ahardware limit on the range of integers the software run by the CPU can utilize. [11]
Integer range can also affect the number of locations in memory the CPU can address (locate). For example, if a binary CPU uses 32bits to represent a memory address, and each memory address represents one octet (8 bits), the maximum quantity of memory thatCPU can address is 232 octets, or 4 GiB. This is a very simple view of CPU address space, and many designs use more complexaddressing methods like paging to locate more memory than their integer range would allow with a flat address space.
Higher levels of integer range require more structures to deal with the additional digits, and therefore more complexity, size, power usage,
and general expense. It is not at all uncommon, therefore, to see 4- or 8-bit microcontrollers used in modern applications, even thoughCPUs with much higher range (such as 16, 32, 64, even 128-bit) are available. The simpler microcontrollers are usually cheaper, use lesspower, and therefore generate less heat, all of which can be major design considerations for electronic devices. However, in higher-endapplications, the benefits afforded by the extra range (most often the additional address space) are more significant and often affectdesign choices. To gain some of the advantages afforded by both lower and higher bit lengths, many CPUs are designed with different bitwidths for different portions of the device. For example, the IBM System/370 used a CPU that was primarily 32 bit, but it used 128-bitprecision inside its floating point units to facilitate greater accuracy and range in floating point numbers.[4] Many later CPU designs usesimilar mixed bit width, especially when the processor is meant for general-purpose usage where a reasonable balance of integer andfloating point capability is required.
Clock rate
Main article: Clock rate
The clock rate is the speed at which a microprocessor executes instructions. Every computer contains an internal clock that regulates
the rate at which instructions are executed and synchronizes all the various computer components. The CPU requires a fixed number ofclock ticks (or clock cycles) to execute each instruction. The faster the clock, the more instructions the CPU can execute per second.
Most CPUs, and indeed most sequential logic devices, are synchronous in nature.[12] That is, they are designed and operate onassumptions about a synchronization signal. This signal, known as a clock signal, usually takes the form of a periodic square wave. Bycalculating the maximum time that electrical signals can move in various branches of a CPU's many circuits, the designers can select anappropriate period for the clock signal.
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Model of a subscalar CPU. Notice that ittakes fifteen cycles to complete threeinstructions.
Basic five-stage pipeline. In the best casescenario, this pipeline can sustain acompletion rate of one instruction per cycle.
This period must be longer than the amount of time it takes for a signal to move, or propagate, in the worst-case scenario. In setting theclock period to a value well above the worst-case propagation delay, it is possible to design the entire CPU and the way it moves dataaround the "edges" of the rising and falling clock signal. This has the advantage of simplifying the CPU significantly, both from a designperspective and a component-count perspective. However, it also carries the disadvantage that the entire CPU must wait on its slowestelements, even though some portions of it are much faster. This limitation has largely been compensated for by various methods ofincreasing CPU parallelism. (see below)
However, architectural improvements alone do not solve all of the drawbacks of globally synchronous CPUs. For example, a clock signalis subject to the delays of any other electrical signal. Higher clock rates in increasingly complex CPUs make it more difficult to keep theclock signal in phase (synchronized) throughout the entire unit. This has led many modern CPUs to require multiple identical clocksignals to be provided to avoid delaying a single signal significantly enough to cause the CPU to malfunction. Another major issue as
clock rates increase dramatically is the amount of heat that is dissipated by the CPU. The constantly changing clock causes manycomponents to switch regardless of whether they are being used at that time. In general, a component that is switching uses moreenergy than an element in a static state. Therefore, as clock rate increases, so does energy consumption, causing the CPU to requiremore heat dissipation in the form ofCPU cooling solutions.
One method of dealing with the switching of unneeded components is called clock gating, which involves turning off the clock signal tounneeded components (effectively disabling them). However, this is often regarded as difficult to implement and therefore does not seecommon usage outside of very low-power designs. One notable late CPU design that uses clock gating to reduce the power requirementsof the videogame console is that of the IBM PowerPC-based Xbox 360. It utilizes extensive clock gating in which it is used.[13] Anothermethod of addressing some of the problems with a global clock signal is the removal of the clock signal altogether. While removing theglobal clock signal makes the design process considerably more complex in many ways, asynchronous (or clockless) designs carrymarked advantages in power consumption and heat dissipation in comparison with similar synchronous designs. While somewhatuncommon, entire asynchronous CPUs have been built without utilizing a global clock signal. Two notable examples of this are theARMcompliantAMULET and the MIPS R3000 compatible MiniMIPS. Rather than totally removing the clock signal, some CPU designs allowcertain portions of the device to be asynchronous, such as using asynchronousALUs in conjunction with superscalar pipelining toachieve some arithmetic performance gains. While it is not altogether clear whether totally asynchronous designs can perform at acomparable or better level than their synchronous counterparts, it is evident that they do at least excel in simpler math operations. This,combined with their excellent power consumption and heat dissipation properties, makes them very suitable for embedded computers.[14]
Parallelism
Main article: Parallel computing
The description of the basic operation of a CPU offered in the previous section describes thesimplest form that a CPU can take. This type of CPU, usually referred to as subscalar,operates on and executes one instruction on one or two pieces of data at a time.
This process gives rise to an inherent inefficiency in subscalar CPUs. Since only oneinstruction is executed at a time, the entire CPU must wait for that instruction to completebefore proceeding to the next instruction. As a result, the subscalar CPU gets "hung up" on
instructions which take more than one clock cycle to complete execution. Even adding asecond execution unit (see below) does not improve performance much; rather than one pathway being hung up, now two pathways arehung up and the number of unused transistors is increased. This design, wherein the CPU's execution resources can operate on only oneinstruction at a time, can only possibly reach scalarperformance (one instruction per clock). However, the performance is nearly alwayssubscalar (less than one instruction per cycle).
Attempts to achieve scalar and better performance have resulted in a variety of design methodologies that cause the CPU to behave lesslinearly and more in parallel. When referring to parallelism in CPUs, two terms are generally used to classify these design techniques.Instruction level parallelism (ILP) seeks to increase the rate at which instructions are executed within a CPU (that is, to increase theutilization of on-die execution resources), and thread level parallelism (TLP) purposes to increase the number ofthreads (effectivelyindividual programs) that a CPU can execute simultaneously. Each methodology differs both in the ways in which they are implemented,as well as the relative effectiveness they afford in increasing the CPU's performance for an application. [15]
Instruction level parallelism
Main articles: Instruction pipeliningandSuperscalar
One of the simplest methods used to accomplish increased parallelism is to begin the firststeps of instruction fetching and decoding before the prior instruction finishes executing. Thisis the simplest form of a technique known as instruction pipelining, and is utilized in almost allmodern general-purpose CPUs. Pipelining allows more than one instruction to be executed atany given time by breaking down the execution pathway into discrete stages. This separationcan be compared to an assembly line, in which an instruction is made more complete at eachstage until it exits the execution pipeline and is retired.
Pipelining does, however, introduce the possibility for a situation where the result of theprevious operation is needed to complete the next operation; a condition often termed data dependency conflict. To cope with this,additional care must be taken to check for these sorts of conditions and delay a portion of the instruction pipeline if this occurs. Naturally,accomplishing this requires additional circuitry, so pipelined processors are more complex than subscalar ones (though not verysignificantly so). A pipelined processor can become very nearly scalar, inhibited only by pipeline stalls (an instruction spending more thanone clock cycle in a stage).
Further improvement upon the idea of instruction pipelining led to the development of a methodthat decreases the idle time of CPU components even further. Designs that are said to besuperscalarinclude a long instruction pipeline and multiple identical execution units. [16] In asuperscalar pipeline, multiple instructions are read and passed to a dispatcher, which decideswhether or not the instructions can be executed in parallel (simultaneously). If so they aredispatched to available execution units, resulting in the ability for several instructions to be
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Simple superscalar pipeline. By fetchingand dispatching two instructions at a time, amaximumof two instructions per cycle canbe completed.
executed simultaneously. In general, the more instructions a superscalar CPU is able todispatch simultaneously to waiting execution units, the more instructions will be completed ina given cycle.
Most of the difficulty in the design of a superscalar CPU architecture lies in creating aneffective dispatcher. The dispatcher needs to be able to quickly and correctly determinewhether instructions can be executed in parallel, as well as dispatch them in such a way as tokeep as many execution units busy as possible. This requires that the instruction pipeline is filled as often as possible and gives rise tothe need in superscalar architectures for significant amounts ofCPU cache. It also makes hazard-avoiding techniques like branchprediction, speculative execution, and out-of-order execution crucial to maintaining high levels of performance. By attempting to predictwhich branch (or path) a conditional instruction will take, the CPU can minimize the number of times that the entire pipeline must wait
until a conditional instruction is completed. Speculative execution often provides modest performance increases by executing portions ofcode that may not be needed after a conditional operation completes. Out-of-order execution somewhat rearranges the order in whichinstructions are executed to reduce delays due to data dependencies. Also in case of Single Instructions Multiple Data a case when alot of data from the same type has to be processed, modern processors can disable parts of the pipeline so that when a singleinstruction is executed many times, the CPU skips the fetch and decode phases and thus greatly increases performance on certainoccasions, especially in highly monotonous program engines such as video creation software and photo processing.
In the case where a portion of the CPU is superscalar and part is not, the part which is not suffers a performance penalty due toscheduling stalls. The Intel P5Pentium had two superscalar ALUs which could accept one instruction per clock each, but its FPU couldnot accept one instruction per clock. Thus the P5 was integer superscalar but not floating point superscalar. Intel's successor to the P5architecture, P6, added superscalar capabilities to its floating point features, and therefore afforded a significant increase in floating pointinstruction performance.
Both simple pipelining and superscalar design increase a CPU's ILP by allowing a single processor to complete execution of instructionsat rates surpassing one instruction per cycle (IPC).[17] Most modern CPU designs are at least somewhat superscalar, and nearly all
general purpose CPUs designed in the last decade are superscalar. In later years some of the emphasis in designing high-ILP computershas been moved out of the CPU's hardware and into its software interface, orISA. The strategy of the very long instruction word (VLIW)causes some ILP to become implied directly by the software, reducing the amount of work the CPU must perform to boost ILP andthereby reducing the design's complexity.
Thread-level parallelism
Another strategy of achieving performance is to execute multiple programs orthreads in parallel. This area of research is known asparallel computing. In Flynn's taxonomy, this strategy is known as Multiple Instructions-Multiple Data or MIMD.
One technology used for this purpose was multiprocessing(MP). The initial flavor of this technology is known as symmetricmultiprocessing (SMP), where a small number of CPUs share a coherent view of their memory system. In this scheme, each CPU hasadditional hardware to maintain a constantly up-to-date view of memory. By avoiding stale views of memory, the CPUs can cooperate onthe same program and programs can migrate from one CPU to another. To increase the number of cooperating CPUs beyond a handful,schemes such as non-uniform memory access (NUMA) and directory-based coherence protocols were introduced in the 1990s. SMP
systems are limited to a small number of CPUs while NUMA systems have been built with thousands of processors. Initially,multiprocessing was built using multiple discrete CPUs and boards to implement the interconnect between the processors. When theprocessors and their interconnect are all implemented on a single silicon chip, the technology is known as a multi-core processor.
It was later recognized that finer-grain parallelism existed with a single program. A single program might have several threads (orfunctions) that could be executed separately or in parallel. Some of the earliest examples of this technology implemented input/outputprocessing such as direct memory access as a separate thread from the computation thread. A more general approach to thistechnology was introduced in the 1970s when systems were designed to run multiple computation threads in parallel. This technology isknown as multi-threading (MT). This approach is considered more cost-effective than multiprocessing, as only a small number ofcomponents within a CPU is replicated to support MT as opposed to the entire CPU in the case of MP. In MT, the execution units and thememory system including the caches are shared among multiple threads. The downside of MT is that the hardware support formultithreading is more visible to software than that of MP and thus supervisor software like operating systems have to undergo largerchanges to support MT. One type of MT that was implemented is known as block multithreading, where one thread is executed until it isstalled waiting for data to return from external memory. In this scheme, the CPU would then quickly switch to another thread which isready to run, the switch often done in one CPU clock cycle, such as the UltraSPARC Technology. Another type of MT is known as
simultaneous multithreading, where instructions of multiple threads are executed in parallel within one CPU clock cycle.
For several decades from the 1970s to early 2000s, the focus in designing high performance general purpose CPUs was largely onachieving high ILP through technologies such as pipelining, caches, superscalar execution, out-of-order execution, etc. This trendculminated in large, power-hungry CPUs such as the Intel Pentium 4. By the early 2000s, CPU designers were thwarted from achievinghigher performance from ILP techniques due to the growing disparity between CPU operating frequencies and main memory operatingfrequencies as well as escalating CPU power dissipation owing to more esoteric ILP techniques.
CPU designers then borrowed ideas from commercial computing markets such as transaction processing, where the aggregateperformance of multiple programs, also known as throughput computing, was more important than the performance of a single thread orprogram.
This reversal of emphasis is evidenced by the proliferation of dual and multiple core CMP (chip-level multiprocessing) designs andnotably, Intel's newer designs resembling its less superscalarP6 architecture. Late designs in several processor families exhibit CMP,including the x86-64Opteron andAthlon 64 X2, the SPARCUltraSPARC T1, IBM POWER4 and POWER5, as well as several video
game console CPUs like the Xbox 360's triple-core PowerPC design, and the PS3's 7-core Cell microprocessor.Data parallelism
Main articles: Vector processorandSIMD
A less common but increasingly important paradigm of CPUs (and indeed, computing in general) deals with data parallelism. Theprocessors discussed earlier are all referred to as some type of scalar device. [18] As the name implies, vector processors deal withmultiple pieces of data in the context of one instruction. This contrasts with scalar processors, which deal with one piece of data for ever
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instruction. Using Flynn's taxonomy, these two schemes of dealing with data are generally referred to as SIMD (single instruction,multiple data) and SISD (single instruction, single data), respectively. The great utility in creating CPUs that deal with vectors of data liesin optimizing tasks that tend to require the same operation (for example, a sum or a dot product) to be performed on a large set of data.Some classic examples of these types of tasks are multimedia applications (images, video, and sound), as well as many types ofscientific and engineering tasks. Whereas a scalar CPU must complete the entire process of fetching, decoding, and executing eachinstruction and value in a set of data, a vector CPU can perform a single operation on a comparatively large set of data with oneinstruction. Of course, this is only possible when the application tends to require many steps which apply one operation to a large set ofdata.
Most early vector CPUs, such as the Cray-1, were associated almost exclusively with scientific research and cryptography applications.However, as multimedia has largely shifted to digital media, the need for some form of SIMD in general-purpose CPUs has become
significant. Shortly after inclusion offloating point execution units started to become commonplace in general-purpose processors,specifications for and implementations of SIMD execution units also began to appear for general-purpose CPUs. Some of these earlySIMD specifications like HP's Multimedia Acceleration eXtensions (MAX) and Intel's MMXwere integer-only. This proved to be asignificant impediment for some software developers, since many of the applications that benefit from SIMD primarily deal with floatingpoint numbers. Progressively, these early designs were refined and remade into some of the common, modern SIMD specifications,which are usually associated with one ISA. Some notable modern examples are Intel's SSE and the PowerPC-relatedAltiVec (alsoknown as VMX).[19]
Performance
Further information: Computer performance andBenchmark (computing)
Theperformance orspeedof a processor depends on the clock rate (generally given in multiples of hertz) and the instructions per clock(IPC), which together are the factors for the instructions per second(IPS) that the CPU can perform.[20] Many reported IPS values haverepresented "peak" execution rates on artificial instruction sequences with few branches, whereas realistic workloads consist of a mix of
instructions and applications, some of which take longer to execute than others. The performance of the memory hierarchy also greatlyaffects processor performance, an issue barely considered in MIPS calculations. Because of these problems, various standardized tests,often called "benchmarks" for this purposesuch as SPECint have been developed to attempt to measure the real effectiveperformance in commonly used applications.
Processing performance of computers is increased by using multi-core processors, which essentially is plugging two or more individualprocessors (called cores in this sense) into one integrated circuit.[21] Ideally, a dual core processor would be nearly twice as powerful asa single core processor. In practice, however, the performance gain is far less, only about 50%, [21] due to imperfect software algorithmsand implementation. Increasing the number of cores in a processor (i.e. dual-core, quad-core, etc.) increases the workload that can behandled. This means that the processor can now handle numerous asynchronous events, interrupts, etc. which can take a toll on theCPU (Central Processing Unit) when overwhelmed. These cores can be thought of as different floors in a processing plant, with each floorhandling a different task. Sometimes, these cores will handle the same tasks as cores adjacent to them if a single core is not enough tohandle the information.
See alsoAccelerated Processing Unit
Addressing modeCISCComputer bus
Computer engineeringCPU core voltageCPU socketDigital signal processor
List of CPU architecturesRing (computer security)RISC
Stream processingTrue Performance IndexWait state
References
1. Envos Corporation (September 1988). "1. INTRODUCTION" (PDF). 1108 USER'S GUIDE(Manual). Envos Corporation. p. 1. RetrievedMay 24, 2012.
2. ^ab Weik, Martin H. (1961).A Third Survey of Domestic Electronic Digital Computing Systems . Ballistic Research Laboratories.3. First Draft of a Report on the EDVAC . Moore School of Electrical Engineering, University of Pennsylvania. 1945.
4. ^abAmdahl, G. M., Blaauw, G. A., & Brooks, F. P. Jr. (1964).Architecture of the IBM System/360 . IBM Research.5. Digital Equipment Corporation (November 1975). "LSI-11 Module Descriptions" . LSI-11, PDP-11/03 user's manual(2nd ed.). Maynard,
Massachusetts: Digital Equipment Corporation. pp. 43.6. ^ (PDF) Excerpts from A Conversation with Gordon Moore: Moore's Law . Intel. 2005. Retrieved 2012-07-25.7. ^ Since the program counter counts memory addresses and not instructions, it is incremented by the number of memory units that the
instruction word contains. In the case of simple fixed-length instruction word ISAs, this is always the same number. For example, a fixed-length 32-bit instruction word ISAthat uses 8-bit memory words would always increment the PC by 4 (except in the case of jumps). ISAsthat use variable length instruction words,increment the PC by the number of memory words corresponding to the last instruction's length.
8. ^ Because the instruction set architecture of a CPU is fundamental to its interface and usage, it is often used as a classification of the"type" of CPU. For example, a "PowerPC CPU" uses some variant of the PowerPC ISA. Asystem can execute a different ISAby running anemulator.
9. ^ Some early computers like the Harvard Mark I did not support any kind of "jump" instruction, effectively limiting the complexity of the
ftp://download.intel.com/museum/Moores_Law/Video-Transcripts/Excepts_A_Conversation_with_Gordon_Moore.pdfhttp://www.classiccmp.org/bitsavers/pdf/dec/pdp11/1103/EK-LSI11-TM-002.pdfhttp://en.wikipedia.org/wiki/Digital_Equipment_Corporationhttp://www.research.ibm.com/journal/rd/441/amdahl.pdfhttp://en.wikipedia.org/wiki/Gene_Amdahlhttp://en.wikipedia.org/wiki/University_of_Pennsylvaniahttp://en.wikipedia.org/wiki/Moore_School_of_Electrical_Engineeringhttp://www.virtualtravelog.net/entries/2003-08-TheFirstDraft.pdfhttp://en.wikipedia.org/wiki/Ballistics_Research_Laboratoryhttp://ed-thelen.org/comp-hist/BRL61.htmlhttp://www.bitsavers.org/pdf/xerox/interlisp/400004_1108UsersGuide_Sep88.pdfhttp://en.wikipedia.org/w/index.php?title=Envos_Corporation&action=edit&redlink=1http://en.wikipedia.org/w/index.php?title=Central_processing_unit&action=edit§ion=15http://en.wikipedia.org/wiki/Wait_statehttp://en.wikipedia.org/wiki/True_Performance_Indexhttp://en.wikipedia.org/wiki/Stream_processinghttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/Ring_(computer_security)http://en.wikipedia.org/wiki/List_of_CPU_architectureshttp://en.wikipedia.org/wiki/Digital_signal_processorhttp://en.wikipedia.org/wiki/CPU_sockethttp://en.wikipedia.org/wiki/CPU_core_voltagehttp://en.wikipedia.org/wiki/Computer_engineeringhttp://en.wikipedia.org/wiki/Computer_bushttp://en.wikipedia.org/wiki/Complex_instruction_set_computerhttp://en.wikipedia.org/wiki/Addressing_modehttp://en.wikipedia.org/wiki/Accelerated_Processing_Unithttp://en.wikipedia.org/w/index.php?title=Central_processing_unit&action=edit§ion=14http://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Multi-core_processorhttp://en.wikipedia.org/wiki/SPECinthttp://en.wikipedia.org/wiki/Benchmark_(computing)http://en.wikipedia.org/wiki/Memory_hierarchyhttp://en.wikipedia.org/wiki/Instructions_per_secondhttp://en.wikipedia.org/wiki/Hertzhttp://en.wikipedia.org/wiki/Benchmark_(computing)http://en.wikipedia.org/wiki/Computer_performancehttp://en.wikipedia.org/w/index.php?title=Central_processing_unit&action=edit§ion=13http://en.wikipedia.org/wiki/AltiVechttp://en.wikipedia.org/wiki/Streaming_SIMD_Extensionshttp://en.wikipedia.org/wiki/Floating_pointhttp://en.wikipedia.org/wiki/MMX_(instruction_set)http://en.wikipedia.org/wiki/Multimedia_Acceleration_eXtensionshttp://en.wikipedia.org/wiki/Floating_point_unithttp://en.wikipedia.org/wiki/Cryptographyhttp://en.wikipedia.org/wiki/Cray-1http://en.wikipedia.org/wiki/Scientific_computinghttp://en.wikipedia.org/wiki/Multimediahttp://en.wikipedia.org/wiki/Dot_producthttp://en.wikipedia.org/wiki/SISDhttp://en.wikipedia.org/wiki/SIMDhttp://en.wikipedia.org/wiki/Flynn%27s_taxonomy -
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programs they could run. It is largely for this reason that these computers are often not considered to contain a CPU proper, despite theirclose similarity as stored program computers.
10. ^ The physical concept ofvoltage is an analog one by its nature, practically having an infinite range of possible values. For the purpose ofphysical representation of binary numbers, set ranges of voltages are defined as one or zero. These ranges are usually influenced by thecircuit designs and operational parameters of the switching elements used to create the CPU, such as a transistor's threshold level.
11. ^ While a CPU's integer size sets a limit on integer ranges, this can (and often is) overcome using a combination of software andhardware techniques. By using additional memory, software can represent integers many magnitudes larger than the CPU can.Sometimes the CPU's ISAwill even facilitate operations on integers larger than it can natively represent by providing instructions to makelarge integer arithmetic relatively quick. While this method of dealing with large integers is somewhat slower than utilizing a CPU withhigher integer size, it is a reasonable trade-off in cases where natively supporting the full integer range needed would be cost-prohibitive.SeeArbitrary-precision arithmetic for more details on purely software-supported arbitrary-sized integers.
12. ^ In fact, all synchronous CPUs use a combination ofsequential logic andcombinational logic. (See boolean logic)
13. ^ Brown, Jeffery (2005). "Application-customized CPU design" . IBM developerWorks. Retrieved 2005-12-17.14. ^ Garside, J. D., Furber, S. B., & Chung, S-H (1999).AMULET3 Revealed . University of ManchesterComputer Science Department.15. ^ NeitherILPnorTLP is inherently superior over the other; they are simply different means by which to increase CPU parallelism. As such,
they both have advantages and disadvantages, which are often determined by the type of software that the processor is intended to run.High-TLP CPUs are often used in applications that lend themselves well to being split up into numerous smaller applications, so-called"embarrassingly parallel problems". Frequently, a computational problem that can be solved quickly with high TLP design strategies l ikeSMP take significantly more time on high ILP devices like superscalar CPUs, and vice versa.
16. ^ Huynh, Jack (2003). "The AMD Athlon XP Processor with 512KB L2 Cache" . University of Illinois Urbana-Champaign. pp. 611.Retrieved 2007-10-06.
17. ^ Best-case scenario (or peak) IPC rates in very superscalar architectures are difficult to maintain since it is impossible to keep theinstruction pipeline filled all the time. Therefore, in highly superscalar CPUs, average sustained IPC is often discussed rather than peakIPC.
18. ^ Earlier the term scalar was used to compare the IPC (instructions per cycle) count afforded by various ILP methods. Here the term isused in the strictly mathematical sense to contrast with vectors. Seescalar (mathematics) andVector (geometric).
19.^
Although SSE/SSE2/SSE3 have superseded MMX in Intel's general purpose CPUs, laterIA-32 designs still support MMX. This is usuallyaccomplished by providing most of the MMX functionality with the same hardware that supports the much more expansive SSE instructionsets.
20. "CPU Frequency" . CPU World Glossary. CPU World. 25 March 2008. Retrieved 1 January 2010.
21. ^ab"What is (a) multi-core processor?" . Data Center Definitions. SearchDataCenter.com. 27 March 2007. Retrieved 1 January 2010.
External links
How Microprocessors Work at HowStuffWorks.25 Microchips that shook the world an article by the Institute of Electrical andElectronics Engineers.
CPU technologies
Basic computer components
Categories: Central processing unit
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