emitter coupled logic (ecl)
TRANSCRIPT
A Presentation On Emitter Coupled Logic
Course Title: Digital Electronics and Pulse Techniques
Course No: ECE 2203
Presented To:Shakila NazninLecturerElectronics & Communication Engineering DisciplineKhulna university,Khulna.
Presented By:Group 2Student ID:120902,120928,1209332nd Year 2nd TermElectronics & Communication Engineering DisciplineKhulna university,Khulna
Date of Presentation: 08 Sep, 2014
Emitter
Coupled
Logic
ECL Vs Others Logic Gate
Differential amplifier configuration
Taking cut-off & active modeLower time delayTaking negative voltage
supply
Why ECL?More speedySmall voltage swingFastest switchingConstant current supplyNoise immunity
Disadvantages Low fan-out Input-Output voltage
variation not matching
Basic circuit diagram of ECL
Basic operation of ECL:
All voltage are negativeMore negative= Logic lowLess negative=Logic high
VR>VA,VB
VA,VB>VR
A B Y1
0 0 1
0 1 0
1 0 0
1 1 0
Y1
A B Y2
0 0 0
0 1 1
1 0 1
1 1 1
Y2
NOR
OR
Why it is more speedy?
When, IE1 is 95% of Io
VA=VR+75mV
And IE1 is 5% of Io VA=VR-75mV
VA=VR±75mV
If this circuit drives N similar gates then output current will be N*I0/β
HOW TO SOLVE THE PROBLEM
?
Previous circuit diagram:
Emitter follower is used
Solving the problem of fan-out
Why negative voltage supply used
?
330 ohm
1.5k
V01
V02
Noise margin circuit
V01 ≈ 0
V02 ≈ Vn
Thank you
Any question please