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Emitter-Coupled Logic (ECL) Here, the two emitters of two BJTs are coupled together. Transistors are prevented from going into saturation (non-saturating logic) eliminating storage delays. Logic levels are close to each other so that transistor is turned on by a small increase in base voltage. Fastest and steady current flow from power supply but power consumption is more and less noise immunity. Description The logic level corresponding to logic 1 and logic 0 are –0.9V and –1.7V respectively. Input is applied to base of Q1 and base of Q2 is held at average of two logic levels i.e. -1.3V by a internally regulated source. If base of Q1 is at logic LOW(-1.7V): The total voltage tending to forward bias BE junction of Q1 is –1.7-(-5.2) = 3.5V whereas that for Q2 is –1.3-(-5.2) = 3.9V. Since Emitter of both Q1 and Q2 are at common potential it is –1.7 – 0.8 = -2.5V if Q1 is on [Transistors are specially made to have BE drop 0.8V at forward bias] and –1.3 – 0.8 = -2.1V if Q2 is on. They cannot be on simultaneously. The one that is ‘most’ forward biased is on. In this case Q2 is on and Q1 is off. If base of Q1 is at logic HIGH(-0.9V): By similar logic Q1 is on and Q2 is off with common emitter voltage at –0.9-0.8 = -1.7V IE = (VIN – VBE(on) + 5.2)/R3 = (VIN + 4.4)/R3 ≈ IC [Since only one transistor is on and IB small] Current IE switches from Q1 to Q2 or the reverse with the change in input logic level. At the collector of Q1 voltage when input LOW = 0V (GND) At the collector of Q1 voltage when input HIGH = 0 – ICR1 = -(-0.9 + 4.4)R1/R3

If R1 = 290Ω and R3 = 1.18KΩ this voltage is –3.5x0.29/1.18 ≈ -0.9V Therefore outputs are fairly independent of transistor parameters. Also though individual resistance values may vary a lot the ratio does not.

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Two Input ECL OR/NOR Gate

Typical values: R1 = 290Ω, R2 = 300Ω, R3 = 1.18KΩ, R4 = 1.5KΩ, R5 = 1.5KΩ When both A and B are LOW i.e. Q1A and Q1B off R1 is chosen such that base current of Q3 makes IB3R1 ≈ -0.1V Similarly value of R2 is chosen such that under this condition I2 flowing through puts the collector of Q2 at ≈ -0.9V

Now emitter of Q3 is at –0.1 - 0.8 = -0.9V and that for Q4 is –0.9 - 0.8 = -1.7V

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When at least one input is HIGH i.e. either Q1A or Q1B conducts

By similar logic the outputs of Q3 and Q4 are opposite. And we get following Truth Table.

The differential input circuitry in ECL gates provide common mode rejection. Power supply noise common to both sides of the differential configuration is effectively differenced out. Modern ECL circuits have internal pull down resistors connected between each input and negative power supply to prevent build up of charge on stray capacitances when input is open.

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Noise Margin Current through Q1 and Q2 are same when VIN = -1.3V (Reference voltage) at the midpoint of transition. Current through a diode changes a factor of 10 for each change of 60mV across the junction. With voltage at base of Q1 just 60mV less than base of Q2 the current in Q2 is 10 times more and vice versa. (This is the Current switch action.) The transition width is ≈ 120 mV is independent of transistor parameters and is centred around reference voltage. Transition width = VIH – VIL = 240 mV (then current 0.01 percent) Therefore, VIH = -1.3 + 0.12 = -1.18V and VIL = -1.3 - 0.12 = -1.42V Thus NMH = VOH – VIH = -0.9 – (-1.18) = 0.28V NML = VIL – VOL = -1.42 – (-1.7) = 0.28V Fanout Since ECL output is produced at an emitter follower, the output impedance is desirably small, typically 7 ohm. For this ECL has huge fanouts and are relatively unaffected by capacitive loads. With minimum VIH = -1.18V voltage at base of Q4 = -1.18-(-0.8) = -0.38V IB4 = (0 – (-0.38))/0.29 = -1.31mA (Since, Q1 is off) Current available for load Ioutput = (βF + 1)IB4 – (VIH – (-5.2))/R4

= (30+1)x1.31 – (-1.18+5.2)/1.5 = 37.93 mA Assuming gate input current to be 100 microamp, the fanout is 37.93/0.1 → 379 Note that for any fast logic fanout limitation comes from capacitive load rather than current loading.

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Wired-OR Connections ECL gates are available with open emitter outputs – i.e. with the resistors in the output emitter followers omitted. All logic gates in the 10K and 10KH series have open emitter outputs. Open emitter outputs can be connected directly together and to an external resistor to perform wired-OR operation.

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Integrated Injection Logic (I2L) This is newest of the logic families using BJTs and do not require any space consuming resistors. It is easily fabricated and ecomomical with speed power product 4 pJ comparable to advanced low power Schottky TTL. PNP transistor Q1 serves as a constant current source that injects current in node X. There the direction of current flow depends on input level. A LOW sinks current diverting current from base of Q2. Therefore Q2 is off and its output HIGH. The reverse happens if input is HIGH and then output is LOW. In actual I2L circuit the output transistor has two collectors (sometimes three), making it equivalent to two transistors with parallel bases and emitters. Thus it produces two equal outputs. Instead of a collector resistor, the outputs are connected directly to the inputs of other I2L gates. I2L can also be interpreted in terms of current flow: Current flowing through a transistor is LOW and no current is HIGH. Equivalently, a on transistor capable of sinking current is LOW and an off transistor that prevents current from flowing into it is HIGH. Typically, V = 0.8V.

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