HighSpeed

FullSpeed

SuperSpeed

More nasty software bugs 9

Creating an event-flow tracer 23

Ganssle’s mailbox overflows 34

VOLUME 23,NUMBER 9

E M B E D D E D S Y S T E M S D E S I G NThe Official Publication of The Embedded Systems Conferences and Embedded.com

USB 3.0:cranking up to superspeed 14

NOVEMBER 2010

The desire to extend battery life in the fast growing mobile com-puting market has placed a new spotlight on power managementwithin portable systems. Developers of laptops, netbooks, smartphones, and tablets now scrutinize every amp of power usage atthe system level in their drive for better power efficiency. The in-troduction of USB 3.0 brings new opportunities to boost batterylife for both host and endpoint functions thanks to comprehen-sive power-management features that operate autonomously atthe hardware level.

USB 3.0 offers new opportunities to boost battery life for both host and endpointfunctions thanks to comprehensive power management features that operate

autonomously at the hardware level.

BY MIKE MICHELETTI

14 NOVEMBER 2010 | embedded systems design | www.embedded.com

Designed to overcome the draw-backs of the Advanced Power Manage-ment (APM) model, the Advanced Con-figuration and Power Interface, or ACPI,was introduced in1997. The specifica-tion brings some level of power aware-ness to the BIOS, system hardware andsoftware. ACPI relies on tables in theBIOS to define the power modes for in-dividual peripherals. The operating sys-tem then uses these definitions to decide

when to switch a device, or the entiresystem, from one power state to another.USB 2.0 has supported this software-based approach relying on suspend-re-sume commands to place the universalserial bus in a power-reduced state.However, these ACPI-based implemen-tations have been plagued by stabilityand latency issues.

Implementing an effective power-management policy for interfaces such

USB 3.0: Deliveringsuperspeed with25% lower power

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HighSpeed

FullSpeed

SuperSpeed

as USB presents additional challenges.USB is one of the few peripheral busesthat allow different types of deviceswith varying usage frequencies to at-tach simultaneously. Many of theseUSB devices experience extended peri-ods of idle. In addition, developersmust contend with the growing popu-larity of devices that draw power orrecharge batteries over USB.

The USB 2.0 power-management

model was enhanced with the intro-duction of Link Power Management(LPM) in the EHCI specification 1.1.The new LPM transaction is similar tothe existing USB 2.0 suspend/resumecapability, however—it defines a mech-anism for faster transition of a rootport from an enabled state (L0) to anew sleep state (L1). ImplementingLPM requires changes at both the chipand software layers, which have slowed

market adoption. Table 1 outlines theLPM entry and exit timing windows.

USB 3.0: DESIGNED FOR POWEREFFICIENCYRecognizing that continued adoptionof USB will require improved powerefficiency, the USB Implementers Fo-rum (USB-IF) has made power man-agement a cornerstone to its next gen-eration interface, SuperSpeed USB. For

backwards compatibility, USB 3.0 de-vices are required to support both 2.0and 3.0 link speeds. USB 3.0 devices willmaintain separate controllers and physi-cal layers for high/full speed and super-speed links. To ensure power savingsgained while operating in USB 3.0 modeare not lost when 3.0 hosts are connect-ed to legacy 2.0 devices, all USB 3.0ports (host and device) are now requiredto support the LPM feature above whenoperating at high/full speed. Correctpower-management operation in both

legacy USB 2.0 mode as well as super-speed mode will be verified during USB3.0 logo certification.

SuperSpeed USB uses dual simplexdifferential signaling operating at 5 GHzfrequency to provide a 10x performanceincrease over high-speed USB. The high-er power required to drive the 5 GHzsignaling in superspeed mode is more

than offset by the improved efficiency of3.0 data transfers. The USB-IF estimatesthe system power necessary to completea 20-MB superspeed data transfer will be25% lower when compared with high-speed mode. This is possible becauseseveral architectural issues that ham-pered USB 2.0 power efficiency havebeen enhanced in the USB 3.0 specifica-tion below:

• Elimination of device polling by al-lowing devices to asynchronouslysignal when they need service fromthe host.

• The ability for device ports to initi-ate low-power states.

• The ability for device ports to re-move power from all or portions oftheir circuitry (function level sus-pend).

• The ability to use data streaming forbulk transfers.

• More efficient token/data/hand-shake sequence.

• The addition of packet routingeliminates the need to broadcastpackets to all endpoints downstreamfrom hubs.

In addition to these changes, USB3.0 improves efficiency by implementingpower management at the link layer toprovide greater speed and precision inmanaging power consumption. Figure 1

16 NOVEMBER 2010 | embedded systems design | www.embedded.com

The higher power requiredto drive the 5-GHz signal-ing in superspeed mode ismore than offset by theimproved efficiency of 3.0data transfers.

!!!

25% less system power is used during a SuperSpeed 20-Mbyte data transfer compared with high-speed.

Syst

em p

ower

Figure 1

13 W12.5 W

7 W

Time

Average system power using superspeed device7.5 W

Average system power using high-speed device9.7 W

High-speed USB 2.0data transfers

SuperSpeed USB 3.0data transfers

shows the power savings when using superspeed data transfer. Table 2 outlines the four power states in USB 3.0. Each

state incrementally lowers power use while increasing the al-lowed exit latency. This method provides a more adaptivepower-management model that uses timers and link-stateawareness to reduce power use. Although the specifics of howdevices will lower their power draw are left to the vendor,Table 2 outlines the link states defined by the USB 3.0 specifi-cation.

Most early 3.0 devices rely on inactivity timers to initiateentry into the U1 state. In the U1 state, these devices will typi-cally reduce power to their SuperSpeed PHY. These devices willprogressively lower power to other parts of the interface as theinactively period increases. In some cases, host ports will im-mediately request transition to the most aggressive power sus-pend state (U3) during idle periods. This more rigid approachto lowering power draw is generally initiated by higher layersand is based on expected usage patterns for specific deviceclasses. USB 3.0 also preserves function-suspend features fromUSB 2.0 allowing individual functions to be placed into a lowerpower state. The remainder of this article explores the Super-Speed power-management model and the power-state transi-tions required by the USB 3.0 specification.

CONFIGURE USB DEVICES FOR POWER MANAGEMENT Four steps are involved in configuring a USB 3.0 device forpower management.

1. Devices must report their level of support for powermanagement within their Endpoint Descriptors. Whileit’s required for all devices to support power managementto gain SuperSpeed certification, USB developers may electto configure devices with this functionality disabled forspecific applications.

2. Host must send SET_FEATURE to U1/U2_ENABLE duringconfiguration. Alternatively, some peripheral devices thatare used intermittently may aggressively direct their ownlinks to the lower power state. Higher layers require amechanism to enable (or disable) the upstream port’s abil-ity to request low-power entry. When asserted, U1/U2_EN-ABLE allows the upstream port to initiate entry to U1/U2.

3. Host must send Link Management Packet (LMP) to de-fine the U1/U2 Inactivity Timeout. The U1/U2 inactivitytimers allow the host to define the time interval betweenthe U0 > U1 and the U1 > U2 power-state transitions.

These timers provide the flexibility to delay power statetransitions for specific applications, such as Blu-Ray diskwriters, that could suffer usability problems if response la-tency is introduced. The U1 and U2 inactivity timeout canbe as long as 127 µs and 65 ms respectively. Sending anLMP with the U1 inactivity timeout value between therange 0x01-0xFE also serves to implicitly enable the hostport to initiate U1/U2 transitions.

4. Host will inform the device of the U1/U2 System Exit La-tency using SET_SEL. Reporting System Exit Latency(SEL) allows the host to more intelligently manage powerstate transitions for periodic endpoints, such as isochro-nous devices. SEL represents the total latency to transitionthe entire path of links between the device and host fromU1/U2 back to U0. It provides a mechanism for higher lay-ers to reduce or even disable U1/U2 entry if system exit la-

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USB 2.0 Link Power Management (LPM) states. Entry Exit L1 Sleep Host-initiated via LPM extended transaction Device or host-initiated via resume signaling; Entry: ~10 µs Remote-wake can be (optionally) enabled/disabled via software Exit latency: ~70 µs to 1 ms (host-specific). L2 Suspend Implicitly entered after 3 ms of link inactivity Device- or host-initiated via resume signaling; (OS-dependent)Table 1

tency exceeds the minimum serviceintervals reported by the device. Fig-ure 2 shows a host-device exchangeof Power Management Configura-tion data.

TRANSITIONING FROM U0 >U1Either link partner can initiate a transi-tion from U0 >U1 based on the expira-tion of the PORT_U1_TIMEOUT timer. Al-ternatively, some devices may attempt tosave power by proactively initiating U1mode more aggressively by setting theirU1_Enable feature selector and reportingtheir U1 Inactivity Timeout equal to 0.

Initial entry into a low-power stateis always negotiated between ports usingthe LGO_Un followed by LAU (accept) orLXU (reject). The port sending the LAUshould wait until it receives a singleLPMA (accept response), which serves asa final handshake before transitioningto any of the low-power states. To maxi-mize power savings, ports are requiredto respond to power-management com-

mands within the PM_LC_TIMER time-out. If the port initiating the statechange does not receive an LAU or LXUbefore the PM_LC_TIMER expires (3 µs),it’s considered a link error and shouldinitiate recovery.

Alternatively, if after sending theLAU, the device doesn’t receive the LPMAor any other valid traffic (such as TS1,LFPS, Link Command) before thePM_ENTRY_TIMER expires (6 µs), itshould proceed to the low-power state

anyway. In this event, it’s assumed theLPMA was corrupted and the port issuingthe LGO_U1 has already entered U1.

TRANSITIONING FROM U1 > U2The transition from U1 to U2 is general-ly triggered by a second timer called theU2_Inactivity_Timer which, whenenabled, will silently move the link to thelower power U2 state. This U2 inactivitytime out value is reported by the end-point’s configuration descriptor. It’s thehost responsibility to enable this timerusing the U2 Inactivity Timeout LMP.When a link enters U1, this starts the U2inactivity timer and provides a mecha-nism for the port to autonomouslymove to the U2 state.

For some devices, it may not bepractical for individual endpoint func-tions to enter U1 (in other words, com-posite devices that may have a sharedPLL). Some devices may bypass the U1mode altogether and instead transitionthe link from U0 directly to U2 using theLGO_U2 link command thus allowing alarger portion of the SuperSpeed inter-face to be suspended. A device can beconfigured to support U2 exclusivelywith SET_FEATURE: U1_DISABLE.

As mentioned previously, some de-vices may attempt to save more powerby immediately transitioning to U1 orU2, using the U1/U2_Enable feature se-lector. For example, storage devices mayimmediately issue an LGO_U2 after eachtransfer if the packets pending bit is de-asserted in the previous transactionpacket.

TRANSITIONING FROM U0 > U3The U3 state is a deep power-saving statewhere interface power may be removed.It’s the equivalent of Suspend state inUSB 2.0, and it can only be initiated by adownstream facing port using theLGO_U3 followed by LAU (accept). Up-stream facing ports are not allowed toreject the LGO_U3. While the goal is toconserve as much power as possible,while in U3, a port must still maintainits Warm Reset detect, U3 wake detect,(for host initiated wakeup) as well as

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The U3 state is a deeppower-saving state whereinterface power may beremoved. It’s the equiva-lent of Suspend state inUSB 2.0

!!!

Logical link states defined in USB 3.0. Link Key Exit state Description characteristics latency U0 Link active NA U1 Link idle, fast exit RX & TX circuit quiesced µs range U2 Link idle, slow exit Clock generation circuit also quiesced Low ms range U3 Suspend Portions of device power removed Higher ms rangeTable 2

Host-device exchange of Power Management Configuration data.

Figure 2

wake transmission (for remote_wakecapable devices).

TRANSITIONING FROM U1/U2 >U0Returning a link from U1 to U0 activestate mandates the shortest recoverytime in the range of 10 µs. This transi-tion is normally initiated when a pack-et needs to be transmitted, such as anIN message from the host, or an ERDYmessage from the device. Ports in lowerpower states need a mechanism to sig-nal its link partner to begin the link re-covery process. Low Frequency Period-ic Signaling (LFPS) is a 50-MHzside-band signal that provides a portwith a low-power mechanism to send a“wake signal” to a link partner. Bothsides must receive an LFPS “hand-shake” to avoid entering the Recoverylink state before the far-end receiver isready.

To deliver acceptable performance,SuperSpeed devices use a low-latencyrecovery sequence that provides astreamlined way to retrain links whenexiting these low-power conditions. Su-perSpeed ports may also enter the Re-covery state when errors are detectedduring data transfers. In both cases,only TS1 and TS2 ordered sets are ex-changed with the goal of returning thelink to U0 as quickly as possible.

RESOLVING CONFLICTS BETWEENCOMMANDSNumerous rules and conditions are de-fined in the USB 3.0 specification to pre-serve the integrity of the link duringpower-state changes. Included are obvi-ous requirements such as disallowingdevices from starting low-power transi-tions unless they have transmitted andreceived all pending data packets, ac-knowledgements, flow-control link com-mands, header and buffer credit adver-tisements. There are also rules to ensurelinks maintain coherency in the event anexpected power-management responseis not received.

For example, a port that sends U1 orU2 exit signal but does not receive anLFPS handshake from its link partnershould transition to the SS.disabled state(assumes the sleeping device is removedfrom the system). Because power-statechanges can be initiated by both hostand peripheral device ports, several rulesare designed to manage link-state raceconditions and potential conflicts be-tween ports. For example, peripheral de-vices that have sent an LGO_U1 orLGO_U2 and also received an LGO_U3,should wait until they receive an LXUfrom the host and then send an LAU ac-cept for the U3 request.

In the case of a host port that has

been directed (by a higher layer) to initi-ate a transition to U3 while a transitionto U1 or U2 has been initiated but notyet completed, the host port shouldcomplete the in-process transition to U1or U2, then immediately return to U0and request entry to U3.

TESTING AND VERIFYING USB 3.0POWER MANAGEMENTTo ensure USB 3.0 devices properly im-plement these power management be-haviors, they will be verified during theUSB-IFs SuperSpeed certification pro-gram. Testing devices to ensure reliableoperation in power-managed environ-ments raises a substantial verificationchallenge. Post-silicon functional testteams may struggle to simply initiatepower-management transitions as thenecessary commands occur at the low-est layers making them difficult to con-trol using software. Entrance and exitfrom these low-power states must occurwithin rigid predefined time limits.This task is greatly simplified by proto-col-layer test tools that have the follow-ing capabilities:

• Low-level traffic generation—Totest many of the link states outlinedabove requires special test systemsthat can control and manipulate thelogical link layer. Most functionaltest teams rely on traffic generatorscapable of emulating real device be-haviors to perform this testing.These tools should be capable ofcreating intentional timing viola-tions and invalid state transitions totest error recovery on the device-un-der-test. The ability to arbitrarilycontrol link-layer handshaking in aconsistent and repeatable way is im-portant for validating power man-agement and other USB 3.0 link lay-er behaviors.

• Accurate capture of U1 recovery se-quence—The SuperSpeed transitionfrom U1 to the active state(Ux_EXIT_TIMER) mandates bothports should enter U0 within 6 msor the link will enter SS.disabled.

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Test tools capable of monitoring link state changes with independent timers in each state are essential for identifying timing violation

Figure 3

Unlike Power-on link training, re-covery from U1 uses a fast link-training sequence without the addedequalization training symbols. Thisfrequent retraining can occur in aslittle as 1µs, which places consider-able pressure on analysis tools asthey must seamlessly capture theLFPS handshaking and achieve 5-GHz signal lock during this short-ened link-training sequence.

• Triggering on power link-statechanges—Traffic at the logical linklayer is invisible to the upper layersof USB 3.0 protocol making it im-possible to see Link Commands us-ing software-based tools. This man-dates using an inline protocolanalyzer capable of accurately cap-turing link-layer traffic between de-vices. Triggering on link commandssuch as the LGO/LAU exchange andthe LFPS wake signals are critical forefficient power management debug.

• Triggering on power-managementtimeouts—Returning to U0 fromthe U1 low-power state has provento be a common problem area forearly devices. This transition in par-ticular can occur hundreds of timesin only a few seconds. To minimizelatency at the application layer, de-vices are required to enter and exitpower save modes within very shorttiming windows. For example, dur-ing the low-power exit sequence,both link partners must exchangean LFPS exit handshake within 2 ms(tNoLFPSResponseTimeout). If ei-ther side fails to send the requiredresponse, the opposite link will goto SS.disabled and the link shouldrevert to USB 2.0 mode. Testingthese behaviors is simplified if de-velopers can set up independentevent timers that trigger when ei-ther a handshake or the requiredstate change is late. It’s particularlyuseful to have a mechanism, such asthat shown in Figure 3, for captur-ing rare or intermittent timing vio-lations during these power-manage-ment transitions.

• Monitoring VBUS power draw—VBUS power supplied by the down-stream facing port can represent asignificant source of battery drainfor mobile platforms. Test equip-ment is now available that mergesvoltage meter functionality withprotocol analyzer features. Thesesystems, such as the one shown inFigure 4 by LeCroy, help users cor-relate actual VBUS power draw withprotocol-layer state changes. Thesetools will typically display voltagegraphically in a timeline format.This power information is synchro-nized to I/O requests, enabling usersto correlate power use at the electri-cal layers with commands occurringat the higher layers. ■

Mike Micheletti is the senior product mar-keting manager at LeCroy with over 10years of experience defining high-speedserial data acquisition solutions for USB,WiMedia, Bluetooth, SAS, SATA, and Fi-bre Channel. Micheletti is a regular con-tributor to the USB-IF Compliance Work-ing Group.

FURTHER READING:1. Ethier, Sheridan. “Application-Driven

Power Management,” 2004, QNX SoftwareSystems Ltd.

2. “Universal Serial Bus 3.0 Specification,”USB Implementers Forum Inc., 2008,www.usb.org.

3. Walsh, James. “SuperSpeed USB PowerManagement,” 2008, www.usb.org.

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Power monitoring tools measure and display vBUS power draw graphically in a timeline format.

Figure 4