embedded fpga design for optimal pixel adjustment process...

Research ArticleEmbedded FPGA Design for Optimal Pixel Adjustment Processof Image Steganography

Chiung-Wei Huang 12 Changmin Chou 2 Yu-Che Chiu1 and Cheng-Yuan Chang 1

1Chung Yuan Christian University Taoyuan City Taiwan2Chien Hsin University of Science and Technology Taoyuan City Taiwan

Correspondence should be addressed to Cheng-Yuan Chang ccycycuedutw

Received 4 November 2017 Revised 5 February 2018 Accepted 19 February 2018 Published 22 March 2018

Academic Editor Ahmed Refaey

Copyright copy 2018 Chiung-Wei Huang et al This is an open access article distributed under the Creative Commons AttributionLicense which permits unrestricted use distribution and reproduction in any medium provided the original work is properlycited

We propose a prototype of field programmable gate array (FPGA) implementation for optimal pixel adjustment process (OPAP)algorithm of image steganography In the proposed scheme the cover image and the secretmessage are transmitted from a personalcomputer (PC) to an FPGA board using RS232 interface for hardware processing We firstly embed 119896-bit secret message into eachpixel of the cover image by the last-significant-bit (LSB) substitution method followed by executing associated OPAP calculationsto construct a stego pixel After all pixels of the cover image have been embedded a stego image is created and transmitted fromFPGA back to the PC and stored in the PC Moreover we have extended the basic pixel-wise structure to a parallel structure whichcan fully use the hardware devices to speed up the embedding process and embed several bits of secret message at the same timeThrough parallel mechanism of the hardware based design the data hiding process can be completed in few clock cycles to producesteganography outcome Experimental results show the effectiveness and correctness of the proposed scheme

1 Introduction

In this digitized era almost all kinds of information such asplain texts voices images and videos can be digitally pre-sented leading to the birth of a wide range of digital mediaIncreased Internet applications also lead people frequentlyto deliver digitized information In the information deliveryprocess the data hiding technology plays an important rolein issues such as data security for digital communicationscopyright protection for digital assets the use of digitalmediato conceal communications and certification of variouselectronic services

Data hiding technique is to hide confidential messagesinto a cover media such that an unintended observer willnot be aware of the existence of the hidden information Theconfidential message can also be compressed and encryptedbefore embedding to an image Embedding data into animage is one of the methods of data hiding to achieve datasecurity In this paper 8-bit grayscale images are selected asthe cover imagesThe cover images embedded with the secret

message are called the stego images For data hidingmethodsthe image quality refers to the quality of the stego images

Many image steganography techniques have been pro-posed in the last two decades These techniques can beclassified into two domains frequency domain techniquesand image (spatial) domain techniques [1] Most frequencydomain techniques apply discrete cosine transform (DCT)[2 3] or discrete wavelet transform (DWT) [4 5] techniqueson images to manipulate the coefficients of frequency trans-forms The image domain techniques usually apply bit inser-tion and noise manipulation procedures on cover images [6]

The data hiding operation will result in distortion inthe cover image For some sensitive applications such asmilitary or medical images it is desirable to restore theoriginal cover image from the stego image after extraction ofthe hidden data The reversible data hiding technology hasbeen identified as an effective way for integrity and copyrightprotection Reversible data hiding techniques can be roughlyclassified into three types [7] lossless compression basedmethods [8 9] difference expansion (DE) methods [10ndash12]

HindawiMathematical Problems in EngineeringVolume 2018 Article ID 5216029 8 pageshttpsdoiorg10115520185216029

2 Mathematical Problems in Engineering

and histogram modification (HM) methods [13 14] Thelossless compression based methods make use of statisticalredundancy of the cover image by performing lossless com-pression to create a spare space to accommodate additionalsecret dataTheDE-basedmethods divide an image into pixelpairs and embed secret data into expanded difference valuesTheHM-basedmethods shift several or the maximum pointsin histogram bins of the original image to reserve spare spacefor data embedding

Among image domain techniques the last-significant-bit(LSB) replacement method [8 9] which proposes to replacethe least 119896-bit of the cover images by the secret message isthe most straightforward algorithm for embedding messageinto images Since the LSB replacement method is easyto be detected and the secret message will be cracked bymalicious attackers more sophisticated methods such asthe optimal moderately significant-bit replacement method[11] or the differences between original and predicted pixelvalues method [12] have been proposed and gotten certaindegrees of success However most published techniques wereimplemented by using software schemes and few researchimplemented image steganography algorithms on hardwaremethods Usually hardware implementations are faster thansoftware implementations in that the hardware logic gatescan be processed in a parallel processing manner The higherthe complexity of the algorithm is the more advantages thehardware implementations can get

During recent years field programmable gate array(FPGA) has become the dominant form of programmablelogic [15] In comparison to previous programmable deviceslike programmable array logic (PAL) and complex pro-grammable logic devices (CPLD) FPGA can implement farlarger logic functions than the others In addition FPGAnot only supports sufficient logic arrays to implement morecomplicated systems and subsystems but also exploits theincreasing capacity of integrated circuits to provide designerswith reconfigurable logic arrays that can be programmed onapplication specific basis This drastically increases the flex-ibility in both the design process and the final manufactureby permitting a board-level design to perform many func-tions

Among all presented techniques optimal pixel adjust-ment process (OPAP) [11] is one of the well-defined algo-rithms for image data hiding Some other data hidingalgorithms may have more information capacity but theirhardware implementations will be much more complicatedIn this paper we proposed an OPAP design of circuitusing FPGA with the hardware description language VerilogHDL (Hardware Description Language) The FPGA boardXilinx Spartan-3E Starter Kit is applied to fulfill the imagedata hiding technique Using both software and hardwarebased schemes two image hiding experiments are fulfilledto compare the correctness and efficiency of the proposedhardware based FPGA method

The rest of the paper is organized as follows Section 2introduces the works about the LSB substitution method andOPAP technique The steps to implement image steganog-raphy by FPGA are also described in detail In Section 3experimental evaluation and discussion about data hiding

Secret message

Cover pixel

LSBsubstitution

Stego pixel110(2)

10000010(2)

10000110(2)

Figure 1 An example of the LSB substitution method

into images are presented to verify the enhancement of thehardware based image steganography technique

2 Image Steganography by FPGA

In this section we introduce the related works about the LSBmethod and the OPAP technique which are essential to thedata hiding process

21 Related Works

211 e LSB Substitution Method The LSB substitutionmethod is a simple and easy image steganography methodThis method replaces the 119896 least significant bits (LSB) bysecret messages in each pixel In a 256-level gray image thevalue of each pixel is usually represented in an 8-bit binaryform

119901 = (1198877 times 27 + 1198876 times 26 + sdot sdot sdot + 1198870 times 20) (1)

where 119901 is the value of a pixel and 119887119894 (0 le 119894 le 7) representsthe 8-bit binary As an example of the LSB substitutionmethod for a pixel value 130(10) secret message 110(2) andreplacement width 119896 = 3 we can try to embed the secretmessage into the pixel of image Therefore the original 8-bit binary value is 10000010 before the data hiding and itbecomes 10000110 after substituting the least 3 significant bitsby the secretmessage 110(2)Thepixel value has changed from130(10) to 134(10) and the difference of 4(10) will not be noticedby human observation Figure 1 illustrates this example of theLSB substitution method

212 OPAP Algorithm An OPAP method is proposed toenhance the image quality and security of the stego imageobtained by the LSB substitution method [11] Assume that119901119894 1199011015840119894 and 11990110158401015840119894 are the corresponding pixel values of the 119894thpixel in the cover image the stego image obtained by the LSBsubstitutionmethod and the refined stego image obtained byOPAP approach respectively Let 120575119894 = 1199011015840119894 minus 119901119894 be the embed-ding error between 119901119894 and 1199011015840119894 According to the embeddingprocess of the LSB substitution method 1199011015840119894 is obtained byreplacing the 119896 least significant bits of 119901119894 with 119896-bit secretmessage therefore the range of the embedding error is

minus2119896 lt 120575119894 lt 2119896 (2)

However the value of 120575119894 can be further segmented intothree intervals such that

Interval 1 2119896minus1 lt 120575119894 lt 2119896if 1199011015840119894 ge 2119896 then 11990110158401015840119894 = 1199011015840119894 minus 2119896else 11990110158401015840119894 = 1199011015840119894

Mathematical Problems in Engineering 3

Interval 2 minus 2119896minus1 le 120575119894 le 2119896minus1when 11990110158401015840119894 = 1199011015840119894

Interval 3 minus 2119896 lt 120575119894 lt minus2119896minus1

if 1199011015840119894 lt 256 minus 2119896 then 11990110158401015840119894 = 1199011015840119894 + 2119896else 11990110158401015840119894 = 1199011015840119894

(3)

In the above three cases the absolute value of 120575119894 may fallinto the range 2119896minus1 lt |120575119894| lt 2119896 only when 256 minus 2119896 le 1199011015840119894 lt 2119896For other possible values of 1199011015840119894 the embedding error 120575119894 willfall into range 0 le |120575119894| le 2119896minus122 FPGA Design with the OPAP Algorithm In image datahiding process researchers usually use the peak signal noiseratio (PSNR) to estimate the quality of the stego images ThePSNR is stated as follows

MSE = ( 1119872 sdot 119873)119872sum119894=0

119873sum119895=0

(1199011015840119894119895 minus 119901119894119895)2

PSNR = 10 sdot log10 (2552

MSE)

(4)

where119872 and 119873 are the dimensions of the cover image and119901119894119895 and 1199011015840119894119895 represent the pixels of the cover image and stegoimage respectively The higher PSNR value means the lowerdistortion and better image quality Table 1 shows a typicalresult of embedding secret message to a cover image (Lena)by the OPAP algorithm It shows that the PSNR of the stegoimage will be greater than 30 dB when the replacement width119896 le 4 According to [11] 30 dB is a reasonable thresholdto make the stego image nature enough In other wordsthe secret messages will not be easily noticed or detected bymalicious attackers when 119896 le 4 Thus we set 119896 = 4 in ourexperiments and thorough the following discussion

Figure 2 shows the procedure of the proposed FPGAbased image steganographymethod First the parameters119872119873 and 119896 are transmitted to the FPGA structure by RS-232where119872119873 are the dimension of the cover image and 119896 is thereplacement width of bitsThat is 119896 bits of the secret messagewill be hided into the 119896 LSB bits of one pixel The bigger the 119896value the larger the difference between the cover image andthe stego image The embedding scheme is processed pixelby pixel utilizing FPGA In the proposed FPGA design theOPAP algorithm for embedding a pixel is shown with thefollowing five steps

Step 1 Read the cover image pixel by pixel the pixel 119901119894 iscalled the cover pixel

Step 2 Embed 119896-bit secret message into 119901119894 by the LSBsubstitution method to get 1199011015840119894

Start

Transmit M N k where M N are thedimension of the cover image k isthe replacement width of bits

Transmit k-bit secret message andthe cover image pixel by pixel

Embed k-bit secret message into acover pixel by FPGA

Save the stego pixel

End

Yes (run out of thecover image needanother cover image)

All secret informationhas been embedded

All pixels in thecover image havebeen embedded

No

No

Output the stego image

Yes (embedding success)

Figure 2 The flowchart of the proposed FPGA based procedure

Step 3 Calculate the embedding error 120575119894 = 1199011015840119894 minus 119901119894Step 4 Locate 120575119894 to its corresponding interval and processwith associated calculations according to (3) to produce thestego pixel 11990110158401015840119894 Step 5 Output the embedded stego pixel 11990110158401015840119894 and save it inmemory

After all the secret information has been embedded wecan save and output the stego image The maximum storageof this embedding scheme is119872times119873times119896 bits Since the proposedprocedure embeds the secretmessage to the cover image pixelby pixel the time complexity is 119874(119872 times119873)23 Hardware FPGA Design Method Figure 3 shows thestructure of the hardware FPGA design including thereceiver Stand by Din Lsb sub D emb Transmitter andWork time modules The function of each module is illus-trated as follows


Recevier

RxD_data_ready

Stand_by

Ready

Din_Lsb_sub

FPGA

RxD_datak

Cover

Secret

dim

ok

D

temp_new

D_emb

ok_new

new

Transmitter

k_bits

Work_time

ce

Clocks

RS232data

RS232data

Figure 3 The structure of the hardware FPGA design

231 Receiver Module All information is transmitted fromPC to the Receiver module of the FPGA board via RS232The transmitted information consists of the cover image thesecret message and the replacement width 119896 After receivingthe information the Receiver module removes the headerfrom the cover image followed by passing information to thenext module The output of the Receiver module consists ofRxD data and RxD data ready where the RxD data includesthe raw data of the cover image the secret message and thereplacement width 119896 the RxD data ready signal triggers theStand by module to receive data

232 Stand byModule In the Stand bymodule a finite statemachine (FSM) is designed to save the received data andtransmit a set of embedding information to the nextmodulesThere are four states in the FSM

First state it saves the dimension information119872times119873of the cover imageSecond state it saves the replacement width 119896Third state it saves the cover imageFourth state it saves the secret message and transmitsall information to the next modules

The output of the Stand by module consists of five outputsignals ready 119896 cover secret and dim which representedthe data ready trigger replacement width 119896 raw data of thecover image the secret message and the dimension119872times119873 ofthe cover image respectively In our embedding procedurethe cover image is transmitted pixel by pixel accompaniedwith 119896-bit secret message The replacement width 119896 a coverpixel and 119896-bit secret message will be transmitted to theDin Lsb sub module The dimension information 119872 times 119873will be transmitted to the work time module for calculatingthe overall processing time

233 Din Lsb subModule The functions of theDin Lsb submodule are to operate the 119896-bit LSB substitution and calculatethe embedding error The Din Lsb sub module receives acover pixel 119901119894 119896-bit secret message and the replacementwidth 119896 in one clock cycle The cover pixel 119901119894 is firstlyembedded with 119896-bit secret message by the LSB substitutionmethod to get 1199011015840119894 After calculating the embedding error120575119894 = 1199011015840119894 minus 119901119894 the Din Lsb sub module transmits the replace-ment width 119896 the LSB substitution result 1199011015840119894 and theembedding error 120575119894 to the D-emb module The output ofthe Din Lsb sub module consists of four output signals OKk bits D and temp new which represented the data readytrigger replacement width 119896 the embedding error 120575119894 and thesubstitution result 1199011015840119894 respectively234 D embModule TheD embmodule uses a comparatorto locate 120575119894 to its corresponding interval and process withassociated calculations according to (3) to produce the stegopixel 11990110158401015840119894 and transmits the stego pixel 11990110158401015840119894 to the Transmittermodule The output of the D emb module consists of twooutput signals ok new and new which represented the dataready trigger and the stego pixel 11990110158401015840119894 respectively235 Transmitter Module TheTransmitter module transfersthe stego pixel 11990110158401015840119894 into a bit stream and transmits theprocessing result to the PC via RS232

236 Work Time Module The Receiver module Stand bymodule Din Lsb sub module and D emb module keepsending RXD data ready ready ok and ok new signalsrespectively to the Work time module thorough their exe-cution period TheWork time module records the executiontime of each module and transfers the recorded data into abit stream After dealing with all pixels of the cover image


Table 1 PSNR of Lena by using OPAP [11]

PSNR (dB)Cover image 119896 OPAP LSB

Lena

1 511410 5114102 463699 4415193 407271 3792344 348062 317808

the Work time module will transmit the bit stream back toPC for analyzing the total execution time

3 Experimental Results

To illustrate the performance of the proposed system thefollowing conditions are consideredTheblock diagramof theoverall system is illustrated in Figure 3 where the FPGA isthe controller and the inputoutput interfaces Our FPGA isSpartan 3E Starter Kit by Xilinx programmed with Veriloglanguage to develop the proposed algorithmThe PC we usedin our experiments is a Core i5 44 (corethread) CPU with16G RAM The processed images are stored in a 7200 rpmhard disk

We test the proposed FPGA structure on a series ofcover images and secret messages Experimental results showthe difference between the proposed design and softwareimplementation to compare the correctness and efficiency Inthe first experiment we use ldquoLenardquo with size 256 times 256 pixelsto be the cover image as shown in Figure 4(a) The secretmessage is an image ldquoMandrilrdquo in size 128 times 256 pixels asshown in Figure 4(b)The stego images produced by softwareimplementation and by the proposed FPGA implementationare shown in Figures 4(c) and 4(d) respectively The secretmessages extracted by software implementation and by theproposed FPGA implementation are shown in Figures 4(e)and 4(f) respectivelyWeused the replacementwidth 119896 = 4 inFigures 4(c)ndash4(f) to compare the performance Since a pixelis usually represented by 8 bits a cover image can embed asecret image of its half size when the replacement width 119896 isset to 4

Another experiment is conducted to further examine theefficiency of the proposed method The cover image shownin Figure 5(a) is ldquoGirlrdquo in size 256 times 256 pixels and thesecret message shown in Figure 5(b) is an image ldquoRoomrdquo insize 128 times 256 pixels The stego images produced by softwareimplementation and by the proposed FPGA implementationare shown in Figures 5(c) and 5(d) respectively The secretmessages extracted by software implementation and by theproposed FPGA implementation are shown in Figures 5(e)and 5(f) respectively All pictures in Figures 5(c)ndash5(f) areobtained by setting 119896 = 4 Experimental results show thatboth the software andhardware implementations produce thesame stego image

Table 2 shows the execution time and speedup forembedding a secret image ldquoMandrilrdquo of size 128 times 256 pixelsto a cover image ldquoLenardquo of size 256 times 256 pixels by boththe software based method and the proposed FPGA schemeTable 3 shows the execution time and speedup for embedding

Table 2 Comparison of execution time and speedup for embeddingldquoLenardquo

Execution time (seconds) Speedup119896 software FPGA1 0116042 0013110 asymp8852 0120556 0013110 asymp9203 0143214 0013110 asymp10924 0199567 0013110 asymp1523Table 3 Comparison of execution time and speedup for embeddingldquoGirlrdquo

Execution time (seconds) Speedup119896 Software FPGA1 0116482 0013110 asymp8882 0122311 0013110 asymp9333 0145358 0013110 asymp11094 0204881 0013110 asymp1563

a secret image ldquoRoomrdquoof size 128times 256 pixels to a cover imageldquoGirlrdquo of size 256 times 256 pixels by both the software basedmethod and the proposed FPGA scheme Both tables showthat the execution time for software based method increaseswith the larger replacement width 119896 and the execution timefor FPGA scheme is almost the same with different values of119896 In both cases the speedup can be up to 15 when 119896 is setto 4 Experimental results show that the outputs of these twoimplementation methods are identical

The device utilization used in these two experiments isshown in Table 4 Less than 10 of the hardware devicesare used in the procedure of embedding a secret image ofsize 128 times 256 pixels to a cover image of size 256 times 256pixels Since the proposed scheme embeds secret image in apixel-by-pixel manner no extra hardware devices are neededeven in embedding image of larger size After observingthe fact that the proposed pixel-wised system used lessthan 10 of the hardware devices we further extend theproposed structure to a parallel structure which operatesto embed 10 pixels at the same time The parallel structureconsists of one Receiver module one Stand by module tenDin Lsb sub modules ten D emb modules one Transmittermodule and one Work time module The device utilizationof the 10-pixel parallel structure is shown in Table 4 Weuse larger size of images to test the efficiency of the parallelembedding structure Figure 6 shows the experimental resultof embedding the secret image ldquoFieldrdquo of size 512 times 1024 intothe cover image ldquoTulipsrdquo of size 1024 times 1024 Both the pixel-wise structure and the 10-pixel parallel structure produce thesame stego image The comparison of the execution time ofthe pixel-wise structure and the 10-pixel parallel structure isshown in Table 5

4 Conclusions

We have proposed a hardware circuit design to carry outthe image data hiding method on FPGA Through themechanism of the hardware design the data hiding process


(a) (b)

(c) (d)

(e) (f)

Figure 4 The experimental results of embedding ldquoMandrilrdquo in ldquoLenardquo (a) The cover image ldquoLenardquo of size 256 times 256 (b) secret imageldquoMandrilrdquo of size 128 times 256 (c) the stego image produced by software implementation (d) the stego image produced by the proposed FPGAdesign (e) the secret message extracted by software implementation (f) the secret message extracted by the proposed FPGA design

Table 4 Device utilization of the proposed FPGA design

System structure Pixel-wised structure 10-pixel parallel structureHardware devices Available Used Utilization Used UtilizationSlices 4650 270 5 1980 43Slice flip flop 9312 239 2 2390 204 input LUTs 9312 340 3 3400 30Bounded IOBs 232 4 1 40 10BUFGMUXs 24 2 8 20 80MUFT18X18SIOs 20 2 10 20 100


(a) (b)

(c) (d)

(e) (f)

Figure 5 The experimental results of embedding ldquoRoomrdquo in ldquoGirlrdquo (a) The cover image ldquoGirlrdquo of size 256 times 256 (b) secret image ldquoRoomrdquoof size 128 times 256 (c) the stego image produced by software implementation (d) the stego image produced by the proposed FPGA design (e)the secret message extracted by software implementation (f) the secret message extracted by the proposed FPGA design

Table 5 The execution time of the pixel-wise structure and the 10-pixel parallel structure

Cover image ldquoGirlrdquo of size 256 times 256 withsecret image ldquoRoomrdquo of size 128 times 256 Cover image ldquoTulipsrdquo of size 1024 times 1024 with

secret image ldquoFieldrdquo of size 512 times 1024Pixel-wisestructure

10-pixel parallelstructure Speedup

Pixel-wisestructure


Execution time(seconds)




119896 = 4 0013110 0001680 78 0210302 0025910 81


(a) (b) (c)

Figure 6The experimental results of embedding ldquoFieldrdquo in ldquoTulipsrdquo (a)The cover image ldquoTulipsrdquo of size 1024 times 1024 (b) secret image ldquoFieldrdquoof size 512 times 1024 (c) the stego image produced by both hardware structures

can be completed in fewer clock cycles to produce outcomemuch faster Experimental results show the effectivenessand correctness of the proposed scheme The speedup ofthe execution time is up to 15 for the proposed schemeover the software implementation scheme The proposedscheme embeds secret image in a pixel-by-pixel manner Theadvantage of this design is that there is no limitation on thesize of the secret message and cover image since no extrahardware devices are needed in embedding large-size imagesThe disadvantage of this design is that we cannot fully usethe hardware devices to speed up the embedding procedureMoreover we have extended the basic pixel-wise structure toa parallel structure which can fully use the hardware devicesto speed up the embedding process and embed several bits ofsecret message at the same time The maximum embeddingstorage is constrained by the size of the cover image and thereplacement width 119896 For an image of size119872times119873 and replace-ment width 119896 the maximum embedding storage will be119872times119873 times 119896 The limitation of the size of the cover image dependson the size of thememory to store the cover imageThe futureresearch includes applying the proposed prototype to developa fully automated embedded systemwhich is designed partic-ularly for data hiding and independent from PC

Conflicts of Interest

The authors declare that they have no conflicts of interest

References

[1] R Poornima and R J Iswarya ldquoAn overview of digital imagesteganographyrdquo International Journal of Computer Science ampEngineering Survey vol 4 no 1 pp 23ndash31 2013

[2] B Kaur A Kaur and J Singh ldquoSteganographic approach forhiding image in DCT domainrdquo International Journal of Advan-ces in Engineering amp Technology vol 1 no 3 pp 72ndash78 2011

[3] J Song Y Zhu and J Song ldquoSteganography an informationhiding method base on logistic map in DCT domainrdquoAdvancesin Information Sciences and Service Sciences (AISS) vol 4 no 22012

[4] Q Gu and T Gao ldquoA novel reversible watermarking algorithmbased onwavelet lifting schemerdquo ICIC Express Letters vol 3 no3 pp 397ndash402 2009

[5] A A Sheju and U L Kulkarni ldquoA secure skin tone based steg-anography using wavelet transformrdquo International Journal ofComputer eory and Engineering vol 3 no 1 pp 1793ndash82012011

[6] W Bender D Gruhl N Morimoto and A Lu ldquoTechniques fordata hidingrdquo IBM Systems Journal vol 35 no 3-4 pp 313ndash3351996

[7] X Zhang ldquoReversible data hiding with optimal value transferrdquoIEEE Transactions on Multimedia vol 15 no 2 pp 316ndash3252013

[8] R-Z Wang C-F Lin and J-C Lin ldquoImage hiding by optimalLSB substitution and genetic algorithmrdquo Pattern Recognitionvol 34 no 3 pp 671ndash683 2001

[9] C-K Chan and L M Cheng ldquoHiding data in images by simpleLSB substitutionrdquo Pattern Recognition vol 37 no 3 pp 469ndash474 2004

[10] W Wang J Ye T Wang and W Wang ldquoReversible data hid-ing scheme based on significant-bit-difference expansionrdquo IETImage Processing vol 11 no 11 pp 1002ndash1014 2017

[11] C-K Chan and L M Cheng ldquoImproved hiding data in imagesby optimal moderately-significant-bit replacementrdquo IEEE Elec-tronics Letters vol 37 no 16 pp 1017-1018 2001

[12] C-C Chang C-C Lin and Y-H Chen ldquoReversible data-embedding scheme using differences between original and pre-dicted pixel valuesrdquo IET Information Security vol 2 no 2 pp35ndash46 2008

[13] W-L Tai C-M Yeh and C-C Chang ldquoReversible data hidingbased on histogram modification of pixel differencesrdquo IEEETransactions on Circuits and Systems for Video Technology vol19 no 6 pp 906ndash910 2009

[14] P Tsai Y-C Hu and H-L Yeh ldquoReversible image hidingscheme using predictive coding and histogram shiftingrdquo SignalProcessing vol 89 no 6 pp 1129ndash1143 2009

[15] J-L Zhang Q Wu Y-P Ding et al ldquoTechniques for Designand Implementation of an FPGA-Specific Physical UnclonableFunctionrdquo Journal of Computer Science and Technology vol 31no 1 pp 124ndash136 2016

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and histogram modification (HM) methods [13 14] Thelossless compression based methods make use of statisticalredundancy of the cover image by performing lossless com-pression to create a spare space to accommodate additionalsecret dataTheDE-basedmethods divide an image into pixelpairs and embed secret data into expanded difference valuesTheHM-basedmethods shift several or the maximum pointsin histogram bins of the original image to reserve spare spacefor data embedding

Among image domain techniques the last-significant-bit(LSB) replacement method [8 9] which proposes to replacethe least 119896-bit of the cover images by the secret message isthe most straightforward algorithm for embedding messageinto images Since the LSB replacement method is easyto be detected and the secret message will be cracked bymalicious attackers more sophisticated methods such asthe optimal moderately significant-bit replacement method[11] or the differences between original and predicted pixelvalues method [12] have been proposed and gotten certaindegrees of success However most published techniques wereimplemented by using software schemes and few researchimplemented image steganography algorithms on hardwaremethods Usually hardware implementations are faster thansoftware implementations in that the hardware logic gatescan be processed in a parallel processing manner The higherthe complexity of the algorithm is the more advantages thehardware implementations can get

During recent years field programmable gate array(FPGA) has become the dominant form of programmablelogic [15] In comparison to previous programmable deviceslike programmable array logic (PAL) and complex pro-grammable logic devices (CPLD) FPGA can implement farlarger logic functions than the others In addition FPGAnot only supports sufficient logic arrays to implement morecomplicated systems and subsystems but also exploits theincreasing capacity of integrated circuits to provide designerswith reconfigurable logic arrays that can be programmed onapplication specific basis This drastically increases the flex-ibility in both the design process and the final manufactureby permitting a board-level design to perform many func-tions

Among all presented techniques optimal pixel adjust-ment process (OPAP) [11] is one of the well-defined algo-rithms for image data hiding Some other data hidingalgorithms may have more information capacity but theirhardware implementations will be much more complicatedIn this paper we proposed an OPAP design of circuitusing FPGA with the hardware description language VerilogHDL (Hardware Description Language) The FPGA boardXilinx Spartan-3E Starter Kit is applied to fulfill the imagedata hiding technique Using both software and hardwarebased schemes two image hiding experiments are fulfilledto compare the correctness and efficiency of the proposedhardware based FPGA method

The rest of the paper is organized as follows Section 2introduces the works about the LSB substitution method andOPAP technique The steps to implement image steganog-raphy by FPGA are also described in detail In Section 3experimental evaluation and discussion about data hiding

Secret message

Cover pixel

LSBsubstitution

Stego pixel110(2)

10000010(2)

10000110(2)

Figure 1 An example of the LSB substitution method

into images are presented to verify the enhancement of thehardware based image steganography technique

2 Image Steganography by FPGA

In this section we introduce the related works about the LSBmethod and the OPAP technique which are essential to thedata hiding process

21 Related Works

211 e LSB Substitution Method The LSB substitutionmethod is a simple and easy image steganography methodThis method replaces the 119896 least significant bits (LSB) bysecret messages in each pixel In a 256-level gray image thevalue of each pixel is usually represented in an 8-bit binaryform

119901 = (1198877 times 27 + 1198876 times 26 + sdot sdot sdot + 1198870 times 20) (1)

where 119901 is the value of a pixel and 119887119894 (0 le 119894 le 7) representsthe 8-bit binary As an example of the LSB substitutionmethod for a pixel value 130(10) secret message 110(2) andreplacement width 119896 = 3 we can try to embed the secretmessage into the pixel of image Therefore the original 8-bit binary value is 10000010 before the data hiding and itbecomes 10000110 after substituting the least 3 significant bitsby the secretmessage 110(2)Thepixel value has changed from130(10) to 134(10) and the difference of 4(10) will not be noticedby human observation Figure 1 illustrates this example of theLSB substitution method

212 OPAP Algorithm An OPAP method is proposed toenhance the image quality and security of the stego imageobtained by the LSB substitution method [11] Assume that119901119894 1199011015840119894 and 11990110158401015840119894 are the corresponding pixel values of the 119894thpixel in the cover image the stego image obtained by the LSBsubstitutionmethod and the refined stego image obtained byOPAP approach respectively Let 120575119894 = 1199011015840119894 minus 119901119894 be the embed-ding error between 119901119894 and 1199011015840119894 According to the embeddingprocess of the LSB substitution method 1199011015840119894 is obtained byreplacing the 119896 least significant bits of 119901119894 with 119896-bit secretmessage therefore the range of the embedding error is

minus2119896 lt 120575119894 lt 2119896 (2)

However the value of 120575119894 can be further segmented intothree intervals such that

Interval 1 2119896minus1 lt 120575119894 lt 2119896if 1199011015840119894 ge 2119896 then 11990110158401015840119894 = 1199011015840119894 minus 2119896else 11990110158401015840119894 = 1199011015840119894





(3)


MSE = ( 1119872 sdot 119873)119872sum119894=0

119873sum119895=0

(1199011015840119894119895 minus 119901119894119895)2


MSE)

(4)





Start





End




No

No







Recevier

RxD_data_ready

Stand_by

Ready

Din_Lsb_sub

FPGA

RxD_datak

Cover

Secret

dim

ok

D

temp_new

D_emb

ok_new

new

Transmitter

k_bits

Work_time

ce

Clocks

RS232data

RS232data











Lena

1 511410 5114102 463699 4415193 407271 3792344 348062 317808












4 Conclusions



(a) (b)

(c) (d)

(e) (f)





(a) (b)

(c) (d)

(e) (f)






Pixel-wisestructure






119896 = 4 0013110 0001680 78 0210302 0025910 81


(a) (b) (c)





References























Journal of












Journal of







Volume 2018






Volume 2018












(3)


MSE = ( 1119872 sdot 119873)119872sum119894=0

119873sum119895=0

(1199011015840119894119895 minus 119901119894119895)2


MSE)

(4)





Start





End




No

No







Recevier

RxD_data_ready

Stand_by

Ready

Din_Lsb_sub

FPGA

RxD_datak

Cover

Secret

dim

ok

D

temp_new

D_emb

ok_new

new

Transmitter

k_bits

Work_time

ce

Clocks

RS232data

RS232data











Lena

1 511410 5114102 463699 4415193 407271 3792344 348062 317808












4 Conclusions



(a) (b)

(c) (d)

(e) (f)





(a) (b)

(c) (d)

(e) (f)






Pixel-wisestructure






119896 = 4 0013110 0001680 78 0210302 0025910 81


(a) (b) (c)





References























Journal of












Journal of







Volume 2018






Volume 2018









Recevier

RxD_data_ready

Stand_by

Ready

Din_Lsb_sub

FPGA

RxD_datak

Cover

Secret

dim

ok

D

temp_new

D_emb

ok_new

new

Transmitter

k_bits

Work_time

ce

Clocks

RS232data

RS232data











Lena

1 511410 5114102 463699 4415193 407271 3792344 348062 317808












4 Conclusions



(a) (b)

(c) (d)

(e) (f)





(a) (b)

(c) (d)

(e) (f)






Pixel-wisestructure






119896 = 4 0013110 0001680 78 0210302 0025910 81


(a) (b) (c)





References























Journal of












Journal of







Volume 2018






Volume 2018











Lena

1 511410 5114102 463699 4415193 407271 3792344 348062 317808












4 Conclusions



(a) (b)

(c) (d)

(e) (f)





(a) (b)

(c) (d)

(e) (f)






Pixel-wisestructure






119896 = 4 0013110 0001680 78 0210302 0025910 81


(a) (b) (c)





References























Journal of












Journal of







Volume 2018






Volume 2018









(a) (b)

(c) (d)

(e) (f)





(a) (b)

(c) (d)

(e) (f)






Pixel-wisestructure






119896 = 4 0013110 0001680 78 0210302 0025910 81


(a) (b) (c)





References























Journal of












Journal of







Volume 2018






Volume 2018









(a) (b)

(c) (d)

(e) (f)






Pixel-wisestructure






119896 = 4 0013110 0001680 78 0210302 0025910 81


(a) (b) (c)





References























Journal of












Journal of







Volume 2018






Volume 2018









(a) (b) (c)





References























Journal of












Journal of







Volume 2018






Volume 2018















Journal of












Journal of







Volume 2018






Volume 2018








embedded fpga design for optimal pixel adjustment process...

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