electronics for telecommunications complete time-domain behavioral model of analog to digital...

Electronics for TelecommunicationsElectronics for Telecommunications

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK® for advanced RF

receiver architectures

POLITECNICO DI BARI

F.CannoneF.Cannone, G.Avitabile, G. Coviello,D. Cascella

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK® for advanced RF receiver architectures

Electronics for Telecommunications

POLITECNICO DI BARI

F. Cannone, G. Avitabile, G. Coviello, D. Cascella

-Introduction

-Proposed Model

-Simulations

- Conclusions

Introduction

Proposed Model

Simulations

Conclusions

OUTLINEOUTLINE



POLITECNICO DI BARI


1. Introduction 2. Proposed model 3. Simulations 4. Conclusions

SHA ADC

DATA ACQUISITION SYSTEM

MotivationMotivation

•Complete study at system level

•Take a choice about technology (SiGe, GaAS, etc), and circuital topology

•Tool of system level analysis after that the design choices have been made

• To drive the choice of the suitable RF architectures (SDR, direct RF Rx, etc.)

• To consider all the non idealities = to address the concerns limiting the performance

• Standard CAD models are lacking in utility (they do not model all the sources of errors)



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-Introduction

-Proposed Model

-Simulations

- Conclusions

Proposed Model

OUTLINEOUTLINE



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1. Introduction 3. Simulations 4. Conclusions2. Proposed model

Developed in SIMULINK® = advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems.

Model description Model description

The architecture of the model•Model of SHA;•Model of ADC (this work);•Model of real clock (with jitter)

The test benchStarting from the time-based simulation results, a set of Matlab files compute the typical FOM (SFDR, SNR, SNDR, ENOB etc.)



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Sample and Hold and real clock behavioral modelsSample and Hold and real clock behavioral models

These blocks consider the following non idealities:

•offset voltage; •gain error and gain linearity error; •slew rate and acquisition time; •aperture time, •effective aperture delay time, •aperture jitter and clock jitter; •hold mode settling time and pedestal; •droop rate; •input feedthrough

[5: Avitabile et al, MELECON 2008]



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The architecture of the ADC model The architecture of the ADC model

• The core of the ADC, it performs the analog to digital conversion, modeling both the linear and the non linear errors associated with such operation

Both based on Matlab files adopted by using the block “Embedded Matlab function”

• It models the non linear behavior of the ADC circuitry

1° block

2° block



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The non linear behavior of the ADC circuitry The non linear behavior of the ADC circuitry

• It is important when the signal is close to VFS (real advanced ADC for SDR Rx)

• The non linear behavior is modeled by using the power series

• The inputs are the level of the first 5 harmonics. -> the Matlab file computes the first 5 coefficients

y=a1*u+a2*u2+a3*u3+a4*u4+a5*u5

1. to emulate a real ADC using the values from the simulations (i.e. Spectre, HB) or from the measurements

2. to evaluate the sensitivity to this feature of the overall ADC performance (i.e. the loss of resolution measured in terms of ENOB due to the large signal distortion)

Two ways to use the model are possible:



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The ADC core (1/2) The ADC core (1/2)

It emulates a generic ADC: n and the FSR are variables, the user can define its own ADC

It models the offset error and allows the user to set a parameter called DNL rms

The DNL rms can be used to model the level of quality of the ADC. It is also possible to use the vector of the measured or simulated real thresholds.

Two ways to use the model are possible:

1. to emulate a real ADC providing offset and the vector of thresholds or the DNL rms

2. to study the sensitivity of the conversion system to these errors



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The ADC core (2/2) The ADC core (2/2)

The outputs of the model are:

1. the quantized signal;2. the codes expressed in decimal

notation;3. the overall conversion error

The core of the Matlab file embedded is composed by the following instructions:

LSB=FSRpp/(2^n);C_noise=DNL;offset=os;if u<-FSR, Analog=-FSR+LSB/2; elseif u>FSR, Analog=FSR-LSB/2; else Analog=u;end;

AnalogShifted=Analog+FSR;R= AnalogShifted/LSB;Cod=floor(R)+1;

V_th=thresholds;eml.extrinsic('wgn')DG=g;for k=1:Max V_th(k)=-FSR+k*LSB+DG(k)*(C_noise*LSB);endif (Analog-offset)<V_th(1), Y=-FSR+LSB/2; elseif (Analog-offset)>V_th(Max),

Y=FSR-LSB/2; elseif (Analog-offset)<V_th(Cod-1), Y=-FSR+(Cod-1)*LSB-LSB/2; elseif (Analog-offset)<V_th(Cod),Y=-FSR+Cod*LSB-LSB/2; else Y=-FSR+(Cod+1)*LSB-LSB/2;endCODICI=(Y+FSR-LSB/2)/LSB+1;Code = CODICI;Out=Y;eq=u-Y;end



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-Introduction

-Proposed Model

-Simulations

- Conclusions

Simulations

OUTLINEOUTLINE



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1. Introduction 4. Conclusions2. Proposed model 3. Simulations

The possible uses • to study the impact of given ADC on the Rx• to make the system level design of the A/D block setting the acceptable level of each non ideality

The description of the test bench The description of the test bench

The inputsall the non-ideal parameters derived from a given ADC (a datasheet, measurements or transistor level simulations) or need to be determined before to start the design at circuit level

The ouputsthe FOMs: SFDR, SNR, SNDR, ENOB, INL,DNL, etc.



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The description of the testsThe description of the testsTo validate the proposed model different simulations have been performed and we have verified that:

1. It emulates an ideal conversion block if all the parameters are set with the ideal values

2. There is a good agreement among the simulations and the expected results modifying separately each parameter taking all the other ones at the ideal values

3. It is able to emulate the behavior of a generic SHA [5] (keeping ideal the ADC part)

4. It is able to emulate the behavior of a generic ADC [this work] (keeping ideal the SHA part)



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Some simulation results (1/2)Some simulation results (1/2)

• We have used as inputs the parameters reported in [6]: 2nd harmonic=-49.1dB, 3rd harmonic=-43.7dB and DNL=0.5 LSB

simulated ADC output power spectrum reported ADC output power spectrum [6]

• We have achieved a good agreement!



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[6] [Proposed model]Fin=202MHz, Fclk=600MHz

SNDR = 40.0 dB

Fin=202MHz, Fclk=600MHz

SNDR = 40.021 dB


SFDR = 44.0 dB


SFDR = 41.68 dB

Summary of the comparison

Some simulation results (2/2)Some simulation results (2/2)

The proposed model can be used to test a generic ADC converter inserted in a receiver architecture!

It is possible to use it in the second mode of operations, the system level design!



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-Introduction

-Proposed Model

-Simulations

- ConclusionsConclusions

OUTLINEOUTLINE



POLITECNICO DI BARI


1. Introduction 2. Proposed model 4. Conclusions3. Experimental results

• A complete time-domain behavioral model of A to D converter based on its main

characteristics has been shown

• to consider the FOM of an ADC, like SNR, ENOB and SFDR a complete test bench

has been also developed and presented

• The proposed model is a complete tool in the system level study for addressing

the design of the high speed converter in advanced architectures like SDR or

undersampled direct RF Rx

• We have finally used the proposed model to determine, at the system level, the

reasonable SHA and ADC blocks to be used in a SDR receiver that we are designing

Conclusions and future worksConclusions and future works

electronics for telecommunications complete time-domain behavioral model of analog to digital...

Documents

model sample

model description

proposed model simulations

model outline slide

model of real clock

digital converter block

acquisition time aperture

cascella slide