Electric Circuits

ChalmersCommunications Systems Group,

Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

Hani Mehrpouyan,

Department of Electrical and Computer Engineering, Boise State University

Lecture 4 (Nodal Analysis)

Electric Circuits

ChalmersCommunications Systems Group,

Signals and Systems,Chalmers University of Technology,

Swedenc2010

August 20, 2015

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2015 1 1

Electric Circuits

ChalmersCommunications Systems Group,

Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

2

Overview• With Ohm’s and Kirchhoff’s law established, they may now be

applied to circuit analysis. • Two techniques will be presented in this chapter:

– Nodal analysis, which is based on Kichhoff current law (KCL)

– Mesh analysis, which is based on Kichhoff voltage law (KVL)

• Any linear circuit can be analyzed using these two techniques. • The analysis will result in a set of simultaneous equations

which may be solved by Cramer’s rule or computationally (using MATLAB for example)

Electric Circuits

ChalmersCommunications Systems Group,

Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

3

Nodal Analysis• If instead of focusing on the voltages of the circuit elements, one

looks at the voltages at the nodes of the circuit, the number of simultaneous equations to solve for can be reduced.

• Given a circuit with n nodes, without voltage sources, the nodal analysis is accomplished via three steps: 1. Select a node as the reference node. Assign voltages v1,v2,…vn to

the remaining n-1 nodes, voltages are relative to the reference node.

2. Apply KCL to each of the n-1 non-reference nodes. Use Ohm’s law to express the branch currents in terms of node voltages

3. Solve the resulting n-1 simultaneous equations to obtain the unknown node voltages.

• The reference, or datum, node is commonly referred to as the ground since its voltage is by default zero.

Electric Circuits

ChalmersCommunications Systems Group,

Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

4

Nodal Analysis

since it is assumed to have zero potential. A reference node is indicatedby any of the three symbols in Fig. 3.1. The type of ground in Fig. 3.1(c)is called a chassis ground and is used in devices where the case, enclo-sure, or chassis acts as a reference point for all circuits. When thepotential of the earth is used as reference, we use the earth ground inFig. 3.1(a) or (b). We shall always use the symbol in Fig. 3.1(b).

Once we have selected a reference node, we assign voltage desig-nations to nonreference nodes. Consider, for example, the circuit inFig. 3.2(a). Node 0 is the reference node while nodes 1 and2 are assigned voltages and respectively. Keep in mind that thenode voltages are defined with respect to the reference node. As illus-trated in Fig. 3.2(a), each node voltage is the voltage rise from the ref-erence node to the corresponding nonreference node or simply thevoltage of that node with respect to the reference node.

As the second step, we apply KCL to each nonreference node inthe circuit. To avoid putting too much information on the same circuit,the circuit in Fig. 3.2(a) is redrawn in Fig. 3.2(b), where we now add

and as the currents through resistors and respec-tively. At node 1, applying KCL gives

(3.1)

At node 2,

(3.2)

We now apply Ohm’s law to express the unknown currents andin terms of node voltages. The key idea to bear in mind is that, since

resistance is a passive element, by the passive sign convention, currentmust always flow from a higher potential to a lower potential.

i3i1, i2,

I2 ! i2 " i3

I1 " I2 ! i1 ! i2

R3,R1, R2,i3i1, i2,

v2,v1

(v " 0),

3.2 Nodal Analysis 83

The number of nonreference nodes isequal to the number of independentequations that we will derive.

Figure 3.1Common symbols for indicating areference node, (a) common ground,(b) ground, (c) chassis ground.

(a) (b) (c)

Figure 3.2Typical circuit for nodal analysis.

Current flows from a higher potential to a lower potential in a resistor.

We can express this principle as

(3.3)

Note that this principle is in agreement with the way we defined resist-ance in Chapter 2 (see Fig. 2.1). With this in mind, we obtain fromFig. 3.2(b),

(3.4)

Substituting Eq. (3.4) in Eqs. (3.1) and (3.2) results, respectively, in

(3.5)

(3.6)I2 !v1 # v2

R2"

v2

R3

I1 " I2 !v1

R1!

v1 # v2

R2

i3 "v2 # 0

R3 or i3 " G3v2

i2 "v1 # v2

R2 or i2 " G2 (v1 # v2)

i1 "v1 # 0

R1 or i1 " G1v1

i "vhigher # vlower

R

(a)

(b)

1 2

v1

i1

i2 i2

i3

v2

I2

0

R3v2

+

−

R3

R1v1

+

−

R1I1

I2

R2

R2

I1

ale80571_ch03_081_126.qxd 11/30/11 4:10 PM Page 83

since it is assumed to have zero potential. A reference node is indicatedby any of the three symbols in Fig. 3.1. The type of ground in Fig. 3.1(c)is called a chassis ground and is used in devices where the case, enclo-sure, or chassis acts as a reference point for all circuits. When thepotential of the earth is used as reference, we use the earth ground inFig. 3.1(a) or (b). We shall always use the symbol in Fig. 3.1(b).

Once we have selected a reference node, we assign voltage desig-nations to nonreference nodes. Consider, for example, the circuit inFig. 3.2(a). Node 0 is the reference node while nodes 1 and2 are assigned voltages and respectively. Keep in mind that thenode voltages are defined with respect to the reference node. As illus-trated in Fig. 3.2(a), each node voltage is the voltage rise from the ref-erence node to the corresponding nonreference node or simply thevoltage of that node with respect to the reference node.

As the second step, we apply KCL to each nonreference node inthe circuit. To avoid putting too much information on the same circuit,the circuit in Fig. 3.2(a) is redrawn in Fig. 3.2(b), where we now add

and as the currents through resistors and respec-tively. At node 1, applying KCL gives

(3.1)

At node 2,

(3.2)

We now apply Ohm’s law to express the unknown currents andin terms of node voltages. The key idea to bear in mind is that, since

resistance is a passive element, by the passive sign convention, currentmust always flow from a higher potential to a lower potential.

i3i1, i2,

I2 ! i2 " i3

I1 " I2 ! i1 ! i2

R3,R1, R2,i3i1, i2,

v2,v1

(v " 0),

3.2 Nodal Analysis 83

The number of nonreference nodes isequal to the number of independentequations that we will derive.

Figure 3.1Common symbols for indicating areference node, (a) common ground,(b) ground, (c) chassis ground.

(a) (b) (c)

Figure 3.2Typical circuit for nodal analysis.

Current flows from a higher potential to a lower potential in a resistor.

We can express this principle as

(3.3)

Note that this principle is in agreement with the way we defined resist-ance in Chapter 2 (see Fig. 2.1). With this in mind, we obtain fromFig. 3.2(b),

(3.4)

Substituting Eq. (3.4) in Eqs. (3.1) and (3.2) results, respectively, in

(3.5)

(3.6)I2 !v1 # v2

R2"

v2

R3

I1 " I2 !v1

R1!

v1 # v2

R2

i3 "v2 # 0

R3 or i3 " G3v2

i2 "v1 # v2

R2 or i2 " G2 (v1 # v2)

i1 "v1 # 0

R1 or i1 " G1v1

i "vhigher # vlower

R

(a)

(b)

1 2

v1

i1

i2 i2

i3

v2

I2

0

R3v2

+

−

R3

R1v1

+

−

R1I1

I2

R2

R2

I1

ale80571_ch03_081_126.qxd 11/30/11 4:10 PM Page 83

since it is assumed to have zero potential. A reference node is indicatedby any of the three symbols in Fig. 3.1. The type of ground in Fig. 3.1(c)is called a chassis ground and is used in devices where the case, enclo-sure, or chassis acts as a reference point for all circuits. When thepotential of the earth is used as reference, we use the earth ground inFig. 3.1(a) or (b). We shall always use the symbol in Fig. 3.1(b).

Once we have selected a reference node, we assign voltage desig-nations to nonreference nodes. Consider, for example, the circuit inFig. 3.2(a). Node 0 is the reference node while nodes 1 and2 are assigned voltages and respectively. Keep in mind that thenode voltages are defined with respect to the reference node. As illus-trated in Fig. 3.2(a), each node voltage is the voltage rise from the ref-erence node to the corresponding nonreference node or simply thevoltage of that node with respect to the reference node.

As the second step, we apply KCL to each nonreference node inthe circuit. To avoid putting too much information on the same circuit,the circuit in Fig. 3.2(a) is redrawn in Fig. 3.2(b), where we now add

and as the currents through resistors and respec-tively. At node 1, applying KCL gives

(3.1)

At node 2,

(3.2)

We now apply Ohm’s law to express the unknown currents andin terms of node voltages. The key idea to bear in mind is that, since

resistance is a passive element, by the passive sign convention, currentmust always flow from a higher potential to a lower potential.

i3i1, i2,

I2 ! i2 " i3

I1 " I2 ! i1 ! i2

R3,R1, R2,i3i1, i2,

v2,v1

(v " 0),

3.2 Nodal Analysis 83

The number of nonreference nodes isequal to the number of independentequations that we will derive.

Figure 3.1Common symbols for indicating areference node, (a) common ground,(b) ground, (c) chassis ground.

(a) (b) (c)

Figure 3.2Typical circuit for nodal analysis.

Current flows from a higher potential to a lower potential in a resistor.

We can express this principle as

(3.3)

Note that this principle is in agreement with the way we defined resist-ance in Chapter 2 (see Fig. 2.1). With this in mind, we obtain fromFig. 3.2(b),

(3.4)

Substituting Eq. (3.4) in Eqs. (3.1) and (3.2) results, respectively, in

(3.5)

(3.6)I2 !v1 # v2

R2"

v2

R3

I1 " I2 !v1

R1!

v1 # v2

R2

i3 "v2 # 0

R3 or i3 " G3v2

i2 "v1 # v2

R2 or i2 " G2 (v1 # v2)

i1 "v1 # 0

R1 or i1 " G1v1

i "vhigher # vlower

R

(a)

(b)

1 2

v1

i1

i2 i2

i3

v2

I2

0

R3v2

+

−

R3

R1v1

+

−

R1I1

I2

R2

R2

I1

ale80571_ch03_081_126.qxd 11/30/11 4:10 PM Page 83

since it is assumed to have zero potential. A reference node is indicatedby any of the three symbols in Fig. 3.1. The type of ground in Fig. 3.1(c)is called a chassis ground and is used in devices where the case, enclo-sure, or chassis acts as a reference point for all circuits. When thepotential of the earth is used as reference, we use the earth ground inFig. 3.1(a) or (b). We shall always use the symbol in Fig. 3.1(b).

Once we have selected a reference node, we assign voltage desig-nations to nonreference nodes. Consider, for example, the circuit inFig. 3.2(a). Node 0 is the reference node while nodes 1 and2 are assigned voltages and respectively. Keep in mind that thenode voltages are defined with respect to the reference node. As illus-trated in Fig. 3.2(a), each node voltage is the voltage rise from the ref-erence node to the corresponding nonreference node or simply thevoltage of that node with respect to the reference node.

As the second step, we apply KCL to each nonreference node inthe circuit. To avoid putting too much information on the same circuit,the circuit in Fig. 3.2(a) is redrawn in Fig. 3.2(b), where we now add

and as the currents through resistors and respec-tively. At node 1, applying KCL gives

(3.1)

At node 2,

(3.2)

We now apply Ohm’s law to express the unknown currents andin terms of node voltages. The key idea to bear in mind is that, since

resistance is a passive element, by the passive sign convention, currentmust always flow from a higher potential to a lower potential.

i3i1, i2,

I2 ! i2 " i3

I1 " I2 ! i1 ! i2

R3,R1, R2,i3i1, i2,

v2,v1

(v " 0),

3.2 Nodal Analysis 83

The number of nonreference nodes isequal to the number of independentequations that we will derive.

Figure 3.1Common symbols for indicating areference node, (a) common ground,(b) ground, (c) chassis ground.

(a) (b) (c)

Figure 3.2Typical circuit for nodal analysis.

Current flows from a higher potential to a lower potential in a resistor.

We can express this principle as

(3.3)

Note that this principle is in agreement with the way we defined resist-ance in Chapter 2 (see Fig. 2.1). With this in mind, we obtain fromFig. 3.2(b),

(3.4)

Substituting Eq. (3.4) in Eqs. (3.1) and (3.2) results, respectively, in

(3.5)

(3.6)I2 !v1 # v2

R2"

v2

R3

I1 " I2 !v1

R1!

v1 # v2

R2

i3 "v2 # 0

R3 or i3 " G3v2

i2 "v1 # v2

R2 or i2 " G2 (v1 # v2)

i1 "v1 # 0

R1 or i1 " G1v1

i "vhigher # vlower

R

(a)

(b)

1 2

v1

i1

i2 i2

i3

v2

I2

0

R3v2

+

−

R3

R1v1

+

−

R1I1

I2

R2

R2

I1

ale80571_ch03_081_126.qxd 11/30/11 4:10 PM Page 83

since it is assumed to have zero potential. A reference node is indicatedby any of the three symbols in Fig. 3.1. The type of ground in Fig. 3.1(c)is called a chassis ground and is used in devices where the case, enclo-sure, or chassis acts as a reference point for all circuits. When thepotential of the earth is used as reference, we use the earth ground inFig. 3.1(a) or (b). We shall always use the symbol in Fig. 3.1(b).

Once we have selected a reference node, we assign voltage desig-nations to nonreference nodes. Consider, for example, the circuit inFig. 3.2(a). Node 0 is the reference node while nodes 1 and2 are assigned voltages and respectively. Keep in mind that thenode voltages are defined with respect to the reference node. As illus-trated in Fig. 3.2(a), each node voltage is the voltage rise from the ref-erence node to the corresponding nonreference node or simply thevoltage of that node with respect to the reference node.

As the second step, we apply KCL to each nonreference node inthe circuit. To avoid putting too much information on the same circuit,the circuit in Fig. 3.2(a) is redrawn in Fig. 3.2(b), where we now add

and as the currents through resistors and respec-tively. At node 1, applying KCL gives

(3.1)

At node 2,

(3.2)

We now apply Ohm’s law to express the unknown currents andin terms of node voltages. The key idea to bear in mind is that, since

resistance is a passive element, by the passive sign convention, currentmust always flow from a higher potential to a lower potential.

i3i1, i2,

I2 ! i2 " i3

I1 " I2 ! i1 ! i2

R3,R1, R2,i3i1, i2,

v2,v1

(v " 0),

3.2 Nodal Analysis 83

The number of nonreference nodes isequal to the number of independentequations that we will derive.

Figure 3.1Common symbols for indicating areference node, (a) common ground,(b) ground, (c) chassis ground.

(a) (b) (c)

Figure 3.2Typical circuit for nodal analysis.

Current flows from a higher potential to a lower potential in a resistor.

We can express this principle as

(3.3)

Note that this principle is in agreement with the way we defined resist-ance in Chapter 2 (see Fig. 2.1). With this in mind, we obtain fromFig. 3.2(b),

(3.4)

Substituting Eq. (3.4) in Eqs. (3.1) and (3.2) results, respectively, in

(3.5)

(3.6)I2 !v1 # v2

R2"

v2

R3

I1 " I2 !v1

R1!

v1 # v2

R2

i3 "v2 # 0

R3 or i3 " G3v2

i2 "v1 # v2

R2 or i2 " G2 (v1 # v2)

i1 "v1 # 0

R1 or i1 " G1v1

i "vhigher # vlower

R

(a)

(b)

1 2

v1

i1

i2 i2

i3

v2

I2

0

R3v2

+

−

R3

R1v1

+

−

R1I1

I2

R2

R2

I1

ale80571_ch03_081_126.qxd 11/30/11 4:10 PM Page 83

Electric Circuits

ChalmersCommunications Systems Group,

Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

5

Electric Circuits

ChalmersCommunications Systems Group,

Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

6

Electric Circuits

ChalmersCommunications Systems Group,

Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

7

Electric Circuits

ChalmersCommunications Systems Group,

Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

8

Including voltage sources• Depending on what nodes the

source is connected to, the approach varies

• Between the reference node and a non-reference mode: – Set the voltage at the non-

reference node to the voltage of the source

– In the example circuit v1=10V

• Between two non-reference nodes – The two nodes form a supernode.

Electric Circuits

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Signals and Systems,Chalmers University of Technology,

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Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

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Supernode• A supernode is formed by enclosing a voltage source (dependent

or independent) connected between two non-reference nodes and any elements connected in parallel with it.

• Why? – Nodal analysis requires applying KCL – The current through the voltage source cannot be known in advance

(Ohm’s law does not apply) – By lumping the nodes together, the current balance can still be

described • In the example circuit node 2 and 3 form a supernode • The current balance would be: • Or this can be expressed as:

3241 iiii +=+

60

80

42323121 −

+−

=−

+− vvvvvv

Electric Circuits

ChalmersCommunications Systems Group,

Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

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Supernode

A supernode is formed by enclosing a (dependent or independent)voltage source connected between two nonreference nodes and anyelements connected in parallel with it.

form a generalized node or supernode; we apply both KCL and KVLto determine the node voltages.

3.3 Nodal Analysis with Voltage Sources 89

Figure 3.7A circuit with a supernode.

10 V

5 V

4 Ω

8 Ω 6 Ω

2 Ωv1 v3

v2

i3

i1

i2

i4

Supernode

+−

+ −

A supernode may be regarded as aclosed surface enclosing the voltagesource and its two nodes.

In Fig. 3.7, nodes 2 and 3 form a supernode. (We could have morethan two nodes forming a single supernode. For example, see the cir-cuit in Fig. 3.14.) We analyze a circuit with supernodes using thesame three steps mentioned in the previous section except that thesupernodes are treated differently. Why? Because an essential com-ponent of nodal analysis is applying KCL, which requires knowingthe current through each element. There is no way of knowing thecurrent through a voltage source in advance. However, KCL mustbe satisfied at a supernode like any other node. Hence, at the super-node in Fig. 3.7,

(3.11a)

or

(3.11b)

To apply Kirchhoff’s voltage law to the supernode in Fig. 3.7, weredraw the circuit as shown in Fig. 3.8. Going around the loop in theclockwise direction gives

(3.12)

From Eqs. (3.10), (3.11b), and (3.12), we obtain the node voltages.Note the following properties of a supernode:

1. The voltage source inside the supernode provides a constraintequation needed to solve for the node voltages.

2. A supernode has no voltage of its own.3. A supernode requires the application of both KCL and KVL.

!v2 " 5 " v3 # 0 1 v2 ! v3 # 5

v1 ! v2

2"

v1 ! v3

4#

v2 ! 08

"v3 ! 0

6

i1 " i4 # i2 " i3

+ −

v2 v3

5 V

+ +

− −

Figure 3.8Applying KVL to a supernode.

ale80571_ch03_081_126.qxd 11/30/11 4:10 PM Page 89

• We now have one equation and 2 unknowns, i.e., v2 and v3.

• Hence, we need another equation to solve for all the unknowns.

• We use KVL around the loop that consists of the voltage source (see the figure). This will give us another equation.

• This equation is

5+v3-v2=0

• Now we have enough equations to solve for the unknown.

Electric Circuits

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Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

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Electric Circuits

ChalmersCommunications Systems Group,

Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

12

Electric Circuits

ChalmersCommunications Systems Group,

Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

13

Electric Circuits

ChalmersCommunications Systems Group,

Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

14

Electric Circuits

ChalmersCommunications Systems Group,

Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

15

Electric Circuits

ChalmersCommunications Systems Group,

Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

16

Electric Circuits

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Signals and Systems,Chalmers University of Technology,

Swedenc2010

January 6, 2017

Hani Mehrpouyan (hani.mehr@ieee.org) Boise State c2017 1

Signals and SystemsBoise State University

17