elct 201: digital logic design - german university in cairo

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ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, [email protected] Dr. Eng. Wassim Alexan, [email protected] Lecture 8 ذو Ψ§Ω„Ψ­Ψ¬Ψ©1438 Ω‡Ω€Ω€Winter 2017 Following the slides of Dr. Ahmed H. Madian

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Page 1: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, [email protected]

Dr. Eng. Wassim Alexan, [email protected]

Lecture 8

Ω‡Ω€Ω€ 1438ذو Ψ§Ω„Ψ­Ψ¬Ψ©

Winter 2017

Following the slides of Dr. Ahmed H. Madian

Page 2: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

COURSE OUTLINE

1. Introduction

2. Gate-Level Minimization

3. Combinational Logic

4. Synchronous Sequential Logic

5. Registers and Counters

6. Memories and Programmable Logic

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Page 3: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

LECTURE OUTLINE

β€’ Registers

β€’ Structure and Definition

β€’ Serial Registers

β€’ Parallel Registers

β€’ Serial Adder

β€’ Universal Shift Register

β€’ Universal Shift Register: Applications

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Page 4: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

REGISTERS

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β€’ A register is a memory element that can be used to store more than a single bit of information

β€’ A register is made up of several flip-flops with common control signals that control the movement of data to and from the registers

β€’ An 𝑛-bit register consists of 𝑛 flip-flops and is capable of storing an 𝑛-bit word

β€’ The main operations on a register are the same as for any storage element, namely: β€’ load or store: input new data into the register

β€’ Read: retrieve the stored data in the register

Page 5: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

SERIAL I/P AND O/P REGISTERS

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πΆπ‘™π‘˜

π‘†π‘’π‘Ÿπ‘–π‘Žπ‘™ 𝑖𝑛𝑝𝑒𝑑

π‘†π‘’π‘Ÿπ‘–π‘Žπ‘™ π‘œπ‘’π‘‘π‘π‘’π‘‘

𝐼𝑛 𝑄1 𝑄2 𝑄3 𝑄4

= π‘œπ‘’π‘‘

𝑑0 1 0 0 0 0

𝑑1 0 1 0 0 0

𝑑2 1 0 1 0 0

𝑑3 1 1 0 1 0

𝑑4 1 1 1 0 1

𝑑5 0 1 1 1 0

𝑑6 0 0 1 1 1

𝑑7 0 0 0 1 1

𝑄1 𝑄2 𝑄3

Page 6: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

PARALLEL I/P AND O/P REGISTERS

6 πΆπ‘™π‘˜ πΆπ‘™π‘’π‘Žπ‘Ÿ

𝐼3

𝐼2

𝐼1

𝐼0

𝐴3

𝐴2

𝐴1

𝐴0

But what if we do not want to load new

data with every clock cycle? What if we

want to keep the same data in the

register?

β€’ With every positive edge of the clock,

new data is loaded into the register, in a parallel fashion

Page 7: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

PARALLEL I/P AND O/P REGISTERS

7 πΆπ‘™π‘˜

πΏπ‘œπ‘Žπ‘‘

𝐼3

𝐼2

𝐼1

𝐼0

𝐴3

𝐴2

𝐴1

𝐴0

This design allows us

to:

1. Either load new

data bits into the

register

2. Or keep the old

outputs, by

recirculating them

back into the FF

inputs

Page 8: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

SERIAL ADDITION USING REGISTERS

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πΆπ‘™π‘˜

π‘†β„Žπ‘–π‘“π‘‘ π‘π‘œπ‘›π‘‘π‘Ÿπ‘œπ‘™

π‘†π‘’π‘Ÿπ‘–π‘Žπ‘™ 𝑖𝑛𝑝𝑒𝑑

πΆπ‘™π‘’π‘Žπ‘Ÿ

Circuit implementation

using a FA and a 𝐷 FF

Page 9: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

SERIAL ADDITION USING REGISTERS

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β€’ Initially, register 𝐴 holds the augend and register 𝐡 holds the addend, while the carry FF is cleared to 0

β€’ The outputs 𝑆𝑂 of 𝐴 and 𝐡 provide a pair of significant bits for the full adder at π‘₯ and 𝑦. Output 𝑄 of the FF provides the input carry at 𝑧

β€’ The π‘ β„Žπ‘–π‘“π‘‘ π‘π‘œπ‘›π‘‘π‘Ÿπ‘œπ‘™ enables both registers and the carry FF, so that at the next clock pulse, both registers are shifted once to the right, the sum bit from 𝑆 enters the left-most FF of 𝐴, and the output carry is transferred into FF 𝑄

β€’ The π‘ β„Žπ‘–π‘“π‘‘ π‘π‘œπ‘›π‘‘π‘Ÿπ‘œπ‘™ enables the registers for a number of clock pulses equal to the number of bits in the registers

β€’ For each succeeding clock pulse, a new sum bit is transferred to 𝐴, a new carry is transferred to 𝑄, and both registers are shifted once to the right

β€’ This process continues until the π‘ β„Žπ‘–π‘“π‘‘ π‘π‘œπ‘›π‘‘π‘Ÿπ‘œπ‘™ is disabled

Page 10: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

SERIAL ADDITION USING REGISTERS

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β€’ Thus, the addition is accomplished by passing each pair of bits together with the previous carry through a single full adder circuit and transferring the sum, one bit at a time, into register 𝐴

β€’ Initially, register 𝐴 and the carry FF are cleared to 0, and then the first number is added from 𝐡

β€’ While 𝐡 is shifted through the full adder, a second number is transferred to it through its serial input

β€’ The second number is then added to the contents of register 𝐴 while a third number is transferred to serially into register 𝐡

β€’ This can be repeated to perform the addition of 2, 3 or more 4-bit numbers and accumulate their sum in register 𝐴 (assuming that register 𝐴 is built of 4 FFs only)

Page 11: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

SERIAL ADDITION USING REGISTERS

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πΆπ‘™π‘˜

π‘†β„Žπ‘–π‘“π‘‘ π‘π‘œπ‘›π‘‘π‘Ÿπ‘œπ‘™

π‘†π‘’π‘Ÿπ‘–π‘Žπ‘™ 𝑖𝑛𝑝𝑒𝑑

πΆπ‘™π‘’π‘Žπ‘Ÿ

Circuit implementation using a 𝐽𝐾 FF

𝐽𝑄 = π‘₯𝑦

𝐾𝑄 = π‘₯ + 𝑦 β€²

𝑆 = π‘₯ βŠ• 𝑦 βŠ• 𝑄

FF input and output equations

Page 12: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

SERIAL ADDITION USING REGISTERS

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State table for the full adder implementation using a 𝐽𝐾 FF

Page 13: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

UNIVERSAL SHIFT REGISTER

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This is the most general case of a register and has the following capabilities:

1. A clear control to clear the register to 0

2. A Clk input to synchronize the operations

3. A shift-right control to enable the shift-right operation and the serial input and output lines associated with the shift right

4. A shift-left control to enable the shift-left operation and the serial input and output lines associated with the shift left

5. A parallel-load control to enable a parallel transfer and the n input lines associated with the parallel transfer

6. n parallel output lines

7. A control state that leaves the information in the register unchanged

Page 14: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

UNIVERSAL SHIFT REGISTER

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πΉπ‘’π‘›π‘π‘‘π‘–π‘œπ‘› π‘‘π‘Žπ‘π‘™π‘’

πΊπ‘Ÿπ‘Žπ‘β„Žπ‘–π‘ π‘ π‘¦π‘šπ‘π‘œπ‘™

𝑠0 𝑠1

πΆπ‘™π‘˜

πΆπ‘™π‘’π‘Žπ‘Ÿ

π‘ƒπ‘Žπ‘Ÿπ‘Žπ‘™π‘™π‘’π‘™ 𝐼 𝑖𝑛𝑝𝑒𝑑𝑠

π‘ƒπ‘Žπ‘Ÿπ‘Žπ‘™π‘™π‘’π‘™ 𝐴 π‘œπ‘’π‘‘π‘π‘’π‘‘π‘ 

𝑀𝑆𝐡_𝑖𝑛 𝐿𝑆𝐡_𝑖𝑛

Page 15: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

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𝑠1

4 βˆ’ 𝑏𝑖𝑑 π‘ˆπ‘›π‘–π‘£π‘’π‘Ÿπ‘ π‘Žπ‘™ π‘†β„Žπ‘–π‘“π‘‘ π‘…π‘’π‘”π‘–π‘ π‘‘π‘’π‘Ÿ

𝑠0

𝐴3 𝐴2 𝐴1 𝐴0

𝐼1 𝐼0 𝐼2 𝐼3

πΆπ‘™π‘˜

πΆπ‘™π‘’π‘Žπ‘Ÿ

π‘†π‘’π‘Ÿπ‘–π‘Žπ‘™ 𝑖𝑛𝑝𝑒𝑑 π‘“π‘œπ‘Ÿ

π‘ β„Žπ‘–π‘“π‘‘ βˆ’ 𝑙𝑒𝑓𝑑

π‘ƒπ‘Žπ‘Ÿπ‘Žπ‘™π‘™π‘’π‘™ 𝐼𝑛𝑝𝑒𝑑𝑠

π‘ƒπ‘Žπ‘Ÿπ‘Žπ‘™π‘™π‘’π‘™ 𝑂𝑒𝑑𝑝𝑒𝑑𝑠

π‘†π‘’π‘Ÿπ‘–π‘Žπ‘™ 𝑖𝑛𝑝𝑒𝑑 π‘“π‘œπ‘Ÿ

π‘ β„Žπ‘–π‘“π‘‘ βˆ’ π‘Ÿπ‘–π‘”β„Žπ‘‘

Page 16: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

UNIVERSAL SHIFT REGISTER

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β€’ Each of the four multiplexers has two common selection inputs 𝑠1 and 𝑠0

β€’ Input 0 in each mux is selected when 𝑠0𝑠1 = 00, input 1 is selected when 𝑠0𝑠1 = 01, and similarly for the other two inputs

β€’ The selection inputs control the mode of operation of the shift register, according to the function table

β€’ When 𝑠0𝑠1 = 00, the present value of the register is applied to the 𝐷 inputs of the FF, so that the output recirculates to the input

β€’ The next clock edge transfers into each FF the binary value it held previously, and no change of state occurs

Page 17: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

UNIVERSAL SHIFT REGISTER

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β€’ When 𝑠0𝑠1 = 01, terminal 1 of the mux inputs has a path to the 𝐷 inputs of the FFs. This causes a shift-right operation, with the serial input transferred into FF 𝐴3

β€’ When 𝑠0𝑠1 = 10, a shift-left operation results, with the other serial input going into FF 𝐴0

β€’ Finally, when 𝑠0𝑠1 = 11, the binary info on the parallel input lines is transferred into the register simultaneously during the next clock cycle

Page 18: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

UNIVERSAL SHIFT REGISTER: APPLICATIONS

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β€’ Shift registers are often used to interface digital systems located remotely from each other

β€’ For example, if we need to transmit an 𝑛 βˆ’bit message between two distant points, it will be expensive to use 𝑛 lines to transmit the 𝑛 bits in parallel

β€’ It is more economical to use a single line and transmit the message serially, one bit at a time

β€’ The transmitter accepts the 𝑛 βˆ’bit message in parallel into a shift register and then transmits the data serially along the common line

Page 19: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

UNIVERSAL SHIFT REGISTER: APPLICATIONS

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β€’ The receiver accepts the message serially into a shift register

β€’ When all 𝑛 bits are received, they can be taken from the outputs of the register in parallel

β€’ Thus, the transmitter performs a parallel-to-serial conversion of the message and the receiver does a serial-to-parallel conversion

Page 20: ELCT 201: DIGITAL LOGIC DESIGN - German University in Cairo

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ASSIGNMENT 2 REMINDER!

β€’ Deadline of assignment 2 is Monday the 27th of November, 2017