elct 201: digital logic design - german university in cairo
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ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, [email protected]
Dr. Eng. Wassim Alexan, [email protected]
Lecture 8
ΩΩΩ 1438Ψ°Ω Ψ§ΩΨΨ¬Ψ©
Winter 2017
Following the slides of Dr. Ahmed H. Madian
COURSE OUTLINE
1. Introduction
2. Gate-Level Minimization
3. Combinational Logic
4. Synchronous Sequential Logic
5. Registers and Counters
6. Memories and Programmable Logic
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LECTURE OUTLINE
β’ Registers
β’ Structure and Definition
β’ Serial Registers
β’ Parallel Registers
β’ Serial Adder
β’ Universal Shift Register
β’ Universal Shift Register: Applications
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REGISTERS
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β’ A register is a memory element that can be used to store more than a single bit of information
β’ A register is made up of several flip-flops with common control signals that control the movement of data to and from the registers
β’ An π-bit register consists of π flip-flops and is capable of storing an π-bit word
β’ The main operations on a register are the same as for any storage element, namely: β’ load or store: input new data into the register
β’ Read: retrieve the stored data in the register
SERIAL I/P AND O/P REGISTERS
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πΆππ
ππππππ ππππ’π‘
ππππππ ππ’π‘ππ’π‘
πΌπ π1 π2 π3 π4
= ππ’π‘
π‘0 1 0 0 0 0
π‘1 0 1 0 0 0
π‘2 1 0 1 0 0
π‘3 1 1 0 1 0
π‘4 1 1 1 0 1
π‘5 0 1 1 1 0
π‘6 0 0 1 1 1
π‘7 0 0 0 1 1
π1 π2 π3
PARALLEL I/P AND O/P REGISTERS
6 πΆππ πΆππππ
πΌ3
πΌ2
πΌ1
πΌ0
π΄3
π΄2
π΄1
π΄0
But what if we do not want to load new
data with every clock cycle? What if we
want to keep the same data in the
register?
β’ With every positive edge of the clock,
new data is loaded into the register, in a parallel fashion
PARALLEL I/P AND O/P REGISTERS
7 πΆππ
πΏπππ
πΌ3
πΌ2
πΌ1
πΌ0
π΄3
π΄2
π΄1
π΄0
This design allows us
to:
1. Either load new
data bits into the
register
2. Or keep the old
outputs, by
recirculating them
back into the FF
inputs
SERIAL ADDITION USING REGISTERS
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πΆππ
πβπππ‘ ππππ‘πππ
ππππππ ππππ’π‘
πΆππππ
Circuit implementation
using a FA and a π· FF
SERIAL ADDITION USING REGISTERS
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β’ Initially, register π΄ holds the augend and register π΅ holds the addend, while the carry FF is cleared to 0
β’ The outputs ππ of π΄ and π΅ provide a pair of significant bits for the full adder at π₯ and π¦. Output π of the FF provides the input carry at π§
β’ The π βπππ‘ ππππ‘πππ enables both registers and the carry FF, so that at the next clock pulse, both registers are shifted once to the right, the sum bit from π enters the left-most FF of π΄, and the output carry is transferred into FF π
β’ The π βπππ‘ ππππ‘πππ enables the registers for a number of clock pulses equal to the number of bits in the registers
β’ For each succeeding clock pulse, a new sum bit is transferred to π΄, a new carry is transferred to π, and both registers are shifted once to the right
β’ This process continues until the π βπππ‘ ππππ‘πππ is disabled
SERIAL ADDITION USING REGISTERS
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β’ Thus, the addition is accomplished by passing each pair of bits together with the previous carry through a single full adder circuit and transferring the sum, one bit at a time, into register π΄
β’ Initially, register π΄ and the carry FF are cleared to 0, and then the first number is added from π΅
β’ While π΅ is shifted through the full adder, a second number is transferred to it through its serial input
β’ The second number is then added to the contents of register π΄ while a third number is transferred to serially into register π΅
β’ This can be repeated to perform the addition of 2, 3 or more 4-bit numbers and accumulate their sum in register π΄ (assuming that register π΄ is built of 4 FFs only)
SERIAL ADDITION USING REGISTERS
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πΆππ
πβπππ‘ ππππ‘πππ
ππππππ ππππ’π‘
πΆππππ
Circuit implementation using a π½πΎ FF
π½π = π₯π¦
πΎπ = π₯ + π¦ β²
π = π₯ β π¦ β π
FF input and output equations
SERIAL ADDITION USING REGISTERS
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State table for the full adder implementation using a π½πΎ FF
UNIVERSAL SHIFT REGISTER
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This is the most general case of a register and has the following capabilities:
1. A clear control to clear the register to 0
2. A Clk input to synchronize the operations
3. A shift-right control to enable the shift-right operation and the serial input and output lines associated with the shift right
4. A shift-left control to enable the shift-left operation and the serial input and output lines associated with the shift left
5. A parallel-load control to enable a parallel transfer and the n input lines associated with the parallel transfer
6. n parallel output lines
7. A control state that leaves the information in the register unchanged
UNIVERSAL SHIFT REGISTER
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πΉπ’πππ‘πππ π‘ππππ
πΊπππβππ π π¦ππππ
π 0 π 1
πΆππ
πΆππππ
ππππππππ πΌ ππππ’π‘π
ππππππππ π΄ ππ’π‘ππ’π‘π
πππ΅_ππ πΏππ΅_ππ
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π 1
4 β πππ‘ ππππ£πππ ππ πβπππ‘ π ππππ π‘ππ
π 0
π΄3 π΄2 π΄1 π΄0
πΌ1 πΌ0 πΌ2 πΌ3
πΆππ
πΆππππ
ππππππ ππππ’π‘ πππ
π βπππ‘ β ππππ‘
ππππππππ πΌπππ’π‘π
ππππππππ ππ’π‘ππ’π‘π
ππππππ ππππ’π‘ πππ
π βπππ‘ β πππβπ‘
UNIVERSAL SHIFT REGISTER
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β’ Each of the four multiplexers has two common selection inputs π 1 and π 0
β’ Input 0 in each mux is selected when π 0π 1 = 00, input 1 is selected when π 0π 1 = 01, and similarly for the other two inputs
β’ The selection inputs control the mode of operation of the shift register, according to the function table
β’ When π 0π 1 = 00, the present value of the register is applied to the π· inputs of the FF, so that the output recirculates to the input
β’ The next clock edge transfers into each FF the binary value it held previously, and no change of state occurs
UNIVERSAL SHIFT REGISTER
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β’ When π 0π 1 = 01, terminal 1 of the mux inputs has a path to the π· inputs of the FFs. This causes a shift-right operation, with the serial input transferred into FF π΄3
β’ When π 0π 1 = 10, a shift-left operation results, with the other serial input going into FF π΄0
β’ Finally, when π 0π 1 = 11, the binary info on the parallel input lines is transferred into the register simultaneously during the next clock cycle
UNIVERSAL SHIFT REGISTER: APPLICATIONS
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β’ Shift registers are often used to interface digital systems located remotely from each other
β’ For example, if we need to transmit an π βbit message between two distant points, it will be expensive to use π lines to transmit the π bits in parallel
β’ It is more economical to use a single line and transmit the message serially, one bit at a time
β’ The transmitter accepts the π βbit message in parallel into a shift register and then transmits the data serially along the common line
UNIVERSAL SHIFT REGISTER: APPLICATIONS
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β’ The receiver accepts the message serially into a shift register
β’ When all π bits are received, they can be taken from the outputs of the register in parallel
β’ Thus, the transmitter performs a parallel-to-serial conversion of the message and the receiver does a serial-to-parallel conversion
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ASSIGNMENT 2 REMINDER!
β’ Deadline of assignment 2 is Monday the 27th of November, 2017