KING FAHD UNIVERSITY OF PETROLEUM AND MINERALSUniversity Diploma Programs

EET 022: Digital Electronic Circuits

Final ExaminationSunday, January 26, 2003

Student Name: ID #:

Question No. Points Score1. 52. 53. 104. 105. 106. 107. 108. 109. 1010. 1011. 512. 5

Total 100

Q.1 Circle the most accurate answer for each of the following questions.

A. The bit capacity of a memory that has 1024 addresses and can store 8 bits at each address is:

(a) 1024,(b) 8192,(c) 8,(d) 4096.

B. A 32-bit data word consists of:

(a) 2 bytes,(b) 4 nibbles,(c) 4 bytes,(d) 3 bytes and 1 nibble.

C. Data that are stored at a given address in a random-access memory (RAM) is lost when:

(a) power goes off,(b) the data are read from the address,(c) new data are written at the address,(d) answers (a) and (c).

D. Data are stored in a random-access memory (RAM) during the:

(a) read operation,(b) enable operation,(c) write operation,(d) addressing operation.

E. A ROM is a:

(a) nonvolatile memory,(b) volatile memory,(c) read/write memory,(d) byte-organized memory.

(Page 2 of 13)

Q.2 Circle the most accurate answer for each of the following questions.

A. A memory with 256 addresses has:

(a) 256 address lines,(b) 6 address lines,(c) 1 address line, (d) 8 address lines.

B. The storage cell in a SRAM is:

(a) a flip-flop,(b) a capacitor,(c) a fuse,(d) a magnetic domain.

C. A DRAM must be:

(a) replaced periodically,(b) refreshed periodically,(c) always enabled,(d) programmed before each use.

D. A flash memory is:

(a) volatile,(b) a read-only memory,(c) a read/write memory,(d) nonvolatile,(e) answers (a) and (c),(f) answers (c) and (d).

E. Optical storage devices employ:

(a) ultraviolet light,(b) electromagnetic fields,(c) optical couplers,(d) lasers.

(Page 3 of 13)

Q.3 Solve the following questions:

A. Identify the ROM and the RAM in the following Figure:

B. A static memory array with four rows similar to the one in the following Figure is initially storing all 0s. What is its content after the following conditions? Assume a 1 selects a row:

Row 0 = 1, Data in (Bit 0) = 1,Row 1 = 0, Data in (Bit 1) = 1,Row 2 = 1, Data in (Bit 2) = 1,Row 3 = 0, Data in (Bit 3) = 0.

(Page 4 of 13)

Q.4 Solve the following questions:

A. For the ROM array in the following Figure, determine the outputs for all possible input combinations, and summarize them in tabular form (Bright cell is a 1, Dark cell is a 0).

B. Use 16k X 4 DRAMs to build a 64k X 8 RAM. Show the logic diagram. What is the word length and the word capacity of the memory?

(Page 5 of 13)

Q.5 Assuming that the PROM matrix in the following Figure is programmed by blowing a fuse link to create a 0, indicate the links to be blown to program an X

3 look-up table, where X is a number from 0 through 7.

(Page 6 of 13)

Q.6 The analog curve in the following Figure is sampled at 1 ms intervals. Represent the total curve by a series of 4-bit binary numbers.

(Page 7 of 13)

Q.7 Solve the following questions:

A. To achieve a closed-loop voltage gain of 330 with an inverting amplifier, what value of feedback resistor do you use if Ri = 1.0 kΩ?

B. Determine the resolution expressed as a percentage, for each of the following DACs:

(a) 3-bit,(b) 10-bit,(c) 18-bit.

(Page 8 of 13)

Q.8 Determine the output of the DAC in par (a) of the following Figure if the sequence of 4-bit numbers in part (b) is applied to the inputs. The data inputs have a low value of 0 V and a high value of +5 V.

(Page 9 of 13)

Q.9 Solve the following questions:

A. Determine the signal on the bus line in the following Figure for the data-input and enable waveforms shown.

B. Explain the basic difference between a local bus and the PCI bus.

C. DCE and DTE are part of which bus specification? Explain the acronyms, DCE and DTE.

(Page 10 of 13)

Q.10 Solve the following questions:

A. A certain logic gate has a VOH(min) = 2.2 V, and it is driving a gate with a VIH(min) = 2.5 V. Are these gates compatible for HIGH-state operation? Why?

B. A TTL gate has the following actual voltage level values: VIH(min)

= 2.25 V, VIL(max) = 0.65 V. Assuming it is being driven by a gate with VOH(min) = 2.4 V and VOL(max) = 0.4 V, what are the HIGH- and LOW-level noise margins?

C. Voltage specifications for three types of logic gates are given in the following Table. Select the gate that you would use in a high-noise industrial environment.

(Page 11 of 13)

Q.11 Solve the following questions:

A. Each gate in the circuit of the following Figure has a tPLH, and a tPHL, of 4ns. If a positive-going pulse is applied to the input as indicated, how long will it take the output pulse to appear?

B. The following Table lists parameters for three types of gates. Basing your decision on the speed-power product, which one would you select for best performance?

(Page 12 of 13)

Q.12 Solve the following questions:

A. Determine the output level of each TTL gate in the following Figure.

B. What is the basic difference between ECL circuitry and TTL circuitry?

(Page 13 of 13)