inst.eecs.berkeley.edu/~eecs151

Bora Nikoli

EECS151 : Introduction to Digital Design and ICs

Lecture 11 – CMOS

1EECS151 L11 CMOShttps://risc.berkeley.edu/risc-i/reunion/

RISC-I: Reduced Instruction Set Computing

On February 12, 2015, IEEE installed a plaque at UC Berkeley to commemorate the contribution of RISC-I. The plaque reads:

UC Berkeley students designed and built the first VLSI reduced instruction-set computer in 1981. The simplified instructions of RISC-I reduced the hardware for instruction decode and control, which enabled a flat 32-bit address space, a large set of registers, and pipelined execution. A good match to C programs and the Unix operating system, RISC-I influenced instruction sets widely used today, including those for game consoles, smartphones and tablets.

Review

• Pipelining increases throughput• Structural, control and data hazards exist

• FPGAs are widely used for hardware prototyping and accelerating key applications.

• Core FPGA building blocks:• Configurable Logic Blocks (CLBs)

• Slices• Look-Up Tables

• Flip-Flops

• Carry chain

• Configurable Interconnect

EECS151 L11 CMOS 2

FPGA Interconnect

3EECS151 L11 CMOS

Configurable Interconnect

• Between rows and columns of CLBs are wiring channels.

• These are programable. Each wire can be connected in many ways.

• Switch Box: • Each interconnection has a transistor

switch.

• Each switch is controlled by 1-bit configuration register.

4EECS151 L11 CMOS

FPGA Features: BRAMs, DSP, AI

5EECS151 L11 CMOS

Diverse Resources on FPGA

6

Colors represent different types of resources:

Logic

Block RAM

DSPs

ClockingI/OSerial I/O + PCI

A routing fabric runs throughout the chip to wire everything together.

Virtex-5 Die Photo [Xilinx]

EECS151 L11 CMOS

Block RAM

• Block Random Access Memory

• Used for storing large amounts of data:• 18Kb or 36Kb

• Configurable bitwidth

• 2 read and write ports

• More recently• UltraRAM in UltraScale+ devices

7

Xilinx Datasheet

EECS151 L11 CMOS

DSP Slice

8

Efficient implementation of multiply, add, bit-wise logical.

Z-1 MULT Z-1 ADD Z-1

Z-2

36

OpMode7

48A:B48

0

072

Y36

X

017-bit shift

17-bit shift

A

25

18

CEM REG

D Q

CEP REG

D Q

B48

D

ALUMode

CarryIn

48

Z

CEC REG

D Q

1

4

=C or MC

CEA REG

D Q2-Deep

CEB REG

D2-Deep

Q

P

PATTERN DETECT

C

Inpu

t Con

ditio

ning

OPCTL

Xilinx Resource

EECS151 L11 CMOS

AI Engine

• Versal AI Core

9

Xilinx HotChips’2019

EECS151 L11 CMOS

State-of-the-art Xilinx FPGA Platform

• Versal (ACAP: Adaptive Compute Acceleration Platform)

10

Xilinx HotChips’2019

AI Engine

EECS151 L11 CMOS

CMOS Process

11EECS151 L11 CMOS

Design Process

• Design through layers of abstractions

EECS151 L11 CMOS 12

Specification(e.g. in plain text)

Model(e.g. in C/C/SystemVerilog)

RTL logic design(e.g. in Verilog, SystemVerilog)

Physical design(schematic, layout; ASIC, FPGA)

Manufactured part

Validation

Verification(logic/physical design

correct)

Test(Does the part work?)

Tests and test vectors

Architecture(e.g. in-order, out-of-order)

Specification(e.g. in plain text)

Model/ /(e.g. in C/C/( g / /SystemVerilogy g))

Validation Tests andtest vectors

Architecture(e.g. in-order, out-of-order)

Step-and-Scan Lithography

EECS151 L11 CMOS 13

Semiconductor Manufacturing• Repetitive steps (40-70 masks):

• Passivation• Photoresist coating• Patterning (stepper)• Develop• Etch• Process step

• Etching• Deposition• Implant

• Remove resist• Repeat

• Zoom into a chip:

14

http://laplace.ucv.cl/Charlas/Semiconductors/Chip/semiconductors.htmlhttps://youtu.be/Fxv3JoS1uY8EECS151 L11 CMOS

CMOS Process

• Post ~250nm CMOS

• Shallow-trench isolation, dual/triple-well process

15EECS151 L11 CMOS

Metal Stack

• Interconnect is predominantly copper

16EECS151 L11 CMOS

Metal Stack in Modern Processes

17

• Metal stack• Bottom layers have pitch that

matches transistors

• Intermediate are 2-4x

• Top layers are wide and thick:Power distribution, clock

EECS151 L11 CMOS

Lithography Scaling

m

10000

1000

100

10

10

1

0.1

0.01

nm

130nm0nm90nm

65nm

1970 1980 1990 2000 201010

2020

nm45nmnm

32nm22nm

Nominal feature size scaling

130n180nm180n

250nm

365nm248nm

193nm

EUV 13nm

EUV – Expected in volume this year

EECS151 L11 CMOS 18

Sub-Wavelength Lithography

• Light projected through a gap

Mask193nm light

Lightintensity

Lightintensity

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Lithography Implications

• Forbidden directions

20

• Forbidden pitches

• Optical proximity correction (OPC)

?

EECS151 L11 CMOS

We Would Just Like a Square Contact…

• OPC vs. ILT

21

https://semiengineering.com/what-happened-to-inverse-lithography/

EECS151 L11 CMOS

Multiple Patterning

• “Layout coloring”

• 7nm process is quadruple patterned (w/o EUV)22

Starting layout Split pattern Overlay

With overlay misalignment

• Double patterning (pitch-split double exposure)

EECS151 L11 CMOS

Lithography and Processing Takeaways

• 193nm lithography impacts many of the design rules in modern processes:

• Preferred and forbidden directions

• Forbidden pitches

• Multiple patterning

• EUV relaxes many of the restrictions in sub 5nm processes

EECS151 L11 CMOS 23

Administrivia• Semiconductor Workforce Fellowships in the area of SoC design

• 8 undergraduate scholarships (4k each), applications due October 15

• Homework 4 is due today• No new homework this week

• Homework 5 will be posted later this week, due next week

• No lab this week• Lab 6 (last) after the midterm

• Midterm 1on October 7, 7-8:30pm• You will be assigned a classroom

• One double-sided page of notes allowed

• Material includes FPGAs

EECS151 L11 CMOS 24

MOS Transistors

25EECS151 L11 CMOS

MOS Transistors

• Symbol

26

N-type

NMOS

P-type

PMOSW/L

W

L

D

S

G

Source (S) Drain (D)Gate (G)

N+ diffusion

Polysilicon (or metal)

S

D

GW/L

W

L P+ diffusion• Devices are symmetrical

• NMOS: Drain is at higher voltage

• PMOS: Source is at higher voltage

Gate oxide

Contacts

EECS151 L11 CMOS

Different Kinds of MOS Transistors

• Planar bulk CMOS

27

N-type

NMOSW/L

W

L

D

S

G

S DG

W is discrete!

L

S DG

• FinFETIntel 10nm

IEDM 2017

TSi

Source

DrainDrainGate

L

HFIN

EECS151 L11 CMOS

Different Kinds of MOS Transistors

• Planar bulk CMOS

28

N-type

NMOSW/L

W

L

D

S

G

S DG

W

L

S DG

• Fully-depleted SOIST 28nm

VLSI 2012

Burried oxide (or BOX)

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Transistors are Changing

• From bulk to finFET and FDSOI

65/55 nm 45/40 nm 32/28nm 22/20nm 16/14nm 10nm

Bulk

Si02/SiNStrain

Intel, IEDM’07HK/MGStrain

FinFET

FDSOI

Intel, VLSI’14

Intel, IEDM’12

ST, VLSI’12

Intel, IEDM’09

TSMC, Samsung

Intel, IEDM’17

7nm

EECS151 L11 CMOS 29

Transistor Dimensions are Quantized

• FinFET widths are discrete (W = kWunit)• k is an integer

• Lengths are quantized because of lithography• Also are quantized lower metal layers, contacts…

30EECS151 L11 CMOS

Ohm’s Law

• Physical resistors

31

R

+

-

VI

V

I

I = V/R

W

LT

R =• In a planar process,

designer controls W and L

R

• Resistors • Variable resistors

V

I

R

EECS151 L11 CMOS

Series and Parallel

• With two identical resistors, R

32

R

R

Rseries = 2R R R Rparallel = R/2

Equivalent to doubling length

Equivalent to doubling width

V

I

R

R/2

2R

EECS151 L11 CMOS

An n-Channel MOS Transistor

p-

n+

VD = 0V

n+

VS = 0V Polysilicon gate,

dielectric, and substrate form a

capacitor.

When VGS<VTh transistor is off

dielectric

VG = 0V

I = 0

p-

n+

VD > 0

n+

VS = 0Vdielectric

VG = 0V VDS > 0, transistor leaks

IDS ~ nAI > 0

EECS151 L11 CMOS 33

An n-Channel MOS Transistor

p-

n+

VD = 0V

n+

VS = 0V When VGS<VTh transistor is off

dielectric

VG = 0V

I = 0

----------

p-

n+

VD > 0

n+

VS = 0Vdielectric

VG > VTh

+++++++----------

VG > VTh, small region near the

surface turns from p-type to

n-type.

nFet is on.

Current is proportional to VDS

I > 0

EECS151 L11 CMOS 34

An n-Channel MOS Transistor

----------

p-

n+

VD > 0

n+

VS = 0Vdielectric

VGS > VTh

+++++++----------

VDS and VGS change IDS

I > 0

VDS

IDSVGS = VDD

VGS= 0VGS > VTh

----------

p-

n+

VDG < 0

n+

VS = 0Vdielectric

VG > VTh

+++++++----------

VGD < VTh transistor saturates

(VDS > VGS – VTh)

I > 0

VDS

IDS VGS

EECS151 L11 CMOS 35

MOS Transistors

• NMOS Transistor I-V characteristics

36

D

S

G

VDS

IDS VGS= VDD

VGS= 0

VDS

IDSVGS= VDD

VGS= 0

Old transistor ~7nm transistor

VDS

IDS VGS

VDS

IDSVGS

Variable

resistor!VGS

IDS

Nearly linearIDS ~ K(VGS-VTh)

EECS151 L11 CMOS

Velocity Saturation

• Carrier velocity in the channel saturates

37

Electric field, E [V/ m]

Carriervelocity[m/s]

Velocity linearly proportional to E, v = E

Velocity saturated at v 105 m/s(for fields > 1V/m)

• All submicron transistors are velocity saturated

• Other effects (drain-induced barrier lowering)cause IDS to increase in saturation

VDS

IDSVGS= VDD

VGS= 0

EECS151 L11 CMOS

Summary

• Core FPGA building blocks:• Configurable Logic Blocks (CLBs)

• Configurable Interconnect

• Switch boxes

• Modern FPGA Designs:• BRAMs, DSPs, and AI Engines

• CMOS process is used for producing chips• Planar bulk process used up to 28nm node

• finFET used below the 22nm node

• Also FDSOI, but we didn’t talk about it

38EECS151 L11 CMOS