eecs150 - digital design lecture 14 - sequential circuits i (state elements)
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EECS150 - Digital Design Lecture 14 - Sequential Circuits I (State Elements). March 12, 2002 John Wawrzynek. Circuit with feedback . Examples: FSM D-type latch How about CL logic with feedback but without register?. Sequential circuits exhibit either synchronous or asynchronous behavior: - PowerPoint PPT PresentationTRANSCRIPT
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EECS150 - Digital DesignLecture 14 - Sequential Circuits I
(State Elements)
March 12, 2002
John Wawrzynek
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Sequential CircuitsCircuit with feedback.
• Examples:
FSM
D-type latch
How about CL logic with feedback but without register?
• Sequential circuits exhibit either synchronous or asynchronous behavior:– Synchronous: “state” of the
circuit changes at regular intervals controlled by a clock.
– Asynchronous: state changes with changing inputs. No clock present or circuit doesn’t wait for it.
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Cross-coupled NOR gates
• If both R=0 & S=0, then cross-couped NORs equivalent to a stable latch:
• What happens if R or S or both become = 1?
R S
NOR00 101 010 011 0
remember,
R
S
Q
Q'
0
1 00
0 1
1 0
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Asynchronous State Transition Diagram
QQ'01
QQ'10
QQ'00
?
SR=00 SR=00
SR=10
SR=01
SR=11
SR=01
SR=11
SR=10
SR=00
SR=10SR=01
SR Latch:
SR Q00 hold01 010 111 indeterminate
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Nand-gate based SR latch
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Level-sensitive SR Latch
• The input “C” works as an “enable” signal, latch only changes output when C is high.
• usually connected to clock.• Generally, it is not a good idea to use a clock as a logic signal (into
gates etc.). This is a special case.
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D-latch
Compare to transistor version:
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Flip-flops
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J-K FF
J K Q(t) Q(t+)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0
hold
reset
set
toggle
• Add logic to eliminate “indeterminate” action of RS FF.
• New action is “toggle”• J = “jam”• K = “kill”
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J-K Flip-flop from D-FF
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Toggle Flip-flop from D-FF
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Storage Element Taxonomy
synchronous asynchronous
level-sensitive edge-triggered
D-type n.a.
JK-type n.a. n.a.
RS-type “latch” “flip-flop” “latch”
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Design Example with RS FF
• With D-type FF state elements, new state iscomputed based on inputs & present state bits - reloaded each cycle.
• With RS (or JK) FF state elements, inputs are used to determine conditions under which to set or reset state bits.
• Example: bit-serial adder (LSB first)
n-bit shift register
n-bit shift registers
sc
reset
R
FAFF
B
A
With D-FF for carry
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Bit-serial adder with RS FF
• RS FF stores the carry:
SR
Q
a
b
0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1
a b ci ci+1 s
Carry kill a’b’
Carry generateab
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Resets/presets
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Adding Reset/Presets
• D-type flip-flop from latches:
• Asynchronous reset in Flip-flop:Either inverter (or both) can be replaced by either NOR gate or NAND gate in the second
latch of the flip-flop. The second input to the gate is connected to reset or preset signal. The choice of NOR versus NAND defines the sense of the reset/preset (active-high versus active-low). The choice which inverter to replace defines reset versus preset.
• Synchronous reset:A similar procedure as above is applied to the first latch of the flip-flop. Additional logic is
needed to synchronize the reset signal with the correct level of the clock.
D-latch circuit