ee603 chapter5 student

5/27/2018 Ee603 Chapter5 Student

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EE603 CMOS INTEGRATEDCIRCUIT DESIGN

Static CMOS inverter

Azman Bin Mat Hussin


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CMOS VLSI DesignCMOS INVERTER Slide 2

Outline

CMOS inverter switch model

CMOS inverter properties

CMOS inverter loads line

CMOS inverter voltage transfer characteristic

The switch model of dynamic behavior of static

CMOS inverter


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CMOS VLSI DesignCircuits and Layout Slide 3

CMOS Inverter Transistor level & layout

OutIn

VDD

PMOS

NMOS PolysiliconIn Out

VDD

GND

PMOS2

Metal 1

NMOS

Contacts

N Well


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Two Inverters

Connect in Metal

Share power and ground

Abut cells

VDD


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CMOS VLSI Design

CMOS Switch Characteristic

Switch In Series

Circuits and Layout Slide 5

INPUT

OUTPUT

S1

S2

Truth Table

S1 S2 PATH?

OFF OFF

OFF ON

ON OFF

ON ON


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INPUT

OUTPUT

S1

S2

Truth Table (OFF/ON=0/1)

S1 S2 PATH?

OFF OFF NO

OFF ON NO

ON OFF NOON ON YES

What Function ??


Switch In Series


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CMOS VLSI Design

Switch In Series


INPUT

OUTPUT

S1

S2


S1 S2 PATH?0 0 0

Function = ??



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INPUT

OUTPUT

S1

S2


S1 S2 PATH?0 0 0

0 1 0

Function = ??

Switch In Series



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INPUT

OUTPUT

S1

S2


S1 S2 PATH?0 0 0

0 1 0

1 0 0

Function = ??


Switch In Series


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INPUT

OUTPUT

S1

S2


S1 S2 PATH?0 0 0

0 1 0

1 0 0

1 1 1

Function = Logic AND


Switch In Series


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INPUT

OUTPUT

S1

Truth Table

S1 S2 PATH?OFF OFF NO

OFF ON YES

ON OFF YES

ON ON YES

S2

Switch In Parallel



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INPUT

OUTPUT

S1

Truth Table

S1 S2 PATH?0 0 0

Function =??

S2


Switch In Parallel


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INPUT

OUTPUT

S1

Truth Table

S1 S2 PATH?0 0 0

0 1 1

Function =??

S2


Switch In Parallel


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INPUT

OUTPUT

S1

Truth Table

S1 S2 PATH?

0 0 0

0 1 1

1 0 1

Function =??

S2


Switch In Parallel


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INPUT

OUTPUT

S1

Truth Table

S1 S2 PATH?0 0 0

0 1 1

1 0 1

1 1 1

Function = Logic OR

S2


Switch In Parallel


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CMOS VLSI Design

CMOS TRANSISTOR


Gate

Drain

Source

Gate

Source

Drain

pMOS

nMOS

Complementary MOS

P-channel MOS (pMOS)

N-channel MOS (nMOS)

pMOS

P-type source and drain

diffusions N substrate

Mobility by holes

nMOS

N-type source and draindiffusions

P substrate

Mobility by electrons


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CMOS VLSI Design

CMOS Signal Transfer Property


Gate Path

0 Closed

1 Open

Gate

Drain

Source

Gate

Source

Drain

Gate Path

0 Open

1 Closed

pMOS

nMOS

Transmits 1 wellTransmits 0 poorly

Transmits 0 wellTransmits 1 poorly


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CMOS VLSI Design

High Impedance


When a path

exists

Impedance is low

to allow ample

flow of current

When no path

Impedance is

high allowingalmost no current

flow between two

terminals

Gate=1

DrainSource

> 100M

Closed

Gate=0

DrainSource

Open


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Switch Model of NMOS Transistor

Gate

Source

(of carriers)

Drain

(of carriers)

| VGS |

| VGS | < | VT| | VGS | > | VT|

Open (off) (Gate = 0) Closed (on) (Gate = 1)

Ron


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Switch Model of PMOS Transistor

Gate

Source

(of carriers)

Drain

(of carriers)

| VGS |

| VGS | > | VDD| VT | | | VGS | < | VDD|VT| |

Open (off) (Gate = 1) Closed (on) (Gate = 0)

Ron


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CMOS Inverter:

Switch Model of Dynamic Behavior

VOL= 0

VOH= VDDVM= f(Rn, Rp)

VDD VDD

Vin 5 VDD Vin 5 0

VoutVout

Rn

Rp


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VoutVout

Rn

Rp

VDDV

DD

Vin5 VDDVin5 0(a) Low-to-high (b) High-to-low

CLCL

Gate response time is determined by the time to charge CLthrough Rp(discharge CLthrough Rn)

CMOS Inverter: Transient Response


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CMOS VLSI Design

CMOS INVERTER AS SWITCH


SYMBOL

INPUT A = LOGIC 1 INPUT A = LOGIC 0

1. NMOS is ON, PMOS is OFF.

2. NMOS will transfer logic 0 (GND) to

the output.

3. Output Y = Logic 0

1. PMOS is ON, NMOS is OFF.

2. PMOS will transfer logic 1

(VDD) to the output.

3. Output Y = Logic 1

TRUTH TABLE


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CMOS VLSI Design

important properties of static CMOS

1. The high and low output levels equal VDD and GND,respectively

2. The logic levels are not dependent upon the relative device

sizes, so that the transistors can be minimum size.

3. In steady state, there always exists a path with finite resistance

between the output and either VDD or GND. Typical values of

the output resistance are in kW range.

4. The input resistance of the CMOS inverter is extremely high, as

the gate of an MOS transistor is a virtually perfect insulator and

draws no dc input current



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Voltage TransferCharacteristic


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CMOS VLSI Design

Summary of transistor operation


NMOS transistor PMOS transistor


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CMOS VLSI Design

The nature and the form of the voltage-transfer characteristic(VTC) can be graphically deduced by superimposing the

current characteristics of the NMOS and the PMOS.

Such a graphical construction is traditionally called a load-line

plot.

It requires that the I-V curves of the NMOS and PMOS devices

are transformed onto a common coordinate set.

We have selected the input voltage Vin, the output voltage

Vout and the NMOS drain current IDN as the variables of

choice. The PMOS I-V relations can be translated into

this variable space by the following relations


CMOS inverter load lines


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CMOS VLSI Design

The PMOS I-V relations can be translated into thisvariable space by the following relations

The load-line curves of the PMOS device are obtained by a

mirroring around thexaxis

and a horizontal shift over VDD. This procedure is outlined in

Figure below, where the subsequent steps to adjust the original PMOS I-V curves to the

common coordinate set Vin, Vout and IDn are illustrated.




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CMOS VLSI Design

Transforming PMOS I-V characteristic to a common coordinate set

(assuming VDD = 2.5 V).



VDSp

IDp

VGSp=-5

VGSp=-2

VDSp

IDnVin=0

Vin=3

Vout

IDnVin=0

Vin=3

Vin = VDD-VGSpIDn = - IDp

Vout = VDD-VDSp

Vout

IDnVin = VDD-VGSp

IDn = - IDp

Vout = VDD-VDSp


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CMOS VLSI Design

DC transfer characteristics



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CMOS VLSI Design

CMOS Inverter Load Characteristics


IDn

Vout

Vin= 2.5

Vin

= 2

Vin= 1.5

Vin= 0

Vin

= 0.5

Vin= 1

NMOS

Vin= 0

Vin

= 0.5

Vin= 1

Vin

= 1.5

Vin= 2

Vin

= 2.5

Vin= 1Vin= 1.5

PMOS

Figure 2: Load curves for NMOS and PMOS transistors of the static CMOS inverter (VDD

= 2.5 V). The dots represent the dc operation points for various input voltages


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CMOS VLSI Design

CMOS Inverter Load Characteristics

The resulting load lines are plotted in Figure 2 For a dc operatingpoints to be valid, the currents through the NMOS and PMOS devices

must be equal.

Graphically, this means that the dc points must be located at the

intersection of corresponding load lines.

A number of those points (for Vin = 0, 0.5, 1, 1.5, 2, and 2.5 V) aremarked on the graph.

As can be observed, all operating points are located either at the high

or low output levels.

The VTC of the inverter hence exhibits a very narrow transition zone.

This results from the high gain during the switching transient, when

both NMOS and PMOS are simultaneously on, and in saturation.

In that operation region, a small change in the input voltage results in

a large output variation. All these observations translate into the VTC



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CMOS Inverter VTC

0

0.5

1

1.5

2

2.5

0 0.5 1 1.5 2 2.5

Vin(V)

Vout

(V)

NMOS offPMOS res

NMOS sat

PMOS res

NMOS sat

PMOS sat

NMOS res

PMOS sat NMOS res

PMOS off

VDD

Vout

CL

AB

C

ED


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CMOS VLSI Design

Complete voltagetransfer characteristic VTC


NMOS offPMOS in non sat

NMOS in

sat

PMOS in

non sat

NMOS in

sat

PMOS in

sat

NMOS in

non satPMOS in

sat

NMOS in

nonsatPMOS off

Vout

= VDS

Drain

currentIDS

Vin=2V

VCC

Vin=1V

Vin=3V

Vin=4V

ee603 chapter5 student

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