ee 6961-009: low power circuit design -...

UNIVERSITY OF UTAH ELECTRICAL ENGINEERING DEPARTMENT

EE 6961-009: Low Power Circuit Design

Spring 2001

Tuesday/Thursday 3:40-5:00 PM Instructor: Prof. Reid Harrison Office: 4514 MEB Office Hours: M 3:00-5:00 PM, W 2:00-3:00 PM Phone: 587-7926 Email: [email protected] Prerequisites: EE 3110 or equivalent (see below) Text: Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Web Page: http://www2.elen.utah.edu/~harrison/lowpower.html Grader: Anand Gopalan Email: [email protected] General Description This class will cover the theory and practical aspects of low-power integrated circuit design in CMOS technology. The emphasis will be on transistor-level analog design. Low-power digital design issues will be covered at the level of standard cell design (e.g., logic gates, memory cells, etc.) and with attention to device scaling issues. “Architecture level” digital power-saving techniques will not be covered. While we will use a few chapters from Razavi’s book for some parts of the class, most of the material will be provided through notes and lectures. You are responsible for everything I say in class with regards to course material, assignments, and exam schedules. While some information will be posted on the class web site for convenience, I do not guarantee this information will always be up-to-date. Therefore, it is essential that you attend class regularly. Prerequisite Knowledge

• It is assumed that students taking this class understand basic time-domain and frequency-domain linear circuit analysis.

• It is assumed that they are somewhat familiar with the basic structure of a MOSFET, and have analyzed circuits involving transistors at some point in their education.

• It is assumed that each student has some experience with circuit simulation. • Some homework problems will require the use of MATLAB. If you have never used

MATLAB before, there are introductory tutorials available on the web. If you are an undergraduate taking this class, you must have taken EE 3110 or its equivalent under the old quarter system.

If you don’t remember the details of MOSFET operation, don’t worry. We will “relearn” how MOS transistors work starting from the basics. However, a basic competency in circuit analysis is essential! Homework There will be approximately eight homework assignments in this course involving written problems, MATLAB assignments, and/or circuit simulation assignments. Simulations will be performed in the CADE lab. All problem sets will be collected and graded. Homework assignments are due by 6:00 PM on the specified date in the class locker on the 3rd floor of MEB. Homework assignments turned in up to 24 hours late will be penalized 10% (i.e., multiply your score by 0.9). Assignments turned in more than 24 hours late will not be accepted. Your lowest homework grade will be dropped. Solutions will be posted after the problems are due. Homework will count 40% towards your final grade. Collaboration policy: While you are allowed to work with other students on the homework assignments, everything you turn in should be your own work. Dividing up the work between classmates and then sharing answers is considered cheating. Discussing possible solutions to problems together is not cheating. Exams There will be two 1.5-hour midterm exams given during class. No exam will be given during finals week. Each exam will count 20% towards your final grade. Report A written report will be assigned during the final month of the class. This report will count 20% towards your final grade. Details on the content of the report will be provided later. General Course Outline

• Basics of Power and Energy

• Power Sources for Low-Power Systems

• Overview of CMOS VLSI Technology

• Operation of the MOS Transistor in Strong Inversion

• Operation of the MOS Transistor in Weak Inversion

• MOSFET Models Valid in Strong and Weak Inversion

• CMOS Circuit Building Blocks – Low-Voltage and Low-Current Operation

• Noise in MOS Devices

• Low-Voltage and Low-Current Analog Design

• Low-Power Digital Design

• Scaling Issues

• Theoretical Limits to Power Consumption in Analog and Digital Systems

Low-Power Circuit Design R. Harrison

Lecture 1 1

Why is Low Power Circuit Design Important? Thanks to integrated circuit technology, electronic devices have greatly decreased in size and mass over the past few decades. Most of us routinely carry or wear electronics every day. While VLSI (Very Large Scale Integration) technology, particularly CMOS, has enjoyed the rapid exponential growth characterized by Moore’s Law, energy storage technology (mainly batteries) has grown much more slowly.

Application Areas for Low-Power Electronics • Portable computing, communication, and multimedia devices

o Laptops o Palmtops o Cell phones o Pagers o Video Recorders o Cameras o Watches (Power < 500nW @ 1.5V) o Portable instruments and measurement devices

• Remote sensing o Long-term environmental monitoring in wilderness areas or the ocean o Mobile robots o Satellites and space probes

• Implantable biomedical devices o Pacemakers o Defibrillators o Muscle stimulators o Neuroprosthetic devices

• Cochlear implants to restore hearing loss • Retinal and cortical stimulators to restore vision loss • Neural control of prosthetic limbs

Low power systems are usually smaller and cheaper to manufacture (smaller heat sinks, no cooling fans, smaller power supplies, smaller batteries).

Barriers to Low Power Design • Existing circuit libraries and standard cells…

o …often have inadequate circuit architectures for low-voltage or low-current operation

o …often are designed for fixed bias currents at the mA level. • Lack of adequate, design-oriented transistor models for low-current operation. • Designers are afraid of breaking “the psychological microamp barrier” (Eric Vittoz). • Lack of a power-conscious culture among designers


Lecture 1 2

Energy and Power Power is simply the rate of energy transfer.

Energy is our limited resource, and power is the rate at which we consume (or replenish) that resource.

SI unit for energy = joule (J)

1 J = 1 N·m = 1 kg·m2/s2 = 1 V·C = 1 W·s

SI unit for power = watt (W)

1 W = 1 J/s = V·C/s = V·A ! A 1-watt system consumes 1 joule of energy each second.

In circuit design, the watt-hour (Wh) is generally more useful as a unit of energy than the joule (watt-second) since our devices generally run for hours, not seconds.

1 J = 1 W·s = 1.16 × 10-5 W·h 1 W·h = 3600 J

Energy density of common fuels:

coal 2.9 × 107 J/kg = 8100 Wh/kg oil 4.3 × 107 J/kg = 12,000 Wh/kg gasoline 4.4 × 107 J/kg = 12,000 Wh/kg = 1.3 × 108 J/gallon natural gas 5.5 × 107 J/kg = 15,000 Wh/kg U235 (fission) 8.0 × 1013 J/kg = 22,000 MWh/kg

# If it takes 2 minutes to pump 15 gallons of gasoline into your car, at what rate

of power are you recharging your car’s energy supply? Amazingly enough, the energy content of all food sold in the U.S. is listed on the container (in Calories).

1 food Calorie = 1000 calories = 4180 J

Example: A Big Mac, large fries, and Coke = 1360 Calories = 5.7 MJ = 1,600 Wh

# Most people consume about 2000 Calories per day. What is the average power dissipation of a human being, in watts?


Lecture 1 3

Other forms of energy (remember freshman physics?):

Kinetic energy of a moving object = ½ mass x velocity squared

U = ½mv 2

Example: What is the kinetic energy in an 80-kg person walking at 1.0 m/s?

U = (1/2)(80 kg)(1 m/s)2 = 40 J = 11 mWh

Potential energy in a gravitational field = mass x gravitational acceleration x height

U = mgh

Example: What is the potential energy of a 5-kg rock one meter above the ground on Earth (g = 9.81 m/s2)?

U = (5 kg)(9.81 m/s2)(1 m) = 49 J = 14 mWh

# Suppose we have a box-shaped reservoir of width W, length L, and height H. If this reservoir is filled to the top with water, what is the total potential energy of that water with respect to the bottom of the reservoir? Assume the water has a density of ρ, and the gravitational constant is g.

Electrical potential is measured in volts, and is analogous to height in the previous case. Charge is analogous to mass. Electrical potential energy = charge x voltage.

U = QV

Example: A 5 V battery stores 1 kJ of energy. How many electrons with 5 V potential can this battery dispense before becoming depleted?

Q = U /V = 1000 J / 5 V = 200 C

Number of electrons = Q /q = 200 C / 1.6 x 10-19 C = 1.3 x 1021 electrons We can easily derive the expression for electrical power by noting that power is energy per unit time (1 W = 1 J/s), and current is charge per unit time (1 A = 1 C/s):

P = U /t = QV /t = (Q /t )V = IV


Lecture 1 4

Power Sources for Low-Power Devices Batteries – Most Common Power Source for Portable Electronics Batteries convert chemical energy into electrical energy by means of a reduction-oxidation (redox) reaction. Example: Alkaline cell operation

Load

Zn Anode MnO2 Cathode

ion-permeable insulating barrier

electrolyte (source of ions)

OH– ions

e– flow

current flow

OH–

OH– K+

K+

H2O

H2O

anode reaction (oxidation): Zn + 2 OH– →→→→ Zn(OH)2 + 2e–

cathode reaction (reduction): 2 MnO2 + H2O + 2e– →→→→ Mn2O3 + 2 OH–

electrolyte: KOH (K+, OH– in solution)

overall reaction: Zn + 2 MnO2 + H2O →→→→ Zn(OH)2 + Mn2O3

Electron flow (i.e., current) external to the battery balances internal ionic flow. Two classes of batteries:

• Primary batteries – Non-rechargeable • Secondary batteries – Rechargeable (Redox reaction can be driven

backwards)


Lecture 1 5

PRIMARY (NON-RECHARGEABLE) BATTERIES Type

Anode/Cathode/ Electrolyte

Open-Circuit Voltage (V)

Operating Voltage (V)

Energy Density (Wh/kg)

Energy Density (Wh/L)

Cost

Applications/Notes

Zinc-Carbon (“heavy duty” dry cell)

Zn/MnO2+C/ NH4CL, ZnCL2

1.5 1.5-1.0 60-100 100-170 lowest Older technology Sloping discharge curve

Alkaline Zn/MnO2/ KOH

1.5 1.5-1.1 130-180 320-440 low Most common primary battery Sloping discharge curve

Mercury

Zn/HgO/ KOH

1.35 1.3 100 450 high Cannot supply high current

Zinc-Air

Zn/Air/ KOH

1.5 1.3 340 1050 moderate Highest volumetric energy density

Silver (Silver Oxide)

Zn/Ag2O/ KOH

1.55 1.5 120 370-470 high Cannot supply high current Flat discharge curve

Lithium (many different types)

Li/various/ various

3.0-4.0 3.0 (typical) 230-380 440-850 high Very long shelf life (5-20 years), Flat discharge curve, Best at high and low temp.

SECONDARY (RECHARGEABLE) BATTERIES Type

Anode/Cathode/ Electrolyte

Open-Circuit Voltage (V)

Operating Voltage (V)

Energy Density (Wh/kg)

Energy Density (Wh/L)

Cost

Applications/Notes

Nickel-Cadmium (Nicad, Ni-Cd)

Ni/Cd/ KOH

1.2 1.2-1.1 35-45 100-120 moderate Commonly available 250-1000 recharge cycles Flat discharge curve

Nickel-Metal Hydride (NiMH)

Ni/ZrNi2 or LaNi5/KOH

1.2 1.2-1.1 40-70 130-210 high Replacing Nicads 500 recharge cycles Flat discharge curve

Lithium Ion

C/LiCoO2/ lithium salts

4.0 3.0 50-150 100-200 high 500-2000 recharge cycles Flat discharge curve

Lead Acid

PbO2/Pb/ H2SO4

2.1 2.0 30-40 100 moderate-high

250-1000 recharge cycles Flat discharge curve Very high currents possible


Lecture 1 6

Battery Types Grouped by Application Primary batteries

• General consumer electronics (portable audio equipment, toys, etc.) o Alkaline (Duracell, Energizer, etc.) – Standard AAA, AA, C, D, 9V cells o Zinc-Carbon (old technology, but cheap) – Standard AAA, AA, C, D, 9V cells

• Film cameras and flash units o Alkaline o Lithium

• Wristwatches o Silver – “Button” batteries

• Hearing aids o Zinc-Air – “Button” or “coin” batteries

• Smoke detectors o Mercury o Lithium

• CMOS memory backup o Lithium

• Medical implants (pacemakers, etc.) o Mercury – Used in implants before 1972 o Zinc-Air – Used in many modern implants o Lithium-SVO (silver vanadium oxide) – Used in implantable defibrillators,

where they can supply microamps for years and occasional amp-level pulses. Secondary batteries

• General consumer electronics (portable audio equipment, toys, etc.) o Nickel-Cadmium (Nicad) – Available in standard AAA, AA, C, D, 9V cells o Nickel-Metal Hydride (NiMH) – Available in standard AAA, AA, C, D, 9V cells

• Cell phones o Nickel-Metal Hydride (NiMH) o Lithium Ion

• Laptops o Nickel-Metal Hydride (NiMH) o Lithium Ion

• Palmtops o Lithium Ion

• Handheld video recorders o Lead acid (older models) o Lithium Ion

• Gasoline automobiles o Lead acid

• Electric/hybrid automobiles o Lead acid (General Motors EV1 electric car) o Nickel-Metal Hydride (NiMH) (newer EV1; Honda Insight hybrid gas/electric

car)


Lecture 1 7

A Battery is not an ideal voltage source! All batteries have a finite internal resistance (Rint). This causes the terminal voltage to drop as more current is drawn. Batteries with large internal resistances show poor performance in supplying high current pulses.

Battery Typical internal resistance of fresh battery 9V Zinc-Carbon 35 Ω 9V Lithium 16-18 Ω 9V Alkaline 1-2 Ω AA Alkaline 0.15 Ω (0.30 Ω at 50% discharge) AA NiMH 0.03 Ω (0.04 Ω at 50% discharge) D Alkaline 0.1 Ω D Ni-Cd 0.009 Ω D Lead-Acid 0.006 Ω AC13 Zinc-Air 5 Ω 675 Mercury 10 Ω 76 Silver 10 Ω

Internal resistance generally increases as the battery discharges. A typical alkaline “AA” battery starts with Rint = 0.15 Ω, but at 90% discharge, Rint = 0.75 Ω. Batteries are often rated with capacities in mAh or Ah. Multiply by battery voltage to get energy.

Example: “This 3 V battery has a capacity of 500 mAh @ 1 mA; 470 mAh @ 10 mA”

Sometimes capacity is expressed in terms of the C rate. The number following the letter C is the discharge time in hours.

Example: “This battery has a C/10 capacity of 2 Ah and a C/5 capacity of 1.8 Ah.”

! Note that these scales are typically nonlinear! The capacity typically decreases with increased current draw.

Typical battery energies Battery

Voltage (V)

Capacity (mAh)

Energy (Wh)

Energy density (Wh/kg)

Energy density (Wh/L)

AAA Alkaline 1.5 1,150 1.7 140 440 AA Alkaline 1.5 2,850 4.3 190 520 C Alkaline 1.5 8,000 12.0 180 440 D Alkaline 1.5 16,000 24.0 170 420 9V Alkaline 9 570 5.1 110 220 AA Carbon-Zinc (primary)

1.5

950

1.4

95

170

AA Alkaline (primary) 1.5 2,850 4.3 190 520 AA Lithium (primary) 1.5 2,900 4.4 290 520 AA Ni-Cd (secondary) 1.2 800 1.0 44 120 AA NiMH (secondary) 1.2 1,200 1.4 53 170 ! Secondary batteries provide only about 20-30% the energy density of primary

batteries!


Lecture 1 8

Other Power Sources for Low-Power Systems Solar Power

How much power is in sunlight? Maximum after traveling through the atmosphere: 1kW/m2 (noon, summer, cloudless day)

Night, full moon: 1 mW/m2

Average power per day: In middle latitudes (U.S., Europe, Japan, northern China, southern Australia), 100W/m2 in winter, 250W/m2 in summer.

Indoors: only 500-1000mW/m2

Typical solar cell efficiency: 10% (2-5% for inexpensive cells)

Example: If we use a small (10cm2) solar cell with 10% efficiency, indoors we can expect to get 500-1000µW, outdoors 1W under optimum conditions. Inductively-Coupled Power Link

Used in medical implants, radio-frequency identification (RF ID) tags, and smart cards. Alternating current through a large, external coil creates a magnetic field. The portable device has a small pickup coil that changes the magnetic field back into electric current. Basically a transformer with a small secondary coil.

In medical implants, an externally-powered coil is placed on or near the skin. The internal coil in the implant can power electronics directly (e.g., muscle stimulators) or recharge internal batteries (e.g., pacemaker). Vibration-Based Power Generation From: R. Amirtharajah and A.P. Chandrakasan (1998). Self-Power Signal Processing Using Vibration-Based Power Generation. J. Solid-State Circuits 33:687-695.

Using a 0.5g weight suspended from a spring, Amirtharajah and Chandrakasan estimate 400µW “best case” power generation during human walking.

Some recent wristwatches use a similar technique. Other possible power sources

• Thermal gradients • Fluid flow • Small fuel cells • Light sent through optical fibers • Micromachined batteries


Lecture 2 1

How can we lower power consumption? Power in electronic circuits is voltage times current (P =IV). In most circuits, the power supply voltage is constant. In circuits where the current varies with time, we must make a distinction between instantaneous power and average power.

time

curr

ent d

raw

n fr

om

pow

er su

pply

i(t)

Iavg = 1µA

Ipeak = 3µA power supply voltage = 2V

time

inst

anta

neou

s pow

er

diss

ipat

ion

p(t)

Pavg = 2µW

Ppeak = 6µW p(t) = i(t)v(t)

T

∫=T

avg dttpT

P0

)(1 if p(t) is periodic

Digital circuits typically draw current in bursts. By integrating instantaneous power over time, we can measure the energy associated with each burst:

time

inst

anta

neou

s pow

er

diss

ipat

ion

p(t)

Area under curve = energy (e.g., switching energy)

∫=2

112 )(

t

t

dttpU


Lecture 2 2

Power-Performance Tradeoffs What does additional power buy us? What aspects of circuit performance “cost” power? We’ll go into this in more detail later in the course, but for now let’s take an empirical approach…

Survey of 175 commercially-available integrated operational amplifiers:

Bandwidth vs. Power

0.01

0.1

1

10

100

1000

0.01 0.1 1 10 100 1000

Power (mW)

Uni

ty-G

ain

Ban

dwid

th (M

Hz)

There seems to be a very clear tradeoff between power and bandwidth!

Despite this tradeoff, there is a large variance among the designs. For amplifiers with approximately 1-MHz bandwidth, the power consumption varies between 0.3mW and 30mW – two orders of magnitude!


Lecture 2 3

This graph shows the noise spectral density of each amplifier vs. power consumption.

Noise vs. Power

0.1

1

10

100

1000

0.01 0.1 1 10 100 1000

Power (mW)

Noi

se @

1kH

z (n

V/ro

ot H

z)

There also seems to be a tradeoff between noise and power consumption. It seems we can “pay” for less noise with additional power.

Again, we see a large variance between designs. If look at amplifiers with around 30 nV/Hz1/2 noise spectral density, we see designs dissipating anywhere from 20µW to 50mW!

Some of this variance is caused by bandwidth differences in the amplifiers, but plenty of variance remains even when this is taken into account.


Lecture 2 4

This graph shows the maximum (open-loop) gain of each amplifier vs. power consumption.

Gain vs. Power

0

20

40

60

80

100

120

140

160

0.01 0.1 1 10 100 1000

Power (mW)

Gai

n (d

B)

Here, the trend is not as clear as in the previous two cases. If anything, gain decreases with increasing power consumption, but the slope is not very significant.

Unlike bandwidth and noise, gain does not seem to be a function of power consumption. Conclusion: Some performance parameters (e.g., bandwidth and noise) may cost us power. For a fixed level of power consumption, some circuits do a better job than others at achieving high bandwidth or low noise. Other performance parameters (e.g., gain) may not cost us power.

It is important to recognize these tradeoffs so that we don’t waste power by building circuits with more bandwidth (or lower noise) than we need for our application!


Lecture 2 5

Semiconductors – A Review Most VLSI circuits today are based on silicon (a semiconductor) and silicon dioxide (SiO2, a near-perfect insulator).

A silicon atom has four electrons in its outer shell. Since this shell has an 8-electron capacity, silicon atoms can fill their outer shell by forming bonds with four adjacent atoms.

Si

Si Si

Si

Si Si

Si

Si

Si

Si

Si

outer-shell electrons

When silicon forms a crystal lattice, all the silicon atoms are “happy” because they each have full outer shells (8 electrons). However, there are no free charge carriers, so no current can flow! All electrons are bound to nuclei.

Then why is silicon a semiconductor and not an insulator? Remember, at temperatures above absolute zero, atoms are being vibrated and shaken about. Occasionally, these atomic-scale vibrations (thermal energy) will shake an electron out of the crystal lattice. (An incident photon can also cause this to happen.) This is called generation, since a pair of charge carriers are generated.


Lecture 2 6

Si

Si Si

Si

Si Si

Si

Si

Si

Si

Si

Si

Si

Si

e- h+

In the absence of an electric field, this electron moves through the lattice in a “random walk,” bumped around by thermal energy. We call this electron a “carrier” since it is now free to move and thus carry current.

The “hole” left by escaped electron has a positive charge since there is one less electron than the surrounding protons in the silicon nuclei. It is very easy for a nearby electron to shift over into this hole. Of course, this just moves the hole. Thus, the hole is mobile (just like an air bubble in water) and acts as a positively-charged carrier.

So carriers are generated in pairs: one electron and one hole. If a hole and electron meet, the electron “falls into the hole”, filling it. The hole is gone because it has been filled without creating another hole, and the free electron is no longer a carrier because it is now reattached to the lattice. This electron-hole annihilation is called recombination.

Si

Si

Si

Si

Si

Si

Si

Si

e-

h+

Si

Si

Si

Si

Si

Si

Si

Si

recombination


Lecture 2 7

At room temperature (300°K), a pure (“intrinsic”) silicon crystal has around 1.5 x 1010 “free” electrons per cubic centimeter, and an identical number of holes. This is why silicon is a semiconductor – the electrons in its crystal lattice can be shaken free fairly easily.

This may sound like a lot of electrons running around, but consider this: There are 5 x 1022 silicon atoms per cubic centimeter. This means that only one out of every 3 trillion atoms has an missing electron at any point in time!

So far, all we have is a resistor whose resistance decreases as we raise the temperature. Things get more interesting if we dope a silicon crystal – add impurities.

Suppose we add a few phosphorous (P) atoms to our silicon crystal. Phosphorous atoms are similar in size to silicon atoms, but they have five outer-shell electrons. This extra electron doesn’t fit neatly into the lattice, and it is very easily knocked around by thermal energy. Phosphorous is a donor, since it “donates” extra electrons to the crystal.

Si

Si Si

Si

Si Si

Si

P

Si

Si

Si

Si

Si

Si

e-

+

If this electron moves away from the donor atom, there will be a net positive charge on the phosphorous nucleus, since it needs five electrons in its outer shell to maintain charge neutrality. Unlike a hole, however, this positive charge due to the phosphorous nucleus is fixed to the lattice and cannot move.


Lecture 2 8

Si

Si Si

Si

Si Si

Si

P

Si

Si

Si

Si

Si

Si

e-

+

Silicon doped with donor atoms in known as n-type silicon because of the added negative charge carriers. Typical doping levels are 1015 – 1020 dopants per cubic centimeter (one dopant atom per 102-107 silicon atoms), which greatly overwhelms the intrinsic thermally-generated carriers (1.5 x 1010cm-3).

What if we dope silicon with an atom having three electrons in its outer shell, such as boron (B)?

Si

Si Si

Si

Si Si

Si

B

Si

Si

Si

Si

Si

Si

h+

-

Boron doesn’t fit cleanly into the silicon lattice either; it has one too few electrons, so there is a hole next to the boron nucleus. Boron is called an acceptor because it accepts electrons (into this hole). Equivalently, it donates extra holes to the crystal.


Lecture 2 9

If this hole moves away from the acceptor atom, there will be a net negative charge on the boron nucleus, since it needs three electrons in its outer shell to maintain charge neutrality and now has four. Unlike an electron, however, this negative charge due to the boron nucleus is fixed to the lattice and cannot move.

Si

Si Si

Si

Si Si

Si

B

Si

Si

Si

Si

Si

Si

h+

-

Silicon doped with acceptor atoms in known as p-type silicon because of the added positive charge carriers (i.e., holes). As in n-type silicon, typical doping levels greatly overwhelm the intrinsic thermally-generated carriers.


Lecture 2 10

Now let’s look at a different way of graphically representing doped (extrinsic) silicon:

• We will stop drawing all the silicon atoms and lattice bonds, because these objects have no net charge and cannot move.

• We will draw mobile electrons and holes as plus and minus signs (+ and -)

• We will draw donors atoms as a plus sign with a circle around it, and acceptor atoms as a minus sign with a circle around it. The circle reminds us that these charges cannot move.

n-type silicon p-type silicon intrinsic (undoped)

silicon

Notice that each piece of silicon is electrostatically neutral on the macroscopic level; there are equal numbers of positive and negative charges.

Also notice that even the n-type silicon has a very small concentration of holes due to thermal generation. The same goes for electrons in the p-type silicon.

What happens if we take a piece of p-type silicon and attach it to a piece of n-type silicon?


Lecture 3 1

p-n Junctions

An n-type piece of silicon has many free negative charges (electrons) and an equal number of fixed positive charges due to the dopant atoms. There will also be a tiny number of free electrons and holes generated thermally. The positive and negative charges balance each other out.

Conversely, p-type silicon has many free positive charges (holes) and an equal number of fixed negative charges.

What happens if we take a piece of p-type silicon and attach it to a piece of n-type silicon, forming a p-n junction?

n-type silicon p-type silicon

Both pieces of silicon were (and still are) electrostatically neutral, so there is no electric field to pull electrons or holes one way or the other. The carriers are moving around randomly with thermal energy. So what happens?

There are two mechanisms for carrier (electron or hole) motion: drift and diffusion.

• Drift requires an electric field.

• Diffusion requires a concentration gradient.


Lecture 3 2

Diffusion What are the mechanisms of carrier (electron or hole) motion in the absence of an electric field? Don’t they just move randomly in an unpredictable manner? Random: yes. Unpredictable: no.

Consider the divided tank shown below. It is filled with water on both side, and particles are mixed into one side.

x centroid of

particle density

particle density

Now we remove the barrier…

x centroid of

particle density

particle density


Lecture 3 3

Observation: Although each particle moves in an unpredictable fashion, as a group their behavior is predictable. The particles move from an unlikely arrangement (all the particles on one side of the tank) to a much more likely arrangement (fairly evenly distributed). This is just the second law of thermodynamics – entropy must increase!

The Diffusion Equation in 1-D On average, particles move away from areas of high concentration and into areas of low concentration.

If we express particle concentration (density) at point x as c(x), then the particle flux (particles per second per unit area passing point x) is given by:

( ) ( )dx

xdcDx −=φ

where the constant D is called the diffusion coefficient.

The concept of particle flux is illustrated below. If we count the number of particles passing through the shaded region each second and divide by the area of the region, this gives us flux. The unit for flux is cm-2s-1 (particles per second per unit area).


Lecture 3 4

The electron flux (electrons per area per second passing point x) φn(x) is given by:

( ) ( )dx

xdnDx ndiffusionn −=−φ

where n(x) is the electron density at position x and Dn is the diffusion coefficient for electrons. The quantity dn(x’)/dx represents the electron concentration gradient in the x direction at point x’.

The hole flux is given by:

( ) ( )dx

xdpDx pdiffusionp −=−φ

where p(x) is the hole density at position x and Dp is the diffusion coefficient for holes. The quantity dp(x’)/dx represents the hole concentration gradient in the x direction at point x’.

Since p(x) and n(x) have units of cm-3 and flux has units of cm-2s-1, the unit of the diffusion coefficient is cm2/s.

Drift In the presence of an electric field, charged particles exhibit drift. If a particle with charge q is placed in an electric field E, it experiences a force:

qEF =

Using Newton’s second law (F = ma), we find that the particle undergoes an acceleration:

Emqa =

So a charged particle in a constant electric field should accelerate continuously…


Lecture 3 5

Inside the crystal lattice of silicon, however, the story is different. Accelerating particles are always colliding with the lattice and loosing energy. The situation is similar to the microscopic collisions that result in mechanical friction. When we apply a constant, horizontal force to a block of wood on a table, it doesn’t accelerate without limit, even though Newton’s law predicts this will happen. Rather, it quickly reaches a constant velocity where the frictional forces balance our applied force. In other words, when friction (millions of microscopic collisions) is involved, a constant force produces a constant velocity, roughly (no pun intended).

Electric Field

acceleration… lattice

collision

t

average velocity ⟨v⟩

hole velocity

v

This is certainly the case for charged particles in a solid piece of silicon. While each electron is bouncing around, colliding with the lattice, it is observed experimentally that electrons travel at an average velocity proportional to the electric field:

xnx Ev µ−=

Here, Ex represents the electric field in the x direction, and ⟨vx⟩ is the electron’s average velocity in the x direction. The constant of proportionality µn is called the electron mobility, and is obtained empirically.


Lecture 3 6

The average velocity of holes is observed to be:

xpx Ev µ=

Notice that two things are different here from the previous equation. First, the sign has reversed, indicating that holes have a positive charge and thus travel in the opposite direction of negatively-charged electrons. Second, there is a different constant of proportionality, µp, called the hole mobility.

Of course, this tells us that the mobility of electrons and holes is different. If it was the same, we wouldn’t bother with the subscripts. As you might expect, free electrons squeezing through the crystal lattice are more mobile than holes, which move when a bond switches from one atom to another.

In silicon, electron mobility is typically three times larger than hole mobility.

Mobility is a function of doping density. Ionized dopant atoms are very effective at interfering with the path of a drifting carrier. Mobility decreases with increasing dopant concentration (in a rather complex way).

Mobility is also a function of temperature. The lattice offers more resistance to drifting carriers when it has more thermal energy. Mobility drops with increasing temperature. (It is observed that mobility is proportional to T -3/2 at room temperature and higher.)

Since electric field strength has units of V/cm and velocity has units of cm/s, the unit for mobility is cm2/V⋅s.

Electron and hole flux due to drift can be written as:

( ) ( ) ( )xExnx ndriftn µφ −=−

( ) ( ) ( )xExpx pdriftp µφ =−

where n(x) and p(x) are the densities of electrons and holes, respectively, at point x.


Lecture 3 7

The Einstein relation Mobility and diffusion constants are not independent quantities. If we know one, we can compute the other:

µq

kTD = (the Einstein relation)

where k is Boltzmann’s constant (k = 1.38 x 10-23 J/K), and the quantity kT/q, often called the thermal voltage, is approximately 26 mV at room temperature.

Back to the p-n Junction… Now we have the concepts necessary to understand the behavior of carriers in a p-n junction. While there is no drift initially, there are large hole and electrons concentration gradients, giving rise to carrier diffusion. However, as these opposite charge carriers diffuse together, they annihilate one another (recombination), leaving behind a region depleted of carriers – a depletion region.

p-type silicon n-type silicon

depletion region (no carriers)

x

net c

harg

e de

nsity

Inside the depletion region, the fixed dopant ions are “uncovered,” revealing a net, fixed charge. Now we have an electric field! What happens next?


Lecture 3 8

Electrostatics in 1-D

We need to get a bit more quantitative with regards to charge density and the resulting electric fields. The following two equations take us from charge density ρ to electric field strength E to potential ψ:

( )ε

ρ xdxdE = (Poisson’s equation)

( )xEdxd −=ψ

where

0εε Sik= (permittivity of silicon)

F/cm1085.8 140

−×=ε (permittivity of free space)

8.11=Sik (dielectric constant of silicon)

Charge density ρ has units of C/cm3, and electric field strength E has units of V/cm. We see from Poisson’s equation that charge density divided by permittivity gives us units of C/F⋅cm2. Since 1 F = 1 C/V, we end up with units of V/cm2, which is correct for electric field gradient dE/dx.

We can also express these two equations in integral form:

( ) ( ) ( )∫=− 2

1

112

x

xdxxxExE ρ

ε

( ) ( ) ( )∫−=− 2

112

x

xdxxExx ψψ (∆Energy = Work = ∫ Force)


Lecture 3 9

Here’s a graphical example of how electric field strength and potential (voltage) is computed for a particular charge distribution. Let’s assume we build a p-n junction from p-type silicon having an acceptor doping density of NA and n-type silicon having a donor doping density of ND (units of cm-3).

x

charge density (C/cm3)

ρ (x)

x

E(x)

x

ψ (x)

electric field (V/cm)

potential (V)

+qND

-qNA

V0

We’ll assume that a p-n junction gives us a “rectangular” distribution of charge as shown above.

The electric field is the integral of the charge density. It decreases linearly in regions of constant negative charge density and increases linearly in regions of constant positive charge density. Another way of looking at this is noticing that the slope of the electric field is given by the charge density.

The potential is the integral of the electric field (with a negative sign). It increases more rapidly when the electric field is stronger. Another way of looking at this is noticing that the slope of the potential is given by the electric field (multiplied by –1).


Lecture 3 10

Now we can identify the diffusion and drift current associated with a p-n junction. From the previous diagram, we see that while the electric field strength varies in the depletion region, it is always negative. This sets up the following situation:


electric field

hole diffusion electron diffusion

hole drift

electron drift

current due to diffusion

current due to drift

With no external voltage applied to the p-n junction, the diffusion and drift currents balance exactly, and there is no net current flow.

We can quantify these various currents using the previous equations for drift and diffusion flux, and calculating current from flux:

pp qAI φ=

nn qAI φ−=

Holes generate current in the direction of hole flux. Electrons generate current opposite to the direction of electron flux, since current is defined as the movement of positive charge.

Remember, the unit of flux is cm-2s-1. If we multiply by charge (C) and area (cm2), we get C/s, or amps.


Lecture 3 11

Thus, the currents can be expressed as:

( ) ( ) ( )[ ]xxqAxI diffusionndiffusionpdiffusion −− −= φφ

( ) ( )dx

xdnqADdx

xdpqAD np +−=

( ) ( )

−=

dxxdpD

dxxdnDqA pn

( ) ( ) ( )[ ]xxqAxI driftndriftpdrift −− −= φφ

( ) ( ) ( ) ( )xExnqAxExpqA np µµ +=

( ) ( ) ( )[ ]xnxpxqAE np µµ +=

( ) ( ) ( )xIxIxI driftdiffusiontotal +=

By applying an external voltage (a bias), we can modulate the width of the depletion region and cause diffusion or drift current to dominate. The result is a net current flow:

p n

diffusion current

drift current

depletion region

Equilibrium (V = 0)

p n

diffusion current

drift current

Forward bias (V = Vf)

Vf

p n

diffusion current

drift current

Reverse bias (V = -Vr)

Vr

V0 V0 - Vf V0 + Vr


Lecture 3 12

Leakage Current in a p-n Junction What if an electron-hole pair is generated (thermally, or by a photon) inside the depletion region?


electric field

current Any carriers finding themselves in the depletion region are quickly swept away by the strong electric field, leading to drift-based current. When the p-n junction is reverse-biased, this tiny drift current dominates and is commonly called leakage current.

Leakage current is weakly affected by the reverse bias voltage, which increases the strength of the electric field in the depletion region. It is strongly affected by temperature and light, both of which generate more carriers in the depletion region. Leakage current doubles with every 11°C (20°F) increase in temperature. Leakage current is directly proportional to light intensity, and this is the operational basis for photodiodes.

p

n

I

small leakage current

p

n

I

weak voltage

dependence

p

n

I

strong temperature dependence

p

n

I

strong light

dependence


Lecture 3 13

Asymmetrical Junctions Heavily doped silicon is denoted n+ or p+, and weakly doped silicon is denoted n- or p-. Notice that the superscripts have nothing to do with positive or negative charge; they only indicate dopant concentrations above or below “average,” whatever we define average to be.

In CMOS transistors, we will often encounter asymmetrical p-n junctions: either p+-n- or n+-p- junctions. Let’s take a look at one such junction:

p+ silicon n- silicon


x

net c

harg

e de

nsity

areas are equal

An equal number of dopant ions are uncovered on each side of the junction, maintaining charge neutrality. Notice that the depletion region extends further into the more weakly-doped silicon. In the extreme case where the higher dopant concentration is orders of magnitude higher than the lower dopant concentration, the depletion region will exist almost entirely in the weakly-doped region. Only a thin sliver of the heavily-doped region will be depleted.


Lecture 3 14

Charge density, electric field, and potential profile for an asymmetric p-n junction:

x


ρ (x)

x

E(x)

x

ψ (x)


potential (V)

+qND

-qNA areas are

equal


Lecture 4 1

Charge Storage: Capacitance

Capacitance is the relationship between charge and voltage. Capacitance is defined as the incremental change in stored charge resulting from an incremental change in voltage:

VQC

∂∂≡

A parallel-plate capacitor is a linear capacitor. That is, it’s capacitance is constant, and does not depend on the voltage across it or the charge it is holding.

For a linear capacitor, Q = CV; the charge stored on each plate is directly proportional to the voltage across the plates.

E 1V E 2V

V

Q

slope = C


Lecture 4 2

Let’s take a look at the fields and potentials in a parallel-plate capacitor:

x


ρ (x)

x

E(x)

x

ψ (x)


potential (V)

+Q

-Q

-Q εox

Qtox εox VC = = Q

C’

tox

In CMOS technology, almost all capacitors use silicon dioxide (SiO2) as the insulator. The capacitance of an “oxide capacitor” is given by:

ox

oxox t

ACε

=

where

0εε oxox k= (permittivity of oxide [SiO2])

F/cm1085.8 140

−×=ε (permittivity of free space)

9.3=oxk (dielectric constant of SiO2)

Sometimes it is handy to use capacitance per unit area, C’:

ox

oxox t

Cε

=′


Lecture 4 3

Example: In a modern 0.35µm CMOS process, the gate oxide thickness is around 80Å = 8nm (1Å = 10-10m). This gives us a capacitance per unit area of 430nF/cm2. Since we will build structures on the micron level, it is more useful to convert this number to 4.3fF/µm2.

Remember:

1 pF (picofarad) = 10-12F 1 fF (femtofarad) = 10-15F 1 aF (attofarad) = 10-18F

If we build a 20µm x 20µm capacitor using gate oxide, we can obtain a capacitance of 1.7pF.

Typical values of integrated (on-chip) capacitors range from 50fF (0.05pF) to 50pF.

Below 100fF, parasitic capacitances can dominate. (More on these later.) Capacitors over 5pF begin to consume quite a bit of area.

For example, if we build a minimum-length transistor with moderate width (W/L = 10) in 0.35µm technology, its gate area will be 3.50µm x 0.35µm = 1.2µm2. A good rule of thumb when designing VLSI circuits is that the total area of the circuit will be approximately 2-3 times the total gate area of all the transistors. This extra area is consumed by source/drain regions, wires, and spacing between transistors. So let’s assume that each transistor will consume about 3µm2 of silicon. How big is a capacitor, in terms of transistors? Since our gate capacitance is 4.3fF/µm2, this works out to 13fF/(transistor area). So a 10pF capacitor takes up as much room as 770 transistors! Capacitance is expensive in terms of silicon area!

The situation gets worse if we can’t use gate oxide to build capacitors. Gate oxide capacitors have a semiconductor as their bottom plate (they are often called MOS capacitors or MOScaps), and this can result in nonlinear behavior. Linear capacitors are often built between two layers of polysilicon (“poly1” and “poly2”), but the oxide between these layers is thicker than the gate oxide. In the 0.35µm process mentioned above, the gate oxide capacitance is 4.3fF/µm2, while the poly1/poly2 capacitance is only 0.8fF/µm2! Using our previous assumptions, this works out to 2.4fF/(transistor area), so a 10pF capacitor takes up as much room as 4200 transistors!


Lecture 4 4

The Capacitance of a p-n Junction

A p-n junction stores charge and has a potential difference across it, so it must have a capacitance. Let’s consider the case of a reverse-biased p-n junction – the kind we will encounter most often in CMOS design.

Below is the familiar picture of the charge stored in a p-n junction. Now we are using even more shorthand when we draw our cartoons: We will no longer show the p and n regions outside of the depletion region, because these regions are neutral (have no net charge):



x

net c

harg

e de

nsity

We’ve also added dotted lines to show the boundaries of the depletion region. This will come in handy later.

To calculate the capacitance of this junction, we have to find an expression relating charge to voltage. Since this junction is symmetric, we can make things easier by finding the voltage drop across one half of the junction and then multiplying by two.


Lecture 4 5

Let’s assume the total charge in the p part of the junction is doped with an acceptor density of NA (units cm-3). This means the charge density in the depletion region is qNA. The junction has a cross-sectional area of A.

We can calculate the electric field E(x) and the potential ψ(x):

( ) ( )∫ ∫ −=−== xqNdxqNdxxxE AA

εεερ

( ) ( ) ∫∫ ==−= 2

2xqNxdxqNdxxEx AA

εεψ

Assuming the width of this half of the depletion region is W, we can calculate the voltage drop across the entire junction, which is equal to the junction’s built-in potential V0 plus the reverse bias Vr:

( ) 20 2 WqNWVV A

r εψ ==+

The total depletion charge on one side of the junction is given by:

AWqNQ A−=

which we can rearrange to give us width as a function of charge:

AqNQW

A

−=

Now we can find an expression relating charge to voltage:

2

22

0 ANqQWqNVV

A

Ar εε

==+

( )rA VVNqAQ += 0ε

V

Q

slope = C(V)


Lecture 4 6

Now we can find the junction capacitance:

r

A

rj VV

NqAVQC

+=

∂∂≡

02ε

The capacitance changes with the voltage across it, so this is a nonlinear capacitor. The junction capacitance per unit area is given as:

r

Aj VV

NqC+

=′02

1 ε

For the more general case where NA ≠ ND, it can be shown that:

AD

AD

rj NN

NNVV

qC++

=′0

221 ε

Often, this is written as:

0

0

1VV

CC

r

jj

+

′=′

where C’j0 is the capacitance per unit area when Vr = 0:

AD

ADj NN

NNVqC

+=′

00

221 ε

In the case of an asymmetric p+-n- junction, where NA >> ND, we get:

r

Dj VV

NqC+

=′0

221 ε


Lecture 4 7

Incidentally, we can compute the p-n junction’s built-in potential V0 (sometimes called Φ0) from doping parameters:

200 lni

DA

nNN

qkTV =Φ=

where ni is the intrinsic carrier concentration for silicon: 1.5 x 1010cm-3 at room temperature (and highly dependant on temperature). V0 is typically in the range of 0.7-0.9V.

Example: The n+ drain region of an nMOS transistor forms an asymmetric junction with the p- substrate. The drain has dimensions of 7µm x 2µm. The substrate doping level is NA = 1016cm-3, ND >> NA, and V0 = 0.8V. The substrate is at ground. What is the drain-to-substrate “parasitic” capacitance for Vdrain = 0V, 1V, and 5V?

A = 7µm x 2µm = 14µm2

r

Aj VV

NqAC+

=0

22

ε

Cj(Vdrain = 0V) = 4.5fF



n+

p-

Cj

Vdrain

depletion region


Lecture 4 8

The MOS Capacitor

Suppose we build a parallel-plate capacitor where one plate is metal, one plate is a semiconductor (e.g., weakly-doped silicon), and the insulator is SiO2. Such a device is called a MOS (metal-oxide-semiconductor) capacitor. The metal plate is called the gate, and is not always built out of metal. Nowadays, gates are made from heavily-doped polycrystalline silicon (or “polysilicon,” or just “poly”). Polysilicon does not have a rigid crystal lattice, and conducts current freely, acting almost like a metal.

The MOS capacitor has several distinct regions of operation. For our example, we will consider a MOS capacitors build with p- silicon.

With no external voltage placed across it, the MOS capacitor is in the flat band region (ignoring work functions and implanted fixed charge). If we lower the voltage on the gate (by introducing negative charges), we attract “extra” holes (above the background level of holes in the p- silicon) which accumulate on the surface of the silicon. This creates a thin p+ region near the silicon-oxide interface.

p- silicon

SiO2

metal

p- silicon

SiO2

metal

p+ region

flat band accumulation

holes accumulate near the top

In the accumulation regime, MOS capacitors act as linear capacitors since the p+ region acts as a highly conductive “bottom plate.”


Lecture 4 9

If instead we raise the gate voltage (by introducing positive charges), we “scare away” holes in the p- silicon. This depletes the surface of holes, creating a depletion region with exposed negative dopant ions.

p- silicon

SiO2

metal

p- silicon

SiO2

metal

depletion region

flat band depletion

holes are repelled, depleting the top

As we have seen, the depletion capacitance is nonlinear, so a MOS capacitor operating in this regime is not very linear. It can be modeled as two capacitors in series: a linear oxide capacitance and the nonlinear depletion capacitance. Thus, the total capacitance is less than the oxide capacitance.

Due to contact potentials between the substrate and gate, MOS capacitors are typically in the depletion region when the gate and substrate are at the same potential.


Lecture 4 10

As we continue to raise the gate voltage, the depletion region cannot provide enough negative charges to match all the positive charges we are putting on the gate. Eventually, these positive charges begin to “pull” electrons from bonds, producing mobile electrons which balance the charge. (The missing bond electrons are quickly replaced from below.)

p- silicon

SiO2

metal

p- silicon

SiO2

metal

n region

weak inversion strong inversion The production of mobile electrons begins to invert the silicon at near the surface – it changes it from p-type silicon to n-type silicon! When the number of mobile electrons (the inversion charge) is much lower than the number of exposed dopant ions in the depletion region (the depletion charge), we are in the regime of weak inversion. When the inversion charge greatly exceeds the depletion charge, we have strong inversion, and a conductive n+ layer forms at the surface of the semiconductor.

When the inversion charge and depletion charge are comparable, we are in a regime know as moderate inversion.

p- silicon

SiO2

metal

moderate inversion


Lecture 4 11

The Hydraulic Analogy of Charge

As we explore the operation of transistors, it will be useful to observe the analogy between electricity and water. While this analogy shouldn’t be taken too far, it is surprisingly versatile.

For example, we can draw an analogy between charge storage devices (capacitors) and water storage devices (reservoirs).

C

V Q Q = CV h V

mass = m charge = q

U = mgh U = qV

“ground”

The energy stored in a capacitor can be calculated using the hydraulic analogy. A water molecule with mass m at height h above the ground has a potential energy of U = mgh. Analogously, a particle with charge q and potential V has an energy of U = qV. Calculating the total energy in a capacitor is analogous to calculating the total potential energy of water in a reservoir.

In a “charge reservoir” with capacity C, a thin slice of charge (thickness = dv) at height v contains a total charge equal to Cdv, and thus has a potential energy of Cdv⋅v. Integrating this from v = 0 to v = V, we get

∫ ==⋅=V V

CVCvdvCvU0

2

0

2capacitorlinear 2

121

which is the familiar expression for energy stored in a capacitor.


Lecture 4 12

If we think of current as a stream of water, we can find an analogy for the familiar equation describing capacitor charging and discharging:

dtdVCi =

C

V Q

I

dV dt

I C =

dQ dt = I

C

V Q

I

dV dt

-I C =

dQ dt = -I

It’s easy to see that a larger capacitor (larger reservoir area) will take longer to charge (fill) given a fixed current.

Now we understand the building blocks of CMOS transistors:

• p-n junctions

• MOS capacitors


Lecture 5 1

The MOS Transistor in Strong Inversion

In this section, we shall explore the behavior of the MOS transistor when the area under the gate – the channel – is strongly inverted. Strong inversion is shown below for a MOS capacitor.

p- silicon

SiO2

metal

Inversion layer charge QI

Gate charge QG

Depletion (“bulk”) charge QB

Surface potential ψs

Oxide potential ψox

Gate-to-bulk voltage VGB

The gate-to-bulk voltage VGB can be decomposed into the potential across the oxide (ψox) and the surface potential of the silicon substrate (ψs).

Ignoring any implanted charge or contact potential effects, the charge on the gate (QG) must be balanced out by the charge in the channel. The channel charge consists of the fixed depletion or “bulk” charge QB and the mobile inversion layer charge QI:

BIG QQQ +=

As we saw last time, the charge in a uniformly-doped depletion region is proportional to the square root of the voltage across it:

sAB NqQ ψε2−=′

In strong inversion, the inversion layer charge far surpasses the depletion charge.

BI QQ >> in strong inversion


Lecture 5 2

Depletion Weak inversion

Moderate inversion

Strong inversion

ψs

|QI|

|QB|

In strong inversion, the gate charge is balanced out primarily by the inversion layer charge. The voltage at which inversion layer charge dominates is called the threshold voltage VT. The symbol VT0 will often be used, and this indicates the threshold voltage when the source voltage equals zero (more on this later).


Moderate inversion

Strong inversion

VGB VT0

slope = Cox

|QI|

( )0TGBoxI VVCQ −′−≅′ in strong inversion


Lecture 5 3

Of course, to make a transistor we need more than a gate; we also need a source and a drain. Charge carriers flow through the channel (under the gate) from the source to the drain.

An n-channel MOSFET (“nMOS transistor” or “nFET”) is shown below. Notice that an n-channel FET actually has a channel made of weakly-doped p-type silicon. However, when the transistor conducts current, this channel is inverted, and is thus n-type.

p- silicon

SiO2

poly-Si

n+ n+

GATE

BULK or SUBSTRATE

DRAIN SOURCE L

W tox

p+ silicon

Electrons carry charge in nFETs (since the inverted channel is n-type). Since electrons flow from the source to the drain, current flows from the drain to the source.

The channel has a width W and a length L. The width-to-length ratio (“W/L ratio”) is an important parameter in MOSFET operation, as we shall see.

The complementary type of MOSFET is a p-channel MOSFET (“pMOS transistor” or “pFET”). This is shown below. Although the channel is made from n-type silicon, it becomes p-type when inverted.


Lecture 5 4

p- silicon

SiO2

poly-Si

p+ p+

GATE

BULK or SUBSTRATE

DRAIN SOURCE L

W tox

n-

n+

WELL

p+ silicon

In a complementary-MOS (CMOS) process where both nFETs and pFETs can be built, one of the two devices must be built in a well whose doping is opposite that of the substrate. In most processes nowadays, p- substrates and n- wells are used, so that pFETs reside inside wells.

The substrate is always set at the lowest potential used in the circuit (usually called ground or VSS) so that the nFET source/drain regions stay reverse-biased. Likewise, the wells are usually set to the highest potential used in the circuit (usually called VDD) so that the pFET source/drain regions stay reverse-biased.

If we place a metal wire (aluminum is used in most VLSI processes) directly against a semiconductor, we get a rectifying contact – a Schottky barrier diode. This is obviously not what we want when we tie a wire to our transistor. One way to avoid this diode is to connect metal only to heavily-doped (n+ or p+) regions. This forms a nonrectifying ohmic contact with a typical resistance of a few tens of ohms. This explains why we connect to the well via a n+ well contact region and connect to the substrate via a p+ substrate contact region.


Lecture 5 5

Now let’s take a look at an nFET with a gate voltage below VT (subtheshold). The only charge in the channel is due to the depletion region, which also extends around the source and drain p-n junctions. (For now, we will neglect the small number of mobile electrons present in this condition.)

p- silicon

SiO2

poly-Si

n+ n+

VD = 0V

VG = VT0 – 1V

VS = 0V

VB = 0V

Now, if we raise the gate voltage above the threshold voltage VT, we create an inversion layer of mobile electrons that balance out most of the gate charges:

p- silicon

SiO2

poly-Si

n+ n+

VG = VT0 + 1V

VB = 0V

VS = 0V VD = 0V

The charge in the inversion layer is proportional to the effective voltage Veff.

TGSeff VVV −=

effoxI VCQ ′−≅′ in strong inversion


Lecture 5 6

We can represent the channel charge with a simple fluid model:

VGS VT

VS VD VG

elec

tron

ener

gy

volta

ge

reference voltage

Here, the channel is represented by a barrier whose width corresponds to the channel’s length. The barrier can be moved up and down by means of a handle placed some distance below the top. Water on either side of the barrier represents the electrons in the source and drain. Since electrons have negative charge, the voltage scale is inverted; increasing voltage is in the downward direction.

Let’s consider the case where VS = VD. When the barrier is above the water level (i.e., VGS < VT), the source and drain tanks are separated, and no water flows. There is no channel charge (water above the barrier).

VGS VT

VS VD

VG

Veff elec

tron

ener

gy

volta

ge

reference voltage

When the barrier is pulled below the source/drain water level (i.e., VGS > VT), water flows in and fills the channel. The water in the channel (representing the channel charge) is proportional to Veff. Of course, there is no net water flow here since the source and drain water levels are equal.


Lecture 5 7

Now, if we lower the level of the drain tank (i.e., raise the drain voltage VD), water flows from the source to the drain. It is clear to see that two things would allow more water to flow: lowering the barrier (i.e., increasing the gate voltage VG) or increasing the difference between the source and the drain water levels (i.e., raising the drain-to-source voltage VDS).

VGS

VT

VS VD

VG

Veff

elec

tron

ener

gy

volta

ge

reference voltage

What if we continue to lower the drain water level (i.e., raise the drain voltage) to the point where VDS > Veff ? In this case, the water over the channel goes almost to zero at the drain edge, and we create a “waterfall” that spills into the drain tank. Notice that the rate of water flowing across the barrier (i.e., the channel current) is independent of the drain water level! We can still increase the channel current by raising the source level (i.e., lowering the source voltage) or lowering the barrier (i.e., raising the gate voltage).

elec

tron

ener

gy

volta

ge

reference voltage

VGS

VT

VS

VD VG

Veff


Lecture 5 8

Now let’s return to our cross-section of an actual nFET and observe the channel in strong inversion when VD > VS:

p- silicon

SiO2

poly-Si

n+ n+

VG = VT0 + 1V

VB = 0V

VS = 0V VD = 0.5V

Notice that the depletion layer widens towards the drain since the drain p-n junction is more strongly reverse-biased than the source p-n junction. More importantly, the inversion layer contains more charge towards the source. Why is this?

Near the source, the channel potential (surface potential) VC is approximately equal to VS. Near the drain, the channel potential is approximately equal to VD. Since VS is lower than VD, the voltage across the oxide is greater near the source, and charge is proportional to voltage in a parallel-plate capacitor. We can write the charge at position x under the channel as:

( ) ( )[ ]dxVxVVCWxQ TCGSoxI −−′=

Where the source is at x = 0 and the drain is at x = L.

This non-uniform distribution of charge creates an electric field along the channel, sweeping electrons from the source to the drain. The current at each point in the channel is given by:

( ) ( )xExQI nID µ=

The current is just the charge multiplied by its velocity, which is the electric field strength multiplied by the mobility. The electric field is spatial derivative of the channel voltage, so we can write the channel current as:

( )[ ] ( )dx

xdVVxVVCWI CnTCGSoxD µ−−′=


Lecture 5 9

Now we solve for ID using the boundary conditions VC(0) = VS and VC(L) = VD. Assuming for now that VS = 0, we get:

( )[ ] CTCGSoxn

V

V

L

xD dVVxVVCWdxI

DS

−−′= ∫∫−=

µ00

( )

−−′= 2

21

DSDSTGSoxnD VVVVL

WCI µ

This is the familiar MOS transistor equation valid in strong inversion (VGS > VT).

For small VDS [VDS << 2(VGS – VT)], the VDS2 term is very small, and we can make

the following approximation:

( ) DSTGSoxnD VVVL

WCI −′≈ µ

on

DS

RV

≈

where

( )TGSoxn

on

VVL

WCR

−′=

µ

1

In other words, for small drain-to-source voltages, the MOSFET behaves like a resistor. The resistor’s value decreases as we increase the gate voltage. This is not at all surprising since that increases the amount of inversion charge. This also makes sense when we look back at the fluid model.

Now let’s return to the original MOSFET equation:

( )

−−′= 2

21

DSDSTGSoxnD VVVVL

WCI µ

When VDS = VGS – VT, ID is maximum:

( )2max, 2

1TGSoxnD VV

LWCI −′= µ

Here, QI goes to zero at the end of the channel since VD = Veff. Wait a minute: How can the transistor conduct if there is zero charge at the end of the channel? Well, the charge doesn’t go exactly to zero, but it is quite small, which means the charge is moving extremely fast – the electric field is very strong here.


Lecture 5 10

Look back at the fluid model where VDS > Veff. The slope of the water level corresponds to the electric field strength. The water is moving fastest at the “pinch off” point adjacent to the drain. In fact, this condition in transistors is called pinch off.

What happens if we increase VD further? When VD > Veff, do positive charges accumulate in the channel? No. In fact, very little changes beyond this point, as the fluid model makes clear. The drain becomes “disconnected” from the channel, meaning that changes no in drain voltage no longer affect channel current (to first order).

So the equation we derived for MOSFET operation is only valid up to this point. After this point, the current is “frozen” at that maximum value; it does not follow the parabola described by the equation. So we can describe the current flowing into the drain of an nMOS transistor using two equations (plus one useful approximation):

( )

−−′= 2

21

DSDSTGSoxnD VVVVL

WCI µ TGSDS VVV −< (triode region)

( ) DSTGSoxnD VVVL

WCI −′≈ µ TGSDS VVV −<< (deep triode region)

( )2

21

TGSoxnD VVL

WCI −′= µ TGSDS VVV −≥ (saturation region)

For pMOS transistors, we just use the hole mobility instead of electron mobility, and insert a minus sign since the charge carriers are now holes (or you can just think of the current as flowing out of the drain instead of into it). Also, pFETs have negative threshold voltages (but VGS will also be negative in normal operation).

( )

−−′−= 2

21

DSDSTGSoxpD VVVVL

WCI µ TGSDS VVV −< (triode region)

( ) DSTGSoxpD VVVL

WCI −′−≈ µ TGSDS VVV −<< (deep triode region)

( )2

21

TGSoxpD VVL

WCI −′−= µ TGSDS VVV −≥ (saturation region)


Lecture 5 11

This behavior is shown graphically below. When a MOSFET has a low voltage across it (low VDS), it acts like a voltage-controlled resistor. The resistance is inversely proportional to Veff. When a MOSFET has a sufficiently high voltage across it (high VDS), it acts like a voltage-controlled current source. The current is proportional to the square of Veff.

VDS

ID “resistor” I-V curve

“current source” I-V curve

VGS = 3V

VGS = 2V

VGS = 1V

VDS =VGS - VT = Veff

Triode region

Active or Saturation region

The “current source” behavior of a MOSFET in the saturation region is apparent from the fluid model. The “waterfall” into the drain corresponds to a current source. Why does the current depend on the square of the effective gate voltage? Because when we increase the gate-to-source voltage, we affect the current in two ways: we increase the channel charge and we increase the electric field in the channel. (The slope of the water increases.)

Notice that much of our voltage supply can be used up just keeping MOSFETs in the active region!


Lecture 5 12

The Body Effect What happens if the source is not at the same potential as the substrate? The figure below shows the situation as we keep VDS constant but raise VS > 0.

p- silicon

SiO2

poly-Si

n+ n+

VG = VS + VT0 + 1V

VB = 0V

VS = 0V VD = 0.5V

p- silicon

SiO2

poly-Si

n+ n+

VG = VS + VT0 + 1V

VB = 0V

VS = 2V VD = 2.5V

Now that the source and drain are more strongly reverse-biased with respect to the substrate, the depletion region widens and the depletion charge QB increases. Now that there is more channel charge from the depletion region, there need not be as must inversion layer charge (QI) to balance the gate charge QG. Thus, the inversion layer weakens and the current drops.

This effect can be modeled as a slight increase in the threshold voltage VT. The depletion charge is given by:

sAB NqQ ψε2−=′


Lecture 5 13

The surface potential ψs can be expressed in terms of the resting surface potential φ0 and the source-to-bulk potential VSB:

SBFSBs VV +Φ=+= 20φψ

where

i

subF n

Nq

kT ln=Φ

where Nsub is the substrate doping level. Typical values of |2ΦF| range between 0.7V and 0.9V, and are denoted “PHI” in SPICE models.

The “correction factor” in the threshold voltage is given by:

( )FSBFTT VVV Φ−+Φ+= 220 γ

where

ox

sub

CNq′

=ε

γ2

Typical values of γ range from 0.4V1/2 to 0.8V1/2. Notice that both γ and |2ΦF| increase with doping levels. Smaller, more advanced VLSI processes tend to be more heavily doped, so the body effect is becoming more significant.

Example: For nMOS transistors in a particular VLSI fabrication process, γ = 0.45V1/2 and |2ΦF| = 0.9V. The basic threshold voltage VT0 = 0.70V. What is the threshold voltage for VSB = 0, 1, 2, 3, and 4V?

VT(VSB = 0V) = VT0 = 0.70V

VT(VSB = 1V) = 0.89V

VT(VSB = 2V) = 1.04V

VT(VSB = 3V) = 1.16V

VT(VSB = 4V) = 1.27V

Another way to think of the body effect is to imagine the substrate as a “back gate” that modulates the channel in the same way that the normal “front” gate does. The front gate acts thorough the oxide capacitance, and the substrate, or back gate, operates through the depletion capacitance. Since the substrate, or body, will always have a negative voltage with respect to the source, it acts in opposition to the front gate. Since the depletion capacitance is smaller than the oxide capacitance, the back gate has a weak effect on the channel.


Lecture 6 1

Small-Signal Parameters

The large-signal equations that describe MOSFET behavior are nonlinear. A circuit represents a system of nonlinear equations. Many times we are interested in building linear circuits, like filters that select certain frequencies but do not distort signals. How do we get linear behavior out of nonlinear devices?

If we zoom in on a nonlinear curve, it will eventually begin to look linear over a small range. This is similar to performing a Taylor expansion around a certain point on the curve, and then only keeping the first-order term. If we bias a transistor around an certain operating point and make only small perturbations about this point, we can approximate the device as a linear system. This is called small-signal analysis, because the amplitude of our signals must remain small for this analysis to remain valid.

The most important small-signal parameter of a MOSFET is its transconductance, gm. If we make a small change in gate voltage, the transconductance tells us how much that affects the drain current:

GS

Dm V

Ig∂∂

≡

VGS

ID

VT0

ID’

slope = gm(ID’) = ∂ID(ID’)

∂VGS


Lecture 6 2

We can express the transconductance of an above-threshold MOSFET in saturation in three equivalent ways:

In strong inversion:

effoxm VL

WCg ′= µ

Doxm IL

WCg ′= µ2

eff

Dm V

Ig 2=

Channel-Length Modulation

When we discussed pinch-off and the saturation region, we said that after pinch-off occurred, the drain current was constant. (Remember the waterfall in the fluid model?) Well, that’s not quite true due to an effect called channel-length modulation.

As we increase the drain voltage in the saturation region, the drain depletion region widens. This has the effect of widening the pinch-off region and thus shrinking the channel by a small amount.

p- silicon

SiO2

poly-Si

n+ n+

VG

VB

VS 1.VD increases…

2. Drain depletion region widens…

3. Pinch-off region widens…

4. Effective channel length decreases


Lecture 6 3

Since the current in a MOSFET is proportional to W/L, a shrinking channel length increases the current through the device. In “long-channel” devices (which usually means at least 3 times the minimum length allowed by the process), the slight increase in current as the drain voltage increases is nearly linear. If we plot ID vs. VDS for several values of VGS and extrapolate all the current traces backwards, they tend to converge at the same point on the VDS axis. This voltage is called the Early voltage (VA), and is the characteristic voltage in the first-order model of channel length modulation.

VDS

ID VGS = 3V

VGS = 2V

VGS = 1V

-VA

IDS0

slope = IDS0/VA = 1/ro

We can thus modify our expression for current in the saturation region by adding an extra term:

( )

+⋅−′=

A

DSTGSoxnD V

VVV

LWCI 1

21 2µ

We can define a small-signal parameter called output resistance to describe this effect:

D

A

D

DSo I

VI

Vr =

∂∂

≡

Since longer channels are affected less severely by drain depletion region widening, they show behavior closer to that of an ideal current source:

LrV oA ∝, for long-channel devices

Some people use the channel length modulation coefficient λ instead of VA:

( ) ( )DSTGSoxnD VVVL

WCI λµ +⋅−′= 121 2

where λ = 1/VA.


Lecture 6 4

In modern short-channel devices (lengths near the minimum length allowed by the process), the effect is more severe. Several additional effects contribute to drain current increasing faster than linearly. One of these effects is called drain-induced barrier lowering, or DIBL (“dibble”). In very short devices, the drain can act as an additional gate (“side gate?”), coupling to the channel through the drain depletion capacitance. This can lead to dramatic increases in drain current (and dramatic decreases in ro) as the drain voltage is increased.

VDS

ID VGS = 3V

VGS = 2V

VGS = 1V

short-channel effects

Most models of channel-length modulation are empirical models. They basically fit the observed behavior with first-order or higher-order models. The physical details – even in long-channel devices – are complex and difficult to model reliably.

In other words, the Early voltage is mostly a hack to fit the data.


Lecture 6 5

The MOS Transistor in Weak Inversion

In this section we will explore the behavior of the MOS transistor in the subthreshold regime where the channel is weakly inverted. This will allow us to model transistors operating with drain currents of less than 1µA, where the strong inversion model erroneously predicts zero current.

Remember, the strong inversion MOSFET model makes the assumption that the inversion charge QI goes to zero when the gate voltage drops below the threshold voltage. We saw that this is not quite true. Below threshold, the channel charge drops exponentially with decreasing gate voltage.


Moderate inversion

Strong inversion

VGB VT0

slope = Cox

|QI|


Lecture 6 6

This exponential relationship becomes clearer if we redraw the above figure with a logarithmic y axis:

Weak inversion

Moderate inversion

Strong inversion

VGB VT0

QI = -Cox(VGB – VT0)

log |QI|

QI ∝ -exp(VGB)

QI (actual)

We can think of weak inversion as the region where QI is an exponential function of gate voltage, strong inversion as the region where QI is a linear function of gate voltage, and moderate inversion as a transition region between the two.

In weak inversion, the inversion layer charge is much less than the depletion region charge:

BI QQ << in weak inversion

Since the substrate is weakly doped, QB is small, and there is not enough charge in the channel to generate a significant electric field to pull electrons from the source to the drain. Current flows by diffusion, not drift.

We shall once again consider our fluid model of a transistor. Let’s take another look at a transistor operating in the subthreshold regime:


Lecture 6 7

VGS

VS VD VG

elec

tron

ener

gy

volta

ge

reference voltage

Clearly, this model is insufficient to account for weak inversion since the channel charge is zero. We have to add another degree of realism to our model to account for subthreshold current flow: water vapor.

Electrons, like water molecules, can be excited by thermal energy into higher energy levels. Although most water molecules have a potential energy at or below the level of the liquid in the source and drain tanks, some water molecules have gained enough energy (thermally) to rise above this level – as vapor. Similarly, a small fraction of electrons in the source and drain acquire significantly more energy than the majority of charge carriers in the conduction band.

The density of water vapor above a liquid follows a decaying exponential with height (i.e., potential energy). Similarly, air pressure drops exponentially with altitude. Electrons in a solid obey Fermi-Dirac statistics which leads to this exponential distribution according to energy. This is similar to the Maxwell-Boltzmann statistics obeyed by atoms in a gas. Let’s add water vapor to our fluid model:


Lecture 6 8

VGS

VS VD VG el

ectro

n en

ergy

vo

ltage

reference voltage

Q’

energy

Now it’s clear that the inversion charge in the channel, while small, is an exponential function of the barrier height. The barrier height represents the surface potential ψs. As we mentioned before, in weak inversion the surface potential is flat – it does not change over the length of the channel. The surface potential can be modeled fairly accurately by considering the capacitive divider between the oxide capacitance Cox and the depletion capacitance Cdep:

p- silicon

SiO2

poly-Si

n+ n+

VD

VG

VS

VB

ψs

VB

VG

ψs

Cox

Cdep

Using the equation for a capacitive divider and assuming that VB = 0, we find that:

Gs Vκψ =

where kappa – the gate coupling coefficient – represents the coupling of the gate to the surface potential:

depox

ox

CCC+

=κ


Lecture 6 9

The depletion capacitance stays fairly constant over the subthreshold region, and kappa is usually considered to be constant, although it increases slightly with gate voltage. In modern CMOS processes, kappa ranges between 0.6 and 0.8. It can have slightly different values for pMOS and nMOS devices. A good, all-around approximation for kappa (unless another value is given) is:

7.0≅κ

! Some texts use n or ζ (zeta) instead of κ, where n = ζ = (1/κ) ≅ 1.4.

Now let’s return to the fluid model for VDS > 0:

VS VD

VG

elec

tron

ener

gy

volta

ge

reference voltage

κVG diffusion

The important parameter is the concentration of carriers at channel level (and above). Since the source tank is higher than the drain tank, the carrier concentration is higher where the source meets the channel than where the drain meets the channel. Electrons diffuse from the source to the drain.

The charge concentration (at channel level) in the source (x = 0) and the drain (x = L) is given by:

−∝′

T

GSI U

VVQ

κexp0

−∝′

T

GDIL U

VVQ

κexp

Where UT is the thermal voltage:

mV26≅≡q

kTUT at room temperature

(We use “U” instead of “V” for voltage to avoid confusion with the threshold voltage VT.)


Lecture 6 10

From our previous discussion of diffusion, we know that particle motion is proportional to the concentration gradient. The concentration of electrons decreases linearly from the source to the drain (i.e., concentration gradient is constant), so we can write an expression for the drain current:

( ) ( )ILITnILI

nD QQUL

WL

QQWDI ′−′−=′−′

−= 00 µ

This leads us (details omitted) to the expression for drain current in a subthreshold MOSFET:

−=

−−T

D

T

S

T

G

UV

UV

UV

D eeeL

WIIκ

0

or, writing it larger:

−−

−⋅

=

T

D

T

S

T

GD U

VUV

UV

LWII expexpexp0

κ

where I0 is a process-dependant constant. For nFETs,

−⋅

′≡

T

nTToxnn U

VUCI 0

2

0 exp2 κ

κµ

Typical values of I0n range from 10-15A to 10-12A.

We can rearrange terms and rewrite the expression for drain current as:

−−⋅

−=

T

DS

T

SGD U

VU

VVL

WII exp1exp0κ

Notice that when exp(-VDS/UT) << 1, the last term is approximately equal to one, and can be ignored. This occurs (to within 2%) for VDS > 4UT, since e-4 ≅ 0.018. The expression for drain current then simplifies to:

−=

T

SGD U

VVL

WII κexp0 for VDS > 4UT (saturation)

At room temperature, 4UT ≅ 100mV, an easy value to remember. It is quite easy to keep a subthreshold MOSFET in saturation, and the VDS required to do so does not depend on VGS as is the case above threshold. This is very advantageous for low-voltage designs.


Lecture 6 11

VDS

ID

VGS = 0.42V

VGS = 0.41V

VGS = 0.40V

VDS = 4UT ≅ 100mV

Triode region

Saturation region

This saturation behavior is easy to understand if we look at our fluid model. If the drain tank is significantly lower than the source tank, the concentration of carriers in the drain at channel level will be much, much small than the concentration of carriers in the source at channel level, so the exact level doesn’t matter.

Another difference between subthreshold and above threshold operation is the way ID changes as we increase VGS. In a weakly-inverted FET, the current increases exponentially. In a strongly-inverted FET, the current increases quadratically (square law). This can be understood by looking at a plot of ID vs. VGS in two ways: with a linear ID axis and with a logarithmic ID axis:


Lecture 6 12

VGS

log ID

(UT/κ) ≈ 40mV

factor of e slope = e-fold/(UT/κ)

VT0

VGS

ID

VT0

ID grows as (VGS – VT0)2

ID grows as exp(κVG/UT)

For a pFET, we have to consider the gate, drain, and source potentials with respect with the well potential VW. Unlike the substrate, the well will not be at ground, so we need to write it in explicitly:

( ) ( ) ( )

−−−

−−⋅

−=

T

DW

T

SW

T

GWpD U

VVU

VVU

VVL

WII expexpexp0κ

−⋅

′≡

T

pTToxpp U

VUCI 0

2

0 exp2 κ

κµ

Typical values of I0p range from 10-19A to 10-14A.


Lecture 6 13

In saturation:

( ) ( )

−−−=

T

SWGWD U

VVVVL

WII κexp0 for |VDS| > 4UT

This can be rewritten as:

( )[ ]

−+−=

T

WSGSD U

VVL

WIIκκ 1

exp0

Where (1 - κ) is the back-gate coefficient. Notice that the body effect is explicit in the weak-inversion model without having to add a “fudge factor” like the variable threshold voltage in the strong inversion model.

The transconductance of a subthreshold MOSFET is easily derived:

In weak inversion:

T

Dm U

Ig κ=

Subthreshold MOSFETs behave similarly to bipolar junction transistors (BJTs). The collector current of an npn bipolar transistor exhibits an exponential dependence on base-to-emitter voltage:

=

T

BESC U

VII exp

A bipolar transistor has a transconductance of gm = IC /UT, which is equivalent to the expression for a subthreshold MOSFET if we set κ = 1.

Of course, a MOSFET doesn’t pull any current through its gate like a bipolar transistor pulls through its base. This can make circuit design much easier.


Lecture 6 14

Moderate Inversion

A transistor does switch immediately from an exponential, weak-inversion behavior to a quadratic, strong-inversion behavior. There is a smooth transition between the two extremes where drift and diffusion generate the current with neither effect dominating. Modeling this area is extremely difficult, but the behavior is easily understood as a hybrid between weak- and strong-inversion behavior.

VS VD

VG

elec

tron

ener

gy

volta

ge

reference voltage

The boundaries between weak, moderate, and strong inversion can be approximated in terms of voltages or currents. Of course, the boundaries between the areas are fuzzy, with no clean breaks. Here are two approximations sometimes used:

VGS > VT + 100mV strong inversion

VT + 100mV > VGS > VT – 100mV moderate inversion

VGS < VT – 100mV weak inversion

(This assumes that the threshold voltage VT has been adjusted for the body effect, if necessary.)


Lecture 6 15

It is more common to design circuits with bias currents in mind. Following is a good estimate of the inversion boundaries in terms of drain current:

ID > 10IS strong inversion 10IS > ID > 0.1IS moderate inversion

ID < 0.1IS weak inversion

where IS is called the moderate inversion characteristic current:

LWUC

I ToxS κ

µ 22 ′=

Typical values of IS range from 100nA to 500nA for nFETs with W/L = 1, and 40nA to 120nA for pFETs with W/L = 1. Of course, for large W/L ratios, the weak inversion region can extend well into the microamp range.

Example: In AMI’s 0.5µm CMOS process, µnCox’ = 116µA/V2 and µpCox’ = 38µA/V2. Estimate the boundaries between weak, moderate, and strong inversion (in terms of drain currents) for nMOS and pMOS transistors with W/L = 1 and W/L = 100. Assume κ = 0.7. nFETs:

=′

=L

WUCI ToxnSn κ

µ 22220nA for W/L = 1

• So for W/L = 1, the boundary between weak and moderate inversion is around 22nA, and the boundary between moderate and strong inversion is around 2.2µA.

• For W/L = 100, the boundary between weak and moderate inversion is around 2.2µA, and the boundary between moderate and strong inversion is around 220µA.

pFETs:

=′

=L

WUCI Toxp

Sp κµ 22

73nA for W/L = 1

• So for W/L = 1, the boundary between weak and moderate inversion is around 7.3nA, and the boundary between moderate and strong inversion is around 0.73µA.

• For W/L = 100, the boundary between weak and moderate inversion is around 0.73µA, and the boundary between moderate and strong inversion is around 73µA.


Lecture 6 16

A More Accurate Model of Kappa

The subthreshold gate coupling coefficient κ is rarely reported in process data. Sometimes, people will report the “subthreshold slope” UT /κ. If it is not given, κ can be calculated by:

( )

1

121

−

Φ++=

Fαγκ

where

ox

sub

CNq′

=ε

γ2

i

subF n

Nq

kT ln=Φ

ox

oxox t

Cε

=′

The α parameter should be set between zero – for extreme weak inversion (near depletion mode) – and one – for the boundary between weak and moderate inversion – to account for the slight change in depletion capacitance. Usually, α = 0.5 is a good value to use for general-purpose use.

So all we really need to know is the oxide thickness (to determine Cox’) and the channel doping (Nsub) to estimate kappa. In SPICE models, oxide thickness is called TOX (units = m) and the channel doping is called NSUB or NCH (units = cm-3).

Example: An nFET has a substrate doping level of 1.7 x 1017cm-3 and an oxide thickness of 139Å. Compute κ, using α = 0.5.

tox = 1.39 × 10-6cm

Cox’ = 0.248µF/cm2

γ = 0.960V1/2

ΦF = 0.422V

κ = 0.62


Lecture 7 1

Transistor Summary

The specific current IS is used to mark the boundary between weak and strong inversion operation:

LWUCI Tox

S ⋅′

=κ

µ 22

The inversion coefficient IC of a transistor is the ratio of the transistor’s drain current to specific current:

S

D

IIIC =

Strong Inversion (IC > 10)

Parameter Expression Drain current – triode region ( )

−−′= 2

21

DSDSTGSoxnD VVVVL

WCI µ

where ( )FSBFTT VVV Φ−+Φ+= 220 γ

Drain current – deep triode region (linear region) ( ) DSTGSoxnD VVV

LWCI −′≈ µ

Drain current – saturation region ( )2

21

TGSoxnD VVL

WCI −′= µ

Condition for saturation

TGSDS VVV −≥

Drain current – saturation region (with channel-length modulation)

( )

+⋅−′=

A

DSTGSoxnD V

VVVL

WCI 121 2µ

Transconductance Doxm I

LWCg ′= µ2

( )TGSox VVL

WC −′= µ

TGS

D

VVI−

=2

Output resistance

D

Ao I

Vr =


Lecture 7 2

Weak Inversion (IC < 0.1) Parameter Expression

Drain current – general

−=

−−T

D

T

S

T

G

UV

UV

UV

D eeeL

WIIκ

0

Drain current – saturation region T

sG

UVV

D eL

WII−

=κ

0

Condition for saturation

TDS UV 4≥

Drain current – saturation region (with channel-length modulation)

+⋅=

−

A

DSUVV

D VV

eL

WII T

sG

10

κ

Transconductance

T

Dm U

Ig κ=

Output resistance

D

Ao I

Vr =

For a pMOS device with well voltage VW, replace VG, VS, and VD with VW–VG, VW–VS, and VW–VD respectively.

The following circuit symbols are commonly used to represent nMOS and pMOS transistors in circuit diagrams. In this class we will use the first symbols, but the book uses the later symbols (with the arrows). The arrows make a rather artificial distinction between the source and drain in a completely symmetric device.

S S S S

S S S S

G G G G

G G G G

D D D D

D D D D

B B

W W

nFET symbols

pFET symbols

(G = gate; S = source, D = drain; B = bulk; W = well)


Lecture 7 3

Small-Signal Models

The equations describing drain current as a function of terminal voltages are useful for large-signal analysis. Sometimes it’s useful to linearize a circuit around a dc operating point and perform small-signal analysis, assuming all ac signals don’t affect the bias currents significantly. The two small-signal parameters most commonly used in MOSFET design are gm (the transconductance) and ro (the output resistance).

There are two particularly useful small-signal equivalent circuits of a MOSFET:

S

G

D

S

G D

ro gmvGS vGS

T equivalent:

S

G

D

S

G

D

is

1/gm is

ig = 0 ro

Often when using the T model, ro is assumed to be infinite to facilitate analysis.

Now let’s take a look at some simple circuit building blocks, and analyze them in weak and strong inversion operation…


Lecture 7 4

Diode-Connected Transistor

V

I

I

Vdd Vdd

V

elec

tron

ener

gy

volta

ge

reference voltage

VGS

VS

VD VG

Veff

this level fixed at ground

Iin


Lecture 7 5

Current Mirrors

V

Iin

Iin

Vdd

V Iout

Vdd

Iout

reference voltage

VGS

VS

VD VG

Veff

this level fixed at ground

Iin

Iout


Lecture 7 6

Source Followers (Common Drain Configuration)

Vout

I

I

Vdd Vdd

Vin

Vout

Vin

elec

tron

ener

gy

volta

ge

reference voltage

VGS

Vout

Vin

Veff

Ibias

Ibias


Lecture 7 7

More Source Followers

I

Vdd

Vout

V1

I

Vdd

Vout

Vin V2


Lecture 7 8

Series and Parallel Combinations

VS

I

VG

VD

VS

VG

VD

I

W/L

W/L

W/L W/L


Lecture 7 9

Basic Gain Stage (Common Source Configuration)

Vout

I

I

Vdd Vdd

Vin

Vout

Vin


Lecture 7 10

Alternate Expression for Channel-Length Modulation in Weak Inversion

The traditional way to account for channel-length modulation (to first order) is to add a (1 + VDS/VA) term to the drain current equation:

+⋅=

−

A

DSUVV

D VV

eL

WII T

sG

10

κ

We’ve seen in the above examples how nice an exponential drain current expression can be for circuit analysis. This linear expression tacked on to the end brings our analysis to a halt. But consider the following Taylor series expansion of ex:

K+++++= 432

241

61

211 xxxxex

Now let’s substitute x = VDS/VA:

K+

+

+

++=

432

241

61

211

A

DS

A

DS

A

DS

A

DSVV

VV

VV

VV

VV

e A

DS

For VDS << VA (as is usually the case since VA can range from 10-40V for typical gate lengths), the higher order terms become insignificant, and we can approximate the exponential with a linear expression:

A

DSVV

VVe A

DS

+≈ 1

Here we have the original factor that we multiplied our drain current by to model channel-length modulation. But what if we just use the exponential representation instead? It grows faster than linearly, but so does drain current due to second-order effects such as DIBL. The Early voltage is a hack anyway, so why not make it a hack that makes our math easier? Let’s write the expression for saturation drain current as:

A

DS

T

sG

VV

UVV

D eeL

WII−

=κ

0

Now everything is exponential. Let’s try analyzing the basic gain stage using this equation.


Lecture 8 1

Transistor Gain

Weve seen that the following configurations give us an inherent voltage gain of AV = -gmro.

Vout

I

I

Vdd Vdd

Vin

Vout

Vin

Thus, if we want to increase the voltage gain, we have to increase the transconductance or the output resistance. The output resistance can be increased by making the transistor longer. The transconductance can be increased by raising the drain current, but this decreases the output resistance, so this doesnt help us. If our transistor is operating in strong inversion, we can raise the transconductance by increasing W/L. We should increase the width, since decreasing the length reduces the output resistance. If our transistor is operating in weak inversion, the transconductance is independent of W/L, so there is no way to increase it without lowering the output resistance.

Example: Suppose we have an nMOS transistor with Early voltage VA = 20V and W/L = 10. Calculate the transistors inherent voltage gain at bias currents of I = 1nA, I = 10nA (both weak inversion), I = 10µA, and I = 100µA (both strong inversion). In this technology, µnCox = 120µA/V2 and κ = 0.7.

I = 1nA: gm = κI/UT = (0.7)(1 nA) / (26 mV) = 27 nA/V ro = VA/I = (20 V) / (1 nA) = 20 GΩ A = -gmro = -540 ⇒ 55 dB

I = 10nA: gm = κI/UT = (0.7)(10 nA) / (26 mV) = 270 nA/V ro = VA/I = (20 V) / (10 nA) = 2 GΩ A = -gmro = -540 ⇒ 55 dB

I = 10µA: gm = [2µnCox(W/L)I]1/2 = [2(120 µA/V2)(10)(10µA)]1/2 = 155 µA/V ro = VA/I = (20 V) / (10 µA) = 2 MΩ A = -gmro = -310 ⇒ 50 dB


Lecture 8 2

I = 100µA: gm = [2µnCox(W/L)I]1/2 = [2(120 µA/V2)(10)(100µA)]1/2 = 490 µA/V ro = VA/I = (20 V) / (100 µA) = 200 kΩ A = -gmro = -98 ⇒ 40 dB

Notice several trends:

• In weak inversion, gain is independent of bias current and W/L ratio.

• Gain is at a maximum in weak inversion (typically 50dB-60dB), and decreases in strong inversion.

• In strong inversion, gain decreases as the square root of bias current and increases as the square root of the W/L ratio.

If we need additional gain beyond what can be obtained through a single device, we have two options: cascade or cascode.

A cascade configuration is simply two gain stages in series:

I

Vdd

Vout

Vin

I

It is easy to see that the gain of N elementary gain stages in series is simply the product of each individual gain:

( )∏=

−=N

ioimicascade rgA

1

For the case of two identical cascaded gain stages, A = (gmro)2.


Lecture 8 3

The cascode configuration is shown below. The idea behind the cascode scheme is to add a source follower at the drain of the original transistor. If we set the source followers input to a dc voltage (VCAS), this device will attempt to hold the first transistors drain voltage constant while Vout swings up and down. This has the effect of multiplying the effective output resistance ro by the gain of the circuit (approximately).

I

Vdd

Vout

Vin

VCAS

So we see that the gain of a cascode stage is given by:

( )21omcascode rgA

κ−≅


Lecture 8 4

Another Look at the Body Effect Our expressions for transistor operation and weak inversion and strong inversion deal with the body effect in different ways:

• In our weak inversion equations, we use the capacitive-divider ratio kappa to express the partial control the gate has over the channel.

• In our strong inversion equations, we increase the threshold voltage as the source-to-body potential increases.

We will now show that these two expressions are equivalent.

Here, again, is the equation for saturation current in strong inversion:

( )2

21

TGSoxnD VVL

WCI −′= µ

where ( )FSBFTT VVV Φ−+Φ+= 220 γ

Combining these equations (and assuming the bulk voltage is zero), we get:

( )[ ]20 2221

FSFSTGoxnD VVVVL

WCI Φ−+Φ−−−′= γµ

( )[ ]202

1STGoxnD VfVV

LWCI −−′= µ

We have grouped all the VS terms into a single function f(VS):

( ) ( )FSFSS VVVf Φ−+Φ+= 22γ

Lets take the derivative of this function:

SFS VdVdf

+Φ+=

221 γ

The value of the derivative at the point VS = 0 is:

κγ 122

10

=Φ

+== FVS

SdVdf

If we simplify our original expression by making a first-order approximation, we can write the saturation current in strong inversion as:

2

021

−−′≅

κµ S

TGoxnDV

VVL

WCI

Now lets pull the κ outside the squared quantity:


Lecture 8 5

( )[ ]2022

1STG

oxnD VVV

LWCI −−

′≅ κ

κµ

Now lets reconsider the expression for weak inversion current:

T

sG

UVV

D eL

WII−

=κ

0

Remember that the I0 factor contains an exp(-κVT0/UT) term, so we can rewrite this as:

( )T

sTG

UVVV

SD eL

WII−−

=0κ

Where IS is the familiar specific current that defines the boundary between weak and strong inversion current levels. Expanding this out, we get:

( )T

sTG

UVVV

Toxn

D eL

WUC

I−−′

=0

22κ

κµ

So we have written both strong and weak inversion current in the following form:

( )[ ]STOGD VVVfI −−= κ

which demonstrates that the body effect results from the same physical effects in both weak and strong inversion, despite the different mathematical conventions used to express it.

We can now define a third important small-signal parameter for a transistor that accounts for the body effect: the body-effect parameter or body transconductance gmb:

BS

Dmb V

Ig∂∂

≡

(Note: This parameter is called gs in Johns & Martin.)

Usually we express gmb as a fraction of the gate transconductance gm:

mmb gg η=

where eta is given by:

κκγη −≅

+Φ= 1

22 SBF V for small VSB


Lecture 8 6

In weak inversion we can write this as:

( )T

Dmmb U

Igg κη −==

1

A good rule of thumb is that gmb will usually be about one-fifth of gm. This is due to the fact that kappa increases with VSB.

mmmb ggg 2.0≅= η

Now we can build a better small-signal model that includes the body effect:

S

G D

ro gmvGS vGS gmbvBS

vBS

B


Lecture 8 7

Node Impedances

Now that we have defined all three small-signal parameters for a MOSFET, we can consider the impedances looking into the transistor in different ways:

1/(gm + gmb)

1/(gm + gmb)

1/gm

1/gm

ro

ro ∞

∞

Low Impedance High Impedance

diode source drain gate

Example: For a MOSFET in weak inversion, compute the resistances looking into a diode-connection, the source, and the drain if the transistor is biased at 50nA. Assume κ = 0.7 and VA = 10V.

diode: 1/gm = UT/κID = 0.74 MΩ

source: 1/(gm + gmb) = UT/ID = 0.52 MΩ

drain: ro = VA/ID = 200 MΩ

So the impedance looking into the drain is about two orders of magnitude higher than the impedance looking into the source or into a diode-connected transistors.

If the bias currents in a circuit are on the same order of magnitude, we can usually determine relative node impedances by inspection. High impedance nodes are usually associated with high gain, and usually determine the high-frequency limit of the circuit [fnode = 1/(2πRnodeCnode)].


Lecture 8 8

The Differential Pair

The differential pair is a very useful subcircuit.

I1

V1

IB

I2

V2

V

The idea is that the bias current IB is divided between two branches, and the difference between V1 and V2 determines the division. The common-source voltage V floats to whatever level is necessary to insure that I1 + I2 = IB.

Lets analyze this circuit in weak inversion.


Lecture 8 9

TT

T

UV

UV

UV

B

ee

eII21

1

1 κκ

κ

+

=

TT

T

UV

UV

UV

B

ee

eII21

2

2 κκ

κ

+

=

I1 I2

V1 - V2

IB

IB 2

0 0 +100 mV -100 mV

I1 + I2 = IB

What if we measure the output differentially (I1 I2)?


Lecture 8 10

Transconductance Amplifier (Voltage In; Current Out)

Here we use a pFET current mirror to subtract I2 from I1.

I1

V1

IB

I2

V2

V

Vdd

Iout = I1 - I2

I1

Vout

( )T

Bout UVVIIII

2tanh 21

21−

=−=κ

The tanh function is a well-behaved function in that it has asymptotes at +1 and 1, and has a slope of 1 at the origin.


Lecture 8 11

If we define Vin = V1 V2,

T

inBout U

VII2κ≅ for small inV

The overall small-signal transconductance of the circuit is given by:

212 mmT

B

in

outm gg

UI

VIG ===

∂∂≡ κ

I1 I2

V1 - V2

IB

IB 2

0 0 +100 mV -100 mV

I1 - I2

-IB


Lecture 9 1

Exploring the Gain-Bandwidth Tradeoff

Consider the following differential amplifier with a resistive load:

I1

V1

2ID

I2

V2

RL RL

VDD

Vout

Vin = V1 – V2 Av = gmRL

The gain of this amplifier is given by gmRL. What is the bandwidth of this amplifier? To answer that question, we must consider the capacitance at the high-impedance output of the circuit:

I1

V1

2ID

I2

V2

RL RL

VDD

Vout

Vin = V1 – V2

Av = gmRL

CL CL

fH = 1/(2πRLCL)


Lecture 9 2

The time constant associated with the output node is τ = RLCL. This sets the amplifier bandwidth fH to:

LLH CR

fπ2

1=

By noting that RL = Av/gm, we can write the gain-bandwidth tradeoff explicitly:

Lv

mH CA

gf

π2=

L

mHv C

gfA

π2=

L

mHv C

gA =ω

For a given transconductance and output capacitance, the gain-bandwidth product is constant in this circuit.

A more accurate expression for gain and bandwidth is obtained when we include the output resistance of the transistors:

( )oLmv rRgA ||=

( ) LoLH CrR

f||21

π=

If RL << ro, we can neglect this effect.

Now let’s consider a source follower:

Vout

ID

Vdd

Vin

CL

1/gmb

The bandwidth of this circuit is set by the output node time constant CL/gmb:


Lecture 9 3

L

m

Lmb

H Cg

Cg

fπ

η

π212

1 =

=

The gain of this circuit is:

83.01

1 ≅+

=ηvA assuming 2.0=η

So we find that the gain-bandwidth product is:

L

m

L

mHv C

gCg

A 17.01

≅+

=η

ηω

So a source follower has a constant gain-bandwidth product that is proportional to gm and inversely proportional to the capacitive load. Since the gain of a source follower is fixed at just under unity, its bandwidth is higher than a high-gain stage for equal values of gm.


Lecture 9 4

Relative Transconductance: gm/ID

Recall the basic expressions for transconductance in weak and strong inversion:

T

Dm U

Ig κ=

inversionweak

( ) Doxm ILWCg ′= µ2inversion strong

If we plot transconductance (gm) vs. drain current (ID) on a log-log graph, we get the following:

log ID IS

log gm

strong inversion weak inversion

gm ∝ √ID

gm ∝ ID

slope = 1

slope = 1/2

It is obvious that transconductance increases with drain current, but that in the weak inversion region, it increases faster. If we divide transconductance by the drain current, we get relative transconductance. As we shall see, relative transconductance is a very important parameter in low-current circuit design.

TD

TD

D

m

UIUI

Ig κκ

==

inversionweak

( ) ( )D

ox

D

Dox

D

m

ILWC

IILWC

Ig ′

=′

=

µµ 22

inversion strong


Lecture 9 5

We can plot relative transconductance as a function of drain current:

log ID IS

gm/ID

κ/UT

0


gm/ID ∝ 1/√ID

gm/ID constant

Another way of looking at relative transconductance is as a function of the inversion coefficient ID/IS:

log ID/IS 1

gm/ID

κ/UT

0


gm/ID ∝ 1/√ID

gm/ID constant

0.1 10 100 0.01 inversion coefficient


Lecture 9 6

Estimating MOSFET Capacitances

When we’re using hand calculations to design circuits, we will often need to estimate parasitic capacitances associated with the drain and gate of a MOSFET. These capacitances depend on doping levels (which vary with process) and operating voltage, but we can leave these details to the simulator and instead make quick estimates that are correct to within a factor of two.

As CMOS processes are scaled down to smaller and smaller feature sizes, many parameter ratios stay the same. For example, the gate oxide thickness is always about 2% of the minimum channel length.

min02.0 Ltox ≅

This is true for a 2.0µm process (circa 1980) and a 0.18µm process (circa 2000). This leads to a constant gate capacitance per unit width of about 2fF/µm for a minimum-length transistor:

mfF/ 2min µ≅′ LCox

Similarly, the drain-to-bulk capacitance per unit width (including bottom-plate and side-wall capacitance) has stayed roughly constant at about 2fF/µm. The doping levels are increasing in smaller processes, but the junction size is deceasing.

mfF/ 2 µ≅DBC

Example: Suppose we build an 36µm x 1.8µm transistor in a 0.5µm process where the minimum channel length is 0.6µm. Estimate the gate and drain capacitances:

( ) fF 72m36mfF/ 2 =⋅≅ µµDBC

Our transistor has a length three times the minimum length:

( ) fF 216m363mfF/ 2min

min =⋅⋅≅⋅

⋅′≅ µµW

LLLCC oxG

The gate capacitance is the dominated by the gate-source capacitance CGS in strong inversion and the gate-body capacitance CGB in weak inversion, and these two capacitances are close but not identical. As long as the source and body are tied to fixed potentials, you don’t need to worry about the difference for hand calculations.


Lecture 9 7

Low-Gain, High-Bandwidth Amplifier

Here we are using diode-connected pFETs as a load having resistance 1/gmL, where gmL is the transconductance of these devices.

I1

V1

2ID

I2

V2

VDD

Vout

gm

gmL

1/gmL 1/gmL

(W/L)L

(W/L)I

The gain of this circuit is given as:

mL

mLmv g

gRgA ==

Another way of looking at this is as a ratio of the relative transconductances of the input and load devices:

( )( )DmL

Dm

mL

mv Ig

Iggg

A ==

In the case where all transistors are operating in strong inversion, the gain is given by:

( )( )

( )( )L

I

p

n

DLoxp

DIoxn

mL

mv LW

LWILWCILWC

gg

Aµµ

µµ

=′

′==

2

2

where (W/L)I is the width-to-length ratio of the input (differential pair) transistors and (W/L)L is the width-to-length ratio of the diode-connected load transistors.


Lecture 9 8

The ratio of mobilities is always around 3, so the gain is boosted by a factor of about 1.7 by using nFETs in our differential pair and pFETs in our load. It is clear that if we want high gain, we should make the input transistors very wide and the load transistors very narrow. For the case where (W/L)I = 100, (W/L)L = 1/10, and µn = 3µp, the gain Av = 55 (35 dB). If we built the same amplifier using pFETs in the differential pair and nFETs in the load, we would get a gain Av = 18 (25 dB). Of course, as we decrease the width-to-length ratio of the load transistors, we lower the dc output level, which can desaturate the differential pair if we’re not careful.

In the case where all transistors are operating in weak inversion, the gain is given by:

1===

T

D

T

D

mL

mv

UI

UI

ggA

κ

κ

Obviously, this is not a good circuit configuration to use in weak inversion. No matter how we size the devices, we cannot get any gain. However, it is possible to operate the input transistors in weak inversion (by making them very wide) and the load transistors in strong inversion (by making them very narrow) for the same bias current ID. In this case, the gain is given by:

( ) ( )Loxp

D

TDLoxp

TD

mL

mv LWC

IUILWC

UIgg

A′

=′

==µ

κµ

κ22

Let’s reconsider our hypothetical amplifier from above where (W/L)I = 100 and (W/L)L = 1/10. We can compute the specific current IS for both devices, assuming µnCox’ = 120µA/V2 and µpCox’ = 40µA/V2:

( )( ) A231007.0

mV 26A/V12022 222

, µµκ

µ=⋅=

⋅

′=

I

ToxnIS L

WUCI

( )( ) nA 7.7101

7.0mV 26A/V4022 222

, =⋅=

⋅

′= µ

κµ

L

ToxpLS L

WUCI

So if we operate the circuit with ID = 2.3 µA, the input transistors have an inversion coefficient ID/IS = 1/10 (weak inversion) and the load transistors have an inversion coefficient ID/IS = 300 (strong inversion). In this case, the gain is found to be:


Lecture 9 9

( ) ( )( ) ( )dB 23 14101A/V402

A2.3mV 267.0

2 2 ==′

=µ

µµ

κ

Loxp

D

Tv LWC

IU

A

This is significantly lower than the case above where both devices were in strong inversion (Av = 55). This demonstrates that the weak inversion region is closer to “traditional” circuit operation than we may think: A differential pair built from transistors with W/L = 100 and biased with a current source 2ID = 4.6µA operates in weak inversion, and gives us a different gain than we might expect from the familiar strong inversion equations.

In low-power circuit design, it is essential to compute the inversion coefficient for each transistor so you can use the appropriate expression for transconductance.

Now let’s estimate the bandwidth of this amplifier. The load capacitance consists of parasitic drain-to-bulk capacitances from the load and input transistors, and the gate capacitance of the load transistor.

Let’s assume that we build this device in a technology where the minimum gate length is 0.6µm, and our transistors are sized as follows: (W/L)I = 180µm/1.8µm and (W/L)L = 1.8µm/18µm.

( ) fF 3.6m8.1mfF/ 2, =⋅≅ µµLDBC

( ) ( ) fF 108m8.130mfF/ 2mfF/ 2min

, =⋅⋅≅⋅

⋅≅ µµµ W

LLC LG

( ) fF 360m180mfF/ 2, =⋅≅ µµIDBC

So the total output capacitance is CL ≅ 470fF. The bandwidth fH is given by:

LLH CR

fπ2

1=

The equivalent load resistance is given by 1/gmL. Assuming the load operates in strong inversion, the bandwidth can be expressed as:

( )L

DLoxpH C

ILWCf

πµ

2

2 ′=

From our previous example where ID = 2.3µA, fH = 1.4MHz.


Lecture 9 10

From the above analysis, it is clear that if we can decrease the gm of the load transistors (i.e., increase the load resistance) while keeping the gm of the differential pair unchanged, we will increase the gain of the amplifier. Transconductance decreases as we decrease the current through the transistor, so one technique to boost gain is to steal some of the bias current before it reaches the load transistors:

I1

V1

2ID

I2

V2

VDD

Vout

gm

gmL αID αID (W/L)L

(W/L)I

In this circuit, α is always less than one, and might be something like 0.8. In the case where all devices operate in strong inversion:

( )( ) ( )

( )( )L

I

p

n

DLoxp

DIoxn

mL

mv LW

LWILWC

ILWCgg

Aµµ

ααµµ

−=

−′

′==

11

12

2

So for α = 0.8, we’ve boosted our gain by a factor of 2.2 (an extra 7 dB).

We can use this technique to get a gain greater than 1 out of this amplifier when all devices are operating in weak inversion:

( ) αακ

κ

−=

−==

11

1

T

D

T

D

mL

mv

UI

UI

ggA

So for α = 0.8, we get a gain of 5 (14 dB).


Lecture 9 11

Why not make α = 0.999 and get a gain of 1000? Because we can’t count on our transistors to match perfectly, and if α > 1, the circuit stops working.


Lecture 9 12

High-Gain, Low-Bandwidth Amplifier

We can increase the gain of our differential amplifier substantially by using the channel-length modulation effect to produce a high-resistance load ro.

I1

V1

2ID

I2

V2

VDD

Vout

gm

ro ro

bias

(W/L)I

In this circuit, the top transistors act as current sources biased by some mechanism that keeps the output voltage at a reasonable level. The gain of this circuit is given by:

omLmv rgRgA ==

Now the node impedance at the output is so high that we can no longer neglect the output impedance of the differential pair transistors, so the actual gain is given by:

( ) omoomv rgrrgA21|| ==

(Assuming that all the devices have equal output resistances.) We can rewrite this expression in terms of the relative transconductance of the input transistors:

221 A

D

momv

VIg

rgA ⋅

==


Lecture 9 13

Now it is obvious that the gain will be highest in weak inversion, where gm/ID reaches its maximum value.

In strong inversion, the gain is:

( ) ( )A

D

Ioxn

D

ADIoxnomv V

ILWC

IVILWCrgA ⋅

′=⋅′⋅==

22

21

21 µ

µ

In weak inversion, the gain is:

T

A

D

A

T

Domv U

VIV

UIrgA

221

21 κκ

=⋅⋅==

For VA = 20V, Av = 270 (49 dB).

To facilitate a comparison of the two expressions, we can rewrite the strong inversion gain as a function of the inversion coefficient ID/IS by noting that:

( ) 22 T

Soxn U

ILWC

κµ =′

Using this, we get:

( ) T

A

SDv U

VII

A2

12 κκ

⋅=

At the beginning of strong inversion (ID/IS ≅ 10), we find that the gain is about half the value obtained in weak inversion:

( ) T

A

T

Av U

VUVA

253.0

2101

7.02 κκ ≅⋅=

As we go further into strong inversion, the gain drops as the square root of current.

Now let’s estimate the bandwidth of this amplifier. The load capacitance consists of parasitic drain-to-bulk capacitances from the load and input transistors.

Let’s assume that we build this device in a technology where the minimum gate length is 0.6µm, and our transistors are sized as follows: (W/L)I = 180µm/1.8µm and (W/L)L = 1.8µm/18µm.

( ) fF 3.6m8.1mfF/ 2, =⋅≅ µµLDBC

( ) fF 360m180mfF/ 2, =⋅≅ µµIDBC


Lecture 9 14

So the total output capacitance is CL ≅ 360fF. The bandwidth fH is given by:

LLH CR

fπ2

1=

The equivalent load resistance is given by ro/2. The bandwidth can be expressed as:

LA

DH CV

Ifπ

=

From our previous example where ID = 2.3µA, and assuming VA = 20V, fH = 100kHz. The bandwidth is much lower than in the low-gain amplifier with the diode-connected loads. For these parameters:

( ) DH If ⋅= AkHz/ 44 µ

There is a clear tradeoff between current and bandwidth. Note also that if we increase the length of our transistors to increase VA, we increase gain but loose bandwidth.


Lecture 10 1

Noise and Precision in Circuits

Why are we interested in noise? Noise sets the fundamental limits of performance in all physical systems. Noise is very important in designing low-power systems due to the low current and voltage levels used to represent signals. Noise limits analog circuits to finite levels of precision and dictates logic thresholds in digital circuits.

Noise in a circuit can be divided into two types:

• Extrinsic noise: Noise which arises from a source external to the circuit under consideration and is coupled in somehow. Often called interference.

• Intrinsic noise: Noise generated within the circuit elements, caused by the random motion of charge carriers.

Quantifying Noise

In most physical systems, the average value of noise (voltage noise or current noise, typically) is zero. The exact value of the noise signal at any point in time is unpredictable (otherwise it wouldnt be noise), so how can we quantify this signal?

We can observe the noise over a period of time and construct a probability density function, or PDF, that describes the distribution of voltage (or current) fluctuations over time:

t

v(t)

Vn

v

p(v)

-Vn

Noise is often described by its root mean square value, or rms value, where


Lecture 10 2

( ) ( )∫≡T

nrmsn dttvT

V0

21

( ) ( )∫≡T

nrmsn dttiT

I0

21

If the noise PDF is Gaussian, then the rms value of the noise corresponds to the standard deviation σ of the Gaussian distribution. Most of the area under a Gaussian curve occurs within 3σ of the mean. Thus, the peak-to-peak noise (as you would observe it on an oscilloscope, for example) is approximately six times the rms value of the noise (if that noise is Gaussian).

It is common to talk about the noise power. Noise power is the power a noise source would dissipate if connected to a 1Ω resistor. Voltage and current noise power are expressed as:

( )∫≡T

nn dttvT

V0

22 1

( )∫≡T

nn dttiT

I0

22 1

If the noise PDF is Gaussian, then the noise power corresponds to the variance σ 2 of the Gaussian distribution. The units of noise power are V2 or A2.

Signal-to-Noise Ratio The accuracy of analog circuits is often expressed in terms of the signal-to-noise ratio, or SNR. SNR is defined as the ratio of signal power to noise power.

( )

( )rmsn

rmssignal

n

signal

VV

V

V102

2

1010dBlog20log10

power noisepower signallog10SNR ==≡

In many cases our signal will be a sine wave. The rms value of a sine wave with amplitude A is 2A .

Example: The signal in a circuit is a sine wave with a peak-to-peak voltage of 1.0 V. The rms noise voltage is 20 µV. What is the signal-to-noise ratio? A = (1.0V) / 2 = 500 mV

Vsignal(rms) = 2A = 354 mV


Lecture 10 3

( )

( )dB 85

V 20mV 354log20log20SNR 1010dB

===µrmsn

rmssignal

VV

We can look at a noise signal in the frequency domain and talk about the noise spectrum. A common type of noise is white noise, where the noise power is equal at all frequencies. We can define the noise power spectral density, or PSD, as the amplitude of the spectrum at a particular frequency. Units are V2/Hz or A2/Hz.

It is interesting to consider the SNR of digital systems where the noise is quantization error. Quantization noise is not Gaussian, but we can nevertheless compute its rms value. (We wont go into the details here.) If a signal is quantized to N bits (and is quantized at full scale so that the minimum signal value is encoded as 0 and the maximum signal value is encoded as 2N-1), then

N62SNRdB

+≅

Example: What is the SNR of a signal quantized with 14-bit accuracy?

dB 8662SNRdB

=+≅ N

Every bit we add to a digital representation adds 6 dB to our SNR (assuming a full-scale signal).


Lecture 10 4

Well spend most of our time studying intrinsic noise since it is more fundamental and cannot be reduced by careful layout or circuit construction. Before moving on, however, lets look at some common varieties of extrinsic noise.

Extrinsic Noise in VLSI Circuits

• Capacitive coupling When wires overlap or run next to each other, there is some capacitance between them that can couple a signal in one wire to the other wire.

Cp Cp

• Inductive coupling Parallel wires can also be magnetically coupled (mutual inductance), but this is only a problem at very high frequencies.

I


Lecture 10 5

• Substrate coupling The substrate in bulk CMOS processes is a resistive medium. Although we try to tie it to ground, local voltage deviations are unavoidable.

n+ n+ p+ n+ n+

p-

p+ p+

n-

p-

n+ n+ n+

The effects of substrate coupling can be greatly reduced by the use of guard rings rings of p+ diffusion (in a p- substrate) tied to ground surrounding sensitive circuits.

• Power supply noise. Power derived from an electrical outlet will have a 60 Hz component, plus harmonics (120 Hz, 180 Hz, etc.). In Europe, its 50 Hz (and 100 Hz, 150 Hz, etc.) Switching power supplies are awful. Linear power supplies are better. Batteries are nearly noise free. The power-supply rejection ratio (PSRR) is the standard metric for power supply noise immunity.

Even if we use a clean power supply, we can get local L(di/dt) power supply noise due to inductance in bond wires or local power routing. In typical


Lecture 10 6

packages, the bond wire inductance is between 3-9 nH depending on the pin. (Bond wire capacitance is typically between 1 and 6 pF and bond wire resistance 0.04Ω to 0.4Ω.)


Lecture 10 7

Intrinsic Noise

Even if we pay careful attention to circuit layout to reduce coupling and use a noise-free power supply, we cannot build a noise-free circuit. There are fundamental physical limits of precision in circuits, and these limits are dictated by the random movements of charge carriers. There are three basic types of intrinsic noise that we will cover: thermal noise, shot noise, and 1/f noise.

Thermal Noise

Thermal noise is a manifestation of the random, thermally-induced motion of charge carriers in any conductor. Thermal noise is seen in resistors and in above threshold MOS transistors, where the channel acts a bit like a resistor (i.e., drift current dominates).

( ) kTRfSv 4= (units: V2/Hz)

fkTRVn ∆⋅= 42 (units: V2)

( )RkTfSi

4= (units: A2/Hz)

fRkTI n ∆⋅= 42 (units: A2)


Lecture 10 8

Shot Noise

Shot noise results from the random motion of charges over a potential barrier. Shot noise is seen in p-n junctions and in subthreshold MOS transistors, where diffusion currents dominate.

( ) qIfSi 2= (units: A2/Hz)

fqII n ∆⋅= 22 (units: A2)

VS VD

VG

elec

tron

ener

gy

volta

ge

reference voltage

κVG diffusion

ee 6961-009: low power circuit design -...

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