Edited byPhilip Garrou, Mitsumasa Koyanagi, and Peter Ramm

Handbook of 3D Integration3D Process Technology

Volume 3

Edited by

Philip Garrou, Mitsumasa Koyanagi,

and Peter Ramm

Handbook of 3D Integration

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Handbook of 3D IntegrationTechnology and Applications of 3DIntegrated Circuits

2008

Print ISBN: 978-3-527-33265-6

Edited by Philip Garrou, Mitsumasa Koyanagi,and Peter Ramm

Handbook of 3D Integration

3D Process Technology

Editors

Dr. Philip GarrouMicroelectronic Consultants of North Carolina3021 Cornwallis RoadResearch Triangle Park, NC 27709USA

Mitsumasa KoyanagiTohoku UniversityNew Industry Creation Hatchery Center6-6-10 Aza-Aoba, AramakiSendai 980-8579Japan

Dr. Peter RammFraunhofer EMFTDevice and 3D IntegrationHansastraße 27d80686 M€unchenGermany

All books published byWiley-VCH are carefullyproduced. Nevertheless, authors, editors, andpublisher do not warrant the information containedin these books, including this book, to be free oferrors. Readers are advised to keep in mind thatstatements, data, illustrations, procedural details orother items may inadvertently be inaccurate.

Library of Congress Card No.: applied for

British Library Cataloguing-in-Publication DataA catalogue record for this book is available from theBritish Library.

Bibliographic information published by the DeutscheNationalbibliothekThe Deutsche Nationalbibliothek lists thispublication in the Deutsche Nationalbibliografie;detailed bibliographic data are available on theInternet at < http:// dnb.d-nb.d e> .

#2014 Wiley-VCH Verlag GmbH & Co. KGaA,Boschstr. 12, 69469 Weinheim, Germany

All rights reserved (including those of translation intoother languages). No part of this book may bereproduced in any form – by photoprinting,microfilm, or any other means – nor transmitted ortranslated into a machine language without writtenpermission from the publishers. Registered names,trademarks, etc. used in this book, even when notspecifically marked as such, are not to be consideredunprotected by law.

Print ISBN: 978-3-527-33466-7ePDF ISBN: 978-3-527-67013-0ePub ISBN: 978-3-527-67012-3mobi ISBN: 978-3-527-67011-6oBook ISBN: 978-3-527-67010-9

Cover Design Adam Design, Weinheim, Germany

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Printing and Binding Markono Print Media Pte Ltd,Singapore

Printed on acid-free paper

Contents

List of Contributors XVII

1 3D IC Integration Since 2008 1Philip Garrou, Peter Ramm, and Mitsumasa Koyanagi

1.1 3D IC Nomenclature 11.2 Process Standardization 21.3 The Introduction of Interposers (2.5D) 41.4 The Foundries 61.4.1 TSMC 61.4.2 UMC 71.4.3 GlobalFoundries 71.5 Memory 71.5.1 Samsung 71.5.2 Micron 81.5.3 Hynix 91.6 The Assembly and Test Houses 91.7 3D IC Application Roadmaps 10

References 11

2 Key Applications and Market Trends for 3D Integrationand Interposer Technologies 13Rozalia Beica, Jean-Christophe Eloy, and Peter Ramm

2.1 Introduction 132.2 Advanced Packaging Importance in the Semiconductor

Industry is Growing 162.3 3D Integration-Focused Activities – The Global IP Landscape 182.4 Applications, Technology, and Market Trends 22

References 32

3 Economic Drivers and Impediments for 2.5D/3D Integration 33Philip Garrou

3.1 3D Performance Advantages 333.2 The Economics of Scaling 33

jV

3.3 The Cost of Future Scaling 343.4 Cost Remains the Impediment to 2.5D and 3D Product

Introduction 373.4.1 Required Economics for Interposer Use in Mobile Products 383.4.2 Silicon Interposer Pricing 38

References 40

4 Interposer Technology 41Venky Sundaram and Rao R. Tummala

4.1 Definition of 2.5D Interposers 414.2 Interposer Drivers and Need 424.3 Comparison of Interposer Materials 444.4 Silicon Interposers with TSV 454.5 Lower Cost Interposers 484.5.1 Glass Interposers 484.5.1.1 Challenges in Glass Interposers 494.5.1.2 Small-Pitch Through-Package Via Hole Formation and Ultrathin Glass

Handling 494.5.1.3 Metallization of Glass TPV 514.5.1.4 Reliability of Copper TPVs in Glass Interposers 524.5.1.5 Thermal Dissipation of Glass 534.5.1.6 Glass Interposer Fabrication with TPV and RDL 534.5.2 Low-CTE Organic Interposers 534.5.3 Polycrystalline Silicon Interposer 554.5.3.1 Polycrystalline Silicon Interposer Fabrication Process 564.6 Interposer Technical and Manufacturing Challenges 574.7 Interposer Application Examples 584.8 Conclusions 60

References 61

5 TSV Formation Overview 65Dean Malta

5.1 Introduction 655.2 TSV Process Approaches 675.2.1 TSV-Middle Approach 685.2.2 Backside TSV-Last Approach 685.2.3 Front-Side TSV-Last Approach 695.3 TSV Fabrication Steps 705.3.1 TSV Etching 705.3.2 TSV Insulation 715.3.3 TSV Metallization 715.3.4 Overburden Removal by CMP 725.3.5 TSV Anneal 735.3.6 Temporary Carrier Wafer Bonding and Debonding 745.3.7 Wafer Thinning and TSV Reveal 74

VIj Contents

5.4 Yield and Reliability 75References 76

6 TSV Unit Processes and Integration 79Sesh Ramaswami

6.1 Introduction 796.2 TSV Process Overview 806.3 TSV Unit Processes 826.3.1 Etching 826.3.2 Insulator Deposition with CVD 836.3.3 Metal Liner/Barrier Deposition with PVD 846.3.4 Via Filling by ECD of Copper 846.3.5 CMP of Copper 856.3.6 Temporary Bonding between Carrier and Device Wafer 866.3.7 Wafer Backside Thinning 866.3.8 Backside RDL 876.3.9 Metrology, Inspection, and Defect Review 876.4 Integration and Co-optimization of Unit Processes in Via Formation

Sequence 886.5 Co-optimization of Unit Processes in Backside Processing

and Via-Reveal Flow 896.6 Integration and Co-optimization of Unit Processes in Via-Last Flow 916.7 Integration with Packaging 926.8 Electrical Characterization of TSVs 926.9 Conclusions 96

References 97

7 TSV Formation at ASET 99Hiroaki Ikeda

7.1 Introduction 997.2 Via-Last TSV for Both D2D and W2W Processes in ASET 1037.3 TSV Process for D2D 1057.3.1 Front-Side Bump Forming 1067.3.2 Attach WSS and Thinning 1067.3.3 Deep Si Etching from the Backside 1077.3.4 Liner Deposition 1077.3.5 Removal of SiO2 at the Bottom of Via 1077.3.6 Barrier Metal and Seed Layer Deposition by PVD 1107.3.7 Cu Electroplating 1107.3.8 CMP 1107.3.9 Backside Bump 1117.3.10 Detach WSS 1117.3.11 Dicing 1127.4 TSV Process for W2W 1137.4.1 Polymer Layer Coat and Development 114

Contents jVII

7.4.2 Barrier Metal and Seed Layer Deposition 1147.4.3 Cu Plating 1147.4.4 CMP 1157.4.5 First W2W Stacking (Face to Face) 1167.4.6 Wafer Thinning and Deep Si Etching 1167.4.7 TSV Liner Deposition and SiO2 Etching of Via Bottom 1177.4.8 Barrier Metal and Seed Layer Deposition and Cu Plating 1177.4.9 CMP 1177.4.10 Next W2W Stacking 1187.5 Conclusions 119

References 119

8 Laser-Assisted Wafer Processing: New Perspectives in Through-SubstrateVia Drilling and Redistribution Layer Deposition 121Marc B. Hoppenbrouwers, Gerrit Oosterhuis, Guido Knippels, andFred Roozeboom

8.1 Introduction 1218.2 Laser Drilling of TSVs 1218.2.1 Cost of Ownership Comparison 1218.2.2 Requirements for an Industrial TSV Laser Driller 1238.2.3 Drilling Strategy 1248.2.3.1 Mechanical 1248.2.3.2 Optical 1258.2.4 Experimental Drilling Results 1268.3 Direct-Write Deposition of Redistribution Layers 1268.3.1 Introduction on Redistribution Layers 1268.3.2 Direct-Write Characteristics 1278.3.3 Direct-Write Laser-Induced Forward Transfer 1288.3.4 LIFT Results 1308.4 Conclusions and Outlook 131

References 132

9 Temporary Bonding Material Requirements 135Rama Puligadda

9.1 Introduction 1359.2 Technology Options 1369.2.1 Tapes and Waxes 1369.2.2 Chemical Debonding 1369.2.3 Thermoplastic Bonding Material and Slide Debonding 1369.2.4 Debonding Using Release Layers 1379.3 Requirements of a Temporary Bonding Material 1389.4 Considerations for Successful Processing 1399.4.1 Application of the Temporary Bonding Adhesive to the Device Wafer

and Bonding to Carrier 1399.4.2 Moisture and Contaminants on Surface 139

VIIIj Contents

9.4.3 Total Thickness Variation 1409.4.4 Squeeze Out 1409.5 Surviving the Backside Process 1419.5.1 Edge Trimming 1429.5.2 Edge Cleaning 1429.5.3 Temperature Excursions in Plasma Processes 1439.5.4 Wafer Warpage due to CTE Mismatch 1439.6 Debonding 1449.6.1 Debonding Parameters in Slide-Off Debonding 1449.6.2 Mechanical Damage to Interconnects 144

References 145

10 Temporary Bonding and Debonding – An Update on Materialsand Methods 147Wilfried Bair

10.1 Introduction 14710.2 Carrier Selection for Temporary Bonding 14810.3 Selection of Temporary Bonding Adhesives 15110.4 Bonding and Debonding Processes 15210.5 Equipment and Process Integration 155

References 156

11 ZoneBOND1: Recent Developments in Temporary Bondingand Room-Temperature Debonding 159Thorsten Matthias, J€urgen Burggraf, Daniel Burgstaller,Markus Wimplinger, and Paul Lindner

11.1 Introduction 15911.2 Thin Wafer Processing 15911.2.1 Thin Wafer Total Thickness Variation 16111.2.2 Wafer Alignment 16311.3 ZoneBOND Room-Temperature Debonding 16311.4 Conclusions 165

References 166

12 Temporary Bonding and Debonding at TOK 167Shoji Otaka

12.1 Introduction 16712.2 Zero Newton Technology 16812.2.1 The Wafer Bonder 16812.2.2 The Wafer Debonder 17012.2.3 The Wafer Bonder and Debonder Equipment Lineups 17012.2.4 Adhesives 17012.2.5 Integration Process Performance 17212.3 Conclusions 174

References 174

Contents jIX

13 The 3MTM Wafer Support System (WSS) 175Blake Dronen and Richard Webb

13.1 Introduction 17513.2 System Description 17513.3 General Advantages 17713.4 High-Temperature Material Solutions 17813.5 Process Considerations 18013.5.1 Wafer and Adhesive Delamination 18013.5.2 LTHC Glass Delamination 18113.6 Future Directions 18113.6.1 Thermal Stability 18113.6.2 Elimination of Adhesion Control Agents 18213.6.3 Laser-Free Release Layer 18313.7 Summary 183

Reference 184

14 Comparison of Temporary Bonding and DebondingProcess Flows 185Matthew Lueck

14.1 Introduction 18514.2 Studies of Wafer Bonding and Thinning 18614.3 Backside Processing 18614.4 Debonding and Cleaning 188

References 189

15 Thinning, Via Reveal, and Backside Processing – Overview 191Eric Beyne, Anne Jourdain, and Alain Phommahaxay

15.1 Introduction 19115.2 Wafer Edge Trimming 19215.3 Thin Wafer Support Systems 19415.3.1 Glass Carrier Support System with Laser Debonding

Approach 19615.3.2 Thermoplastic Glue Thin Wafer Support System – Thermal

Slide Debondable System 19615.3.3 Room-Temperature, Peel-Debondable Thin Wafer Support

Systems 19715.4 Wafer Thinning 19815.5 Thin Wafer Backside Processing 20215.5.1 Via-Middle Thin Wafer Backside Processing: “Via-Reveal”

Process 20215.5.1.1 Mechanical Via Reveal 20215.5.1.2 “Soft” Via Reveal 20215.5.2 Via-Last Thin Wafer Backside Processing 203

References 205

Xj Contents

16 Backside Thinning and Stress-Relief Techniquesfor Thin Silicon Wafers 207Christof Landesberger, Christoph Paschke, Hans-Peter Sp€ohrle,and Karlheinz Bock

16.1 Introduction 20716.2 Thin Semiconductor Devices 20716.3 Wafer Thinning Techniques 20816.3.1 Wafer Grinding 20916.3.2 Wet-Chemical Spin Etching 21016.3.3 CMP Polishing 21116.3.4 Plasma Dry Etching 21216.3.5 Dry Polish 21316.3.6 Chemical–Mechanical Grinding (CMG) 21416.4 Fracture Tests for Thin Silicon Wafers 21416.5 Comparison of Stress-Relief Techniques for Wafer Backside

Thinning 21616.6 Process Flow for Wafer Thinning and Dicing 22016.7 Summary and Outlook on 3D Integration 222

References 223

17 Via Reveal and Backside Processing 227Mitsumasa Koyanagi and Tetsu Tanaka

17.1 Introduction 22717.2 Via Reveal and Backside Processing in Via-Middle Process 22717.3 Backside Processing in Back-Via Process 23217.4 Backside Processing and Impurity Gettering 23417.5 Backside Processing for RDL Formation 237

References 239

18 Dicing, Grinding, and Polishing (Kiru Kezuru and Migaku) 241Akihito Kawai

18.1 Introduction 24118.2 Grinding and Polishing 24118.2.1 Grinding General 24118.2.1.1 Grinding Method 24118.2.1.2 Rough Grinding and Fine Grinding 24218.2.1.3 The Grinder Polisher 24318.2.2 Thinning 24318.2.2.1 Stress Relief 24518.2.2.2 Die Attach Film 24618.2.2.3 All-in-One System 24618.2.2.4 Dicing Before Grinding 24618.2.3 Grinding Topics for 3DIC Such as TSV Devices 24618.2.3.1 Wafer Support System 246

Contents jXI

18.2.3.2 Edge Trimming 24718.2.3.3 Grinding to Improve Flatness 24818.2.3.4 Higher Level of Cleanliness 24818.2.3.5 Via Reveal 24918.2.3.6 Planarization 24918.3 Dicing 25018.3.1 Blade Dicing General 25018.3.1.1 Dicing Method 25018.3.1.2 Blade Dicing Point 25018.3.1.3 Blade 25118.3.1.4 Optimization of Process Control 25218.3.1.5 Dicer 25218.3.1.6 Dual Dicing Applications 25218.3.2 Thin Wafer Dicing 25318.3.3 Low-k Dicing 25418.3.4 Other Laser Dicing 25418.3.4.1 Ablation 25418.3.4.2 Laser Full Cut Application 25518.3.4.3 Stealth Dicing (SD) 25618.3.5 Dicing Topics for 3D-IC Such as TSV 25718.3.5.1 Cutting of Chip on Chip (CoC) and Chip on Wafer (CoW) 25818.3.5.2 Singulation of CoW and Wafer on Wafer (WoW) 25918.4 Summary 260

Further Reading 260

19 Overview of Bonding and Assembly for 3D Integration 261James J.-Q. Lu, Dingyou Zhang, and Peter Ramm

19.1 Introduction 26119.2 Direct, Indirect, and Hybrid Bonding 26219.3 Requirements for Bonding Process and Materials 26319.4 Bonding Quality Characterization 26719.5 Discussion of Specific Bonding and Assembly Technologies 26919.6 Summary and Conclusions 273

References 274

20 Bonding and Assembly at TSMC 279Douglas C.H. Yu

20.1 Introduction 27920.2 Process Flow 28020.3 Chip-on-Wafer Stacking 28120.4 CoW-on-Substrate (CoWoS) Stacking 28320.5 CoWoS Versus CoCoS 28320.6 Testing and Known Good Stacks (KGS) 28420.7 Future Perspectives 285

References 285

XIIj Contents

21 TSV Packaging Development at STATS ChipPAC 287Rajendra D. Pendse

21.1 Introduction 28721.2 Development of the 3DTSV Solution for Mobile

Platforms 28921.3 Alternative Approaches and Future Developments 293

References 294

22 Cu–SiO2 Hybrid Bonding 295L�ea Di Cioccio, S. Moreau, Loïc Sanchez, Floriane Baudin, Pierric Gueguen,Sebastien Mermoz, Yann Beilliard, and Rachid Taibi

22.1 Introduction 29522.2 Blanket Cu–SiO2 Direct Bonding Principle 29622.2.1 Chemical–Mechanical Polishing Parameters 29622.3 Aligned Bonding 29922.3.1 Wafer-to-Wafer Bonding 29922.3.2 Die-to-Wafer Bonding in Pick-and-Place Equipment 29922.3.3 Die-to-Wafer by the Self-Assembly Technique 30022.4 Blanket Metal Direct Bonding Principle 30222.5 Electrical Characterization 30422.5.1 Wafer-to-Wafer and Die-to-Wafer Copper-Bonding Electrical

Characterization 30422.5.2 Reliability 30722.5.3 Thermal Cycling 30722.5.4 Stress Voiding (SIV) Test on 200 �C Postbonding Annealed

Samples 30822.5.5 Package-Level Electromigration Test 30922.6 Conclusions 310

References 311

23 Bump Interconnect for 2.5D and 3D Integration 313Alan Huffman

23.1 History 31323.2 C4 Solder Bumps 31523.3 Copper Pillar Bumps 31623.4 Cu Bumps 31923.5 Electromigration 320

References 322

24 Self-Assembly Based 3D and Heterointegration 325Takafumi Fukushima and Jicheol Bea

24.1 Introduction 32524.2 Self-Assembly Process 32524.3 Key Parameters of Self-Assembly on Alignment Accuracies 327

Contents jXIII

24.4 How to Interconnect Self-Assembled Chips to Chips orWafers 328

24.4.1 Flip-Chip-to-Wafer 3D Integration 32924.4.2 Reconfigured-Wafer-to-Wafer 3D Integration 331

References 332

25 High-Accuracy Self-Alignment of Thin Silicon Dieson Plasma-Programmed Surfaces 335Christof Landesberger, Mitsuru Hiroshima,Josef Weber, and Karlheinz Bock

25.1 Introduction 33525.2 Principle of Fluidic Self-Alignment Process for

Thin Dies 33525.3 Plasma Programming of the Surface 33625.4 Preparation of Materials for Self-Alignment Experiments 33725.5 Self-Alignment Experiments 33825.6 Results of Self-Alignment Experiments 33925.7 Discussion 34125.8 Conclusions 342

References 343

26 Challenges in 3D Fabrication 345Douglas C.H. Yu

26.1 Introduction 34526.2 High-Volume Manufacturing for 3D Integration 34626.3 Technology Challenges 34626.4 Front-Side and Backside Wafer Processes 34626.5 Bonding and Underfills 35026.6 Multitier Stacking 35226.7 Wafer Thinning and Thin Die and Wafer Handling 35326.8 Strata Packaging and Assembly 35626.9 Yield Management 35926.10 Reliability 36026.11 Cost Management 36226.12 Future Perspectives 362

References 364

27 Cu TSV Stress: Avoiding Cu Protrusion and Impacton Devices 365Eric Beyne, Joke De Messemaeker, and Wei Guo

27.1 Introduction 36527.2 Cu Stress in TSV 36527.3 Mitigation of Cu Pumping 36827.4 Impact of TSVs on FEOL Devices 371

References 378

XIVj Contents

28 Implications of Stress/Strain and Metal Contaminationon Thinned Die 379Kangwook Lee and Mariappan Murugesan

28.1 Introduction 37928.2 Impacts of Cu Contamination on Device Reliabilities in Thinned

3DLSI 37928.3 Impacts of Local Stress and Strain on Device Reliabilities

in Thinned 3DLSI 38628.3.1 Microbump-Induced Stresses in Stacked LSIs 38728.3.2 Microbump-Induced TMS in LSI 38828.3.3 Microbump-Induced LMS 389

References 391

29 Metrology Needs for 2.5D/3D Interconnects 393Victor H. Vartanian, Richard A. Allen, Larry Smith, Klaus Hummler,Steve Olson, and Brian Sapp

29.1 Introduction: 2.5D and 3D Reference Flows 39329.2 TSV Formation 39429.2.1 TSV Etch Metrology 39529.2.2 Liner, Barrier, and Seed Metrology 39729.2.3 Copper Fill Metrology (TSV Voids) 39929.2.4 Cross-Sectional SEM (Focused Ion Beam Milling Sample

Preparation) 40029.2.5 X-Ray Microscopy and CT Inspection 40029.2.6 Stress Metrology in Cu and Si 40229.3 MEOL Metrology 40429.3.1 Edge Trim Inspection 40529.3.2 Bond Voids and Bond Strength Metrology 40629.3.2.1 Acoustic Microscopy: Operation 40729.3.2.2 Acoustic Microscopy for Defect Inspection and Review 40729.3.2.3 Other Bond Void Detection Techniques 40829.3.3 Bond Strength Metrology 40929.3.4 Bonded Wafer Thickness, Bow, and Warp 41029.3.4.1 Chromatic White Light 41129.3.4.2 Infrared Interferometry 41229.3.4.3 White Light Interferometry (or Coherence Scanning

Interferometry) 41429.3.4.4 Laser Profiling 41529.3.4.5 Capacitance Probes 41629.3.4.6 Differential Backpressure Metrology 41729.3.4.7 Acoustic Microscopy for Measuring Bonded Wafer Thickness 41729.3.5 TSV Reveal Metrology 41829.4 Assembly and Packaging Metrology 42029.4.1 Wafer-Level C4 Bump and Microbump Metrology

and Inspection 421

Contents jXV

29.4.2 Package-Level Inspection: Scanning Acoustic Microscopy 42229.4.3 Package-Level Inspection: X-Rays 42429.5 Summary 426

References 427

Index 431

XVIj Contents

List of Contributors

Richard A. AllenNational Institute of Standardsand Technology (NIST)100 Bureau DriveGaithersburg, MD 20899USA

Wilfried BairSUSS MicroTec AGSchleißheimer Str. 9085748 GarchingGermany

Floriane BaudinCEA/LETIDepartment of HeterogeneousIntegration on Silicon17, rue des Martyrs38054 Grenoble CEDEX 9France

Jicheol BeaTohoku UniversityNew Industry Creation HatcheryCenter (NICHe)6-6-10 Aza-Aoba, AramakiSendai 980-8579Japan

Rozalia BeicaYole DeveloppementLe Quartz75, cours Emile Zola69100 Lyon-VilleurbanneFrance

Yann BeilliardCEA/LETIDepartment of HeterogeneousIntegration on Silicon17, rue des Martyrs38054 Grenoble CEDEX 9France

Eric BeyneIMEFKapeldreef 753001 LeuvenBelgium

Karlheinz BockFraunhofer Research Institution forSolid State Technologies EMFTHansastrasse 27d80686 MunichGermany

jXVII

J€urgen BurggrafE. Thallner GmbHEV GroupDI-Erich-Thallner-Straße 14782 Sankt Florian am InnAustria

Daniel BurgstallerE. Thallner GmbHEV GroupDI-Erich-Thallner-Straße 14782 Sankt Florian am InnAustria

Joke De MessemaekerIMEFKapeldreef 753001 LeuvenBelgium

L�ea Di CioccioCEA/LETIDepartment of HeterogeneousIntegration on Silicon17, rue des Martyrs38054 Grenoble CEDEX 9France

Blake Dronen3M Electronics Markets MaterialsBuilding 225-3S-06St. Paul, MN 55144-1000USA

Jean-Christophe EloyYole DeveloppementLe Quartz75, cours Emile Zola69100 Lyon-VilleurbanneFrance

Takafumi FukushimaTohoku UniversityNew Industry Creation HatcheryCenter (NICHe)6-6-10 Aza-Aoba, AramakiSendai 980-8579Japan

Philip GarrouMicroelectronic Consultants ofNorth Carolina3021 Cornwallis RoadResearch Triangle Park, NC 27709USA

Pierric GueguenCEA/LETIDepartment of HeterogeneousIntegration on Silicon17, rue des Martyrs38054 Grenoble CEDEX 9France

Wei GuoIMEFKapeldreef 753001 LeuvenBelgium

Mitsuru HiroshimaPanasonic Factory Solutions Co., Ltd.2-7 Matsuba-cho, KadomaOsaka 571-8502Japan

Marc B. HoppenbrouwersDutch Organization of AppliedScientific Research (TNO)5600 HE EindhovenThe Netherlands

XVIIIj List of Contributors

Alan HuffmanRTI International3040 East Cornwallis RoadPost Office Box 12194Research Triangle Park, NC 27709USA

Klaus HummlerSEMATECH257 Fuller RoadAlbany, NY 12203USA

Hiroaki IkedaASET1-28-38 Shinkawa, Chuo-kuTokyo 104-0033Japan

Anne JourdainIMEFKapeldreef 753001 LeuvenBelgium

Akihito KawaiDISCO CORPORATION13-11 Omori-Kita 2 Chome, Ota-kuTokyo 143-8580Japan

Guido KnippelsAdvanced Laser SeparationInternational (ALSI)Platinawerf 20-G6641 TL BeuningenThe Netherlands

Mitsumasa KoyanagiTohoku UniversityNew Industry Creation HatcheryCenter6-6-10 Aza-Aoba, AramakiSendai 980-8579Japan

Christof LandesbergerFraunhofer Research Institution forSolid State Technologies EMFTHansastrasse 27d80686 MunichGermany

Kangwook LeeTohoku UniversityNew Industry Creation HatcheryCenter6-6-10 Aza-Aoba, AramakiSendai 980-8579Japan

Paul LindnerE. Thallner GmbHEV GroupDI-Erich-Thallner-Straße 14782 Sankt Florian am InnAustria

James J.-Q. LuRensselaer Polytechnic InstituteDepartment of Electrical, Computer,and Systems Engineering110 8th St.Troy, NY 12160USA

Matthew LueckRTI International3040 East Cornwallis RoadPost Office Box 12194Research Triangle Park, NC 27709USA

List of Contributors jXIX

Dean MaltaRTI International3040 East Cornwallis RoadPost Office Box 12194Research Triangle Park, NC 27709USA

Thorsten MatthiasE. Thallner GmbHEV GroupDI-Erich-Thallner-Straße 14782 Sankt Florian am InnAustria

S. MoreauCEA/LETIDepartment of HeterogeneousIntegration on Silicon17, rue des Martyrs38054 Grenoble CEDEX 9France

Sebastien MermozCEA/LETIDepartment of HeterogeneousIntegration on Silicon17, rue des Martyrs38054 Grenoble CEDEX 9France

Mariappan MurugesanTohoku UniversityNew Industry Creation HatcheryCenter6-6-10 Aza-Aoba, AramakiSendai 980-8579Japan

Steve OlsonState University of NY (SUNY) atAlbanyCollege of Nanoscience andEngineering (CNSE)Albany, NY 12203USA

Gerrit OosterhuisDutch Organization of AppliedScientific Research (TNO)5600 HE EindhovenThe Netherlands

Shoji OtakaTOK (Tokyo Ohka Kogya) Co. Ltd.150 Nakamaruko, Nakahara-kuKawasaki 211-0012Japan

Christoph PaschkeFraunhofer Research Institution forSolid State Technologies EMFTHansastrasse 27d80686 MunichGermany

Rajendra D. PendseSTATS ChipPAC#05-17/20 Techpoint10 Ang Mo Kio StreetSingapore 569059Singapore

Alain PhommahaxayIMEFKapeldreef 753001 LeuvenBelgium

Rama PuligaddaBrewer Science2401 Brewer DriveRolla, MO 65401USA

Sesh RamaswamiApplied Materials, Inc.Silcon Systems Group974 East Arques AvenueSunnyvale, CA 94085USA

XXj List of Contributors

Peter RammFraunhoffer EMFTDevice and 3D IntegrationHansastrasse 27d80686 MunichGermany

Fred RoozeboomDutch Organization of AppliedScientific Research (TNO)5600 HE EindhovenThe Netherlands

Loïc SanchezCEA/LETIDepartment of HeterogeneousIntegration on Silicon17, rue des Martyrs38054 Grenoble CEDEX 9France

Brian SappSEMATECH257 Fuller RoadAlbany, NY 12203USA

Larry SmithSEMATECH257 Fuller RoadAlbany, NY 12203USA

Hans-Peter Sp€ohrleFraunhofer Research Institution forSolid State Technologies EMFTHansastrasse 27d80686 MunichGermany

Venky SundaramGeorgia TechSchool of Electrical andComputational Engineering777 Atlantic Drive NWAtlanta, GA 3033-0250USA

Rachid TaibiCEA/LETIDepartment of HeterogeneousIntegration on Silicon17, rue des Martyrs38054 Grenoble CEDEX 9France

Tetsu TanakaTohoku UniversityGraduate School of BiomedicalEngineering6-6-01 Aza-Aoba, AramakiSendai 980-8579Japan

Rao R. TummalaGeorgia TechSchool of Electrical andComputational Engineering777 Atlantic Drive NWAtlanta, GA 3033-0250USA

Victor H. VartanianSEMATECH257 Fuller RoadAlbany, NY 12203USA

Richard Webb3M Electronics Markets MaterialsBuilding 225-3S-06St. Paul, MN 55144-1000USA

List of Contributors jXXI

Josef WeberFraunhofer Research Institution forModular Solid State TechnologyEMFTHansastrasse 27d80686 MunichGermany

Markus WimplingerE. Thallner GmbHEV GroupDI-Erich-Thallner-Straße 14782 Sankt Florian am InnAustria

Douglas C.H. YuTSMCNo.8, Li-Hsin Rd. Vl, Science ParkHsinchuTaiwan 300-78P. R. China

Dingyou ZhangRensselaer Polytechnic InstituteDepartment of Electrical, Computerand Systems Engineering110 8th St.Troy, NY 12160USA

XXIIj List of Contributors

13D IC Integration Since 2008Philip Garrou, Peter Ramm, and Mitsumasa Koyanagi

In Volume 1, we covered some of the history of the development of the 3Dintegrated circuit (3D IC) concept and we direct you to that chapter for suchcontent [1].Since the first two volumes of the Handbook of 3D Integration appeared in 2008,

significant progress has been made to bring 3D IC technology to commercializa-tion. This chapter will attempt to summarize some of the key developments duringthat period.We previously described 3D IC integration as “an emerging, system level integra-

tion architecture wherein multiple strata (layers) of planar devices are stacked andinterconnected using through-silicon (or other semiconductor material) vias (TSV)in the Z direction” as depicted schematically in Figure 1.1a and in cross section inFigure 1.1b [1].With the continued pressure to miniaturize portable products and the near

universal agreement that scaling as we have known it is soon coming to an end [2],a perfect storm has been created. The response to this dilemma at both the deviceand the package level has been to move into the third dimension.It is commonly accepted that chip stacks wire-bonded down to a common

laminate base and stacked packages such as package-on-package (PoP) are cate-gorized as “3D packaging.” Transistor design has also gone vertical [3] as Intel [4]and others move to “finfet” stacked transistor structures at the 22 nm generation.These are compared pictorially in Figure 1.2.In Figure 1.3, we compare system-on-chip (SoC), 3D packaging, and 3D IC with

through-silicon via (TSV) in various performance categories [5].

1.13D IC Nomenclature

Since 2008 there have been attempts to further refine the nomenclature for 3D ICintegration, although it has not yet been universally adopted in publications.In 2009 the International Technology Roadmap for Semiconductors (ITRS)

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Handbook of 3D Integration: 3D Process Technology, First Edition.Edited by Philip Garrou, Mitsumasa Koyanagi, and Peter Ramm.� 2014 Wiley-VCH Verlag GmbH & Co. KGaA. Published 2014 by Wiley-VCH Verlag GmbH & Co. KGaA.

proposed the following nomenclature in an attempt to define the possible differentlevels of connections possible as circuits are deconstructed onto separate strata(see Table 1.1) [6].

1.2Process Standardization

3D IC requires three new pieces of technology: (1) insulated conductive viasthrough a thinned silicon substrate (i.e., TSV); (2) thinning and handlingtechnology for wafers as thin as 50mm or less; (3) technology to assemble andpackage such thinned chips.

Figure1.1 3D IC with TSV: (a) schematic (courtesy of IMEC) and (b) cross section (courtesy ofIBM). Note that the IBM cross section is connected at a higher (fatter) on chip interconnectlevel.

Figure 1.2 3D packaging, 3D finfet transistors, and 3D IC integration.

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Figure 1.3 Comparison of SoC, 3D packaging, and 3D IC [5].

Table 1.1 2009 ITRS roadmap [6].

Level Suggested name Supply chain Key characteristics

Package 3D packaging (3D-P) OSATassem-bly printedcircuit board(PCB)

� Traditional packaging of intercon-nect technologies, for example,wire-bonded die stacks, package-on-package stacks

� Also includes die in PCB integration� No through-Si vias

Bond-pad 3D wafer-level pack-age (3D-WLP)

Wafer-levelpackaging

� WLP infrastructure, such as RDLand bumping

� 3D interconnects are processed afterthe IC fabrication, “post IC passiva-tion” (via-last process). Connectionson bond-pad level

� TSV density requirements followbond-pad density roadmaps

Global 3D stacked integratedcircuit/3D system-on-chip (3D-SIC/3D-SoC)

Wafer fab � Stacking of large circuit blocks(tiles, IP blocks, memory banks),similar to an SoC approach buthaving circuits physically on differ-ent layers

� Unbuffered I/O drivers (low C, littleor no ISD protection on TSVs)

� TSV density requirement signifi-cantly higher than 3D-WLP: Pitchrequirement down to 4–16mm

(continued)

1.2 Process Standardization 3

In the mid-2000s, practitioners were bewildered by the multitude of proposedtechnical routes to 3D IC. It has become clear, since then, that for mostapplications, the preferred process flow is what has been called a “via-middle”approach, where the TSVs are inserted after front-end transistor formation andearly on during the on-chip interconnect process flow. This requires that TSVs aremanufactured in back end of fab, not during or after the assembly process. Thisrequires that TSV fabrication will be done by vertically integrated IDMs orfoundries. TSV technology appears to be stabilized as depicted in Figure 1.4and Table 1.2.

1.3The Introduction of Interposers (2.5D)

Many believe the introduction of interposers (also known as 2.5D) was due to thefailure of 3D IC, but this is not the case. Interposers were and are needed due to thelack of chip interface standardization and the need for a better thermal solutionthan is currently available for some 3D stacking situations.The term “2.5D” is usually credited to Ho Ming Tong from Advanced

Semiconductor Engineering (ASE), who in 2009 (or even earlier) declared that wemight need an intermediate step toward 3D since the infrastructure and standardswere not ready yet. The silicon interposer, Tong felt, would get us a major part ofthe way there, and could be ready sooner than 3D technology, thus the term “2.5D,”which immediately caught on with other practitioners [7].2.5D interposers resemble silicon multichip module technology of the 1990s,

with the addition of TSV [8]. In today’s applications, they provide high-densityredistribution layers (RDLs), so the chips can be connected either through theinterposer or next to each other on the top surface of the interposer as shown in

Table 1.1 (Continued)

Level Suggested name Supply chain Key characteristics

Intermediate 3D-SIC Wafer fab � Stacking of smaller circuit blocks,parts of IP blocks stacked in verticaldimensions

� Mainly wafer-to-wafer stacking� TSV density requirements veryhigh: Pitch requirement down to1–4mm

Local 3D IC Wafer fab � Sticking of transistor layers� Common back-end-of-line (BEOL)interconnect stack on multiplelayers of front-end-of-line (FEOL)

� Requires 3D connections at thedensity level of local interconnects

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Figure 1.5. The latter is the superior thermal solution since all chips can beattached to a heat sink for cooling.Interposers will add cost and probably will not be a broadly accepted solution for

low-cost mobile products, which would prefer straight 3D stacking [9].

Table 1.2 Standard 3D IC process flow options.

Process Preferred option Alternative options available

TSV formation Bosch deepreactive ionetching (DRIE)

Laser

TSV Insulation SiO2 PolymerConductor Cu W pSiProcess flow Via-middle Via-last

(backside)a)Via-first(for pSi)

Via-last(front side)

StackingBonding IMC Cu–Cu Oxide

bondingPolymerbonding

Hybrid bonding(oxide–metal orpolymer–metal)

Thin waferhandling

On carrier On stack

a) Preferred flow for CMOS image sensors.

Figure 1.4 Standard 3D IC process flow. Courtesy of Yole Developpement.

1.3 The Introduction of Interposers (2.5D) 5

1.4The Foundries

1.4.1TSMC

In October 2012, TSMC announced the readiness of their 2.5D CoWoSTM (chip-on-wafer-on-substrate) technology within their “Open Innovation Platform1” and madepublic their reference flows supporting CoWoS. Several EDA companies includingCadence, Mentor, Synopsys, and Ansys were announced as partners in the CoWoSreference flow [10]. Their first public CoWoS demonstrator vehicle (Figure 1.6)included logic and DRAM in a single module using the wide I/O interface [11].Early TSMC customers reportedly included Xilinx, AMD, Nvidia, Qualcomm,

Texas Instruments, Marvell, and Altera [12], with Xilinx being the first to productionin late 2011.

Figure 1.5 Interposer configurations.

Figure 1.6 2.5D TSMC demonstrator vehicle [11].

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