eda cloud full custom flow outline

Microsoft Word - EDA_Cloud_FC_v4.3.doc1. EDA Cloud...……………………2
2. Laker layout…….…………………………....4
3. Laker ADP …………………………………...7
4. Hspice ………………………………………18

EDA Cloud
help CBDK( CBDK)
Cloud GUI”&”
)

PDK
help PDK
TN90GUTM:
== Hspice models=================================================

)
termianl nedit & (example: nedit inv.sp&)

TN90GUTM PDK:

1.5 Laker Main WindowFileExportStream GDS
6
Calibre
1.6 LayoutVerifyCalibreStart RVE 7 Calibre

terminal help PDK
/PDK/TN90GUTM/Laker/laker_90nm_MM_3XTM_1P9M_6X1Z1U_22b.tf
/PDK/TN90GUTM/Laker/laker_90nm_MM_3XTM_1P9M_6X1Z1U_22b.tf

PMOS4Create Instance (i)”analogADP” Library
pmos4 cell INV4
NMOS4 Create Instance (i) ”analogADP”
Library nmos4 cell INV4
cap Create Instance (i)”analogADP” Library
cap cell INV4
Create Port InputOutputInOut Port

10

simulationEnvironment Setting

DC : Sweep Variable tempStart :0Stop :85Step :1000
Tran : Step :0.001n, Stop :100u, Start :0

simulation model librarymodel file

Netlistmodel file

13 Netlist File(ex :Simulation_t.sp)
Qhspice
Qhspice HSPICE_result showq job

Qhspice HSPICE_result
3.15 Laker ADP ToolsAnnotate OP Load
HSPICE_result hspice.log
Main Window File Expand Schematic LakerL3
Library Name T90Project

3.20 Laker Main WindowFileExportStream GDS
5.Calibre DRC6.Calibre LVS7.Calibre LPE
17
Calibre

cp r /cad/PDK/T18 ~ (~ )
tsmc18rf
T18 Laker L3 3.17 Model Map File
~/T18/Laker model.map ( Analog IC
Design using ADP and Laker, 2014)

Laker ADPHspice
Hspice batch mode

model name
.probe.print
4.5 termianl help batch_cmd Hpsice batch mode
Qhspice
HSPICE_result) multithread
Qhspice inv.sp mt 4
EDA Cloud
19
)
Wave Marching IO Update
Waveform Files ( Ctrl+A)

5.2 ~/TN90GUTM/Virtuoso cds.lib
display.drf.cdsinit:
cd ~/TN90GUTM/Virtuoso
TN90GUTMVirtuoso technology file:
TN90Project library copy
cds.libLibrary Manager tsmcN90rf library
5.3 Library Manager FileNewCell View… INV4
layout
Calibre
5.6 LayoutCalibreStart RVE 5 Calibre

PDK Virtuoso icfb
mkdir PDK
cd PDK
help PDK
4.6 Library Name TN90Project
Technology File tsmcN90rf

6.2 Library Manager FileNewCell View… INV4
schematic
pch cellView Symbol
nch cellView Symbol

Instance INV4 Symbol View
analogLib
Tools Analog Environment( 19 ) Virtuoso Analog
Design Environment, ADE( 110)

ADE SetupSimulator/Directory/Host
( 111) Simulator spectre
Project Directory simulation
Section(ex: ss_lib) Change

Analyses

6.9 ADEOutputs Save All ( To Be Saved Select On
Schematic schematic ESC
)

().scs EDA Cloud
Sever
job

6.16 INV4 Schematic Design SynthesisLayout XLCreate
New INV4 Virtuoso Layout
6.17 INV4 Virtuoso Layout DesignGen From Source
Layout
Calibre
6.19 LayoutCalibreStart RVE 7 Calibre

LAYOUT WINDOW CLIP YES
EX: LAYOUT WINDOW CLIP YES
LAYOUT WINDOW 21.72 20.915 27.52 39.685

Qcalibre CALIBRE_result showq
job Calibre_result

( Hierarchical DRC)
Qcalibre drc TN90GUITM_DRC.rule
DRC multicputurbo_all)
Qcalibre help
( Qcalibre)
DRC Laker Virtuoso
Database Database Type DRC/REC
CALIBRE_result DRC_RES.db

INCLUDE TN90GUTM_DRC_RULE
Qcalibre calibre_DRC.log

TN90GUTM_DummyODPO.rule Qcalibre DRC

Instance dummy cell import layout
dummy cell(0, 0)

INCLUDE TN90GUTM_DummyMetal_rule

INCLUDE TN90GUTM_DummyODPO_rule
Qcalibre DRC TN90GUITM_LVS.rule
LAYOUT PATH GDS
SOURCE PATH spice
//PEX NETLIST out_netlist CALIBREVIEW 1 SOURCENAMES LOCATION
//PEX NETLIST out_netlist SPECTRE 1 SOURCENAMES
//PEX NETLIST out_netlist DSPF 1 SOURCENAMES

DRC ICSTATION YES
:
ISOLATE SHORTS RECOGNIZE GATES
Ex: LVS ISOLATE SHORTS YES
LVS RECOGNIZE GATES ALL
Layout Virtual Connect:
Ex: VIRTUAL CONNECT NAME ?
Ex: VIRTUAL CONNECT NAME “VDDD”
( Layout Connect nets named: VDDD)
Dummy Pattern LVS
Dummy Pattern( AB, RC Dummy Pattern)
Calibre LVS GUI SetupLVS Options
Gates
job Calibre_result

multicpu Hierarchical LVS Flat LVS
turbo_all)
37
extract_spice Extract Layout Netlist
EX:

Laker Virtuoso
svdb
Qcalibre calibre_LVS.log

Qcalibre LPE TN90GUITM_LPE.rule
LAYOUT PATH GDS
SOURCE PATH spice

DRC ICSTATION YES
:
Layout Virtual Connect:
Ex: VIRTUAL CONNECT NAME ?
Ex: VIRTUAL CONNECT NAME “VDDD”
( Layout Connect nets named: VDDD)

Netlist”//” out_netlist

Ex:
//PEX NETLIST CREATE SMASHED DEVICE NAMES YES
Hspice INV_PEX.sp
:
Ex: PEX REDUCE TICER 1000
Enable CC reduction Absolute: 0.1fF, Scale: 1
Ex: PEX REDUCE CC ABSOLUTE 0.1 SCALE 1
Enable MinCap reduction COMBINE 0.1 REMOVE 0
Ex: PEX REDUCE MINCAP COMBINE 0.1
PEX REDUCE MINCAP REMOVE 0
Enable MinRes reduction COMBINE 0.1 SHORT 0
Ex: PEX REDUCE MINRES COMBINE 0.1
PEX REDUCE MINRES SHORT 0

Options NetlistReduction and CC
40
job Calibre_result

xrc lpe xrc 3
Qcalibre –lpe –rcrcrcc xrc
3

Ex:
PEX NETLIST out_netlist CALIBREVIEW 1 SOURCENAMES LOCATION
//PEX NETLIST CREATE SMASHED DEVICE NAMES YES
9.7.2 Layout(Virtuoso)CalibrSetupCalibre View

CalibreView Netlist File Browse 9.7.1
Qcalibre –lpen CALIBREVIEW Netlist
Cellmap File Calibre calview.cellmap
Calibre View Type schematic

eda cloud full custom flow outline

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