ecen474/704: (analog) vlsi circuit design spring 2016 · 2018. 9. 10. · ecen474/704: (analog)...
TRANSCRIPT
![Page 1: ECEN474/704: (Analog) VLSI Circuit Design Spring 2016 · 2018. 9. 10. · ECEN474/704: (Analog) VLSI Circuit Design Spring 2016. Announcements • Turn in your 0.18um NDA form and](https://reader035.vdocuments.us/reader035/viewer/2022062610/6114b7e7cbfbeb773e54486c/html5/thumbnails/1.jpg)
Sam PalermoAnalog & Mixed-Signal Center
Texas A&M University
Lecture 2: MOS Transistor Modeling
ECEN474/704: (Analog) VLSI Circuit Design Spring 2016
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Announcements
• Turn in your 0.18um NDA form and email me your linux username
• No Lab this week• Lab 1 starts Feb 2 or 3
• Current Reading• Razavi Chapters 2 & 16
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Agenda
• MOS Transistor Modeling• Threshold Voltage, VT
• DC I-V Equations• Body Effect• Subthreshold Region
3
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Threshold Voltage, VT
• Before a “channel” forms, the device acts as 2 series caps from the oxide cap and the depletion cap
• If VG is increased to a sufficient value the area below the gate is “inverted” and electrons flow from source to drain
4
[Razavi]
• Applying a positive voltage to the gate repels holes in the p-substrate under the gate, leaving negative ions (depletion region) to mirror the gate charge
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222
VT Definition
• The threshold voltage, VT, is the voltage at which an “inversion layer” is formed• For an NMOS this is when the
concentration of electrons equals the concentration of holes in the p- substrate
5
[Silva]
Note, will be defined later
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- 6 -
TAMU-474-09 J. Silva-Martinez
MOS Transistor
substrate
N+ N+
VS=0VG<0
VD>0
P
P+
BD
S
B G
N-type transistor
+ + + + + + + + + +
Accumulation: Two diodes back to backD-S current is zero
P+
Substrate
N+ N+
VS=0VG>0
VD>0
P
P+
B
- - - - - - - - - -
Inversion: Channel is connecting D and SD-S current is possible
IDS
Under this condition, there are 3 possible applications:
Subthreshold (extremely low-voltage low-power applications)
Linear region (voltage controlled resistor, linear OTA’s, multipliers, switches)
Saturation region (Amplifiers)Quasi free electronsN+
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TAMU-474-09 J. Silva-Martinez
MOS Transistor
D
S
B G
N-type transistorTriode Region (D-S channel is complete)
In this condition, there are 3 possible applications:
Subthreshold (extremely low-voltage low-power applications)
Linear region (voltage controlled resistor, linear OTA’s, multipliers, switches)
Saturation region (Amplifiers)
substrate
N+ N+
VS=0VG>0
VD ~ 0
P
P+
B
- - - - - - - - - -
Channel
substrate
N+ N+
VS=0VG>0
VD > 0
P
P+
B
Saturation Region (D-S channel is incomplete)
N-channel
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TAMU-474-09 J. Silva-Martinez
MOS Transistor
N-type transistor
substrate
N+ N+
VS=0 VT >VG>0 VD>0
P (NA)
P+
B
Subthreshold (weak inversion)
Mobile carriersconcentration< NA
- - - - - - - -
substrate
N+ N+
VS=0VG>VT VD>0
P (NA)
P+
B
Saturation (Strong inversion)
Mobile carriersConcentration> NA
- - - - - - - -
Subthreshold
Linear region
Saturation
VD
S
IDS
Subthreshold (extremely low-voltage low-power applications)
Linear region (voltage controlled resistor, linear OTA’s, multipliers, switches)
Saturation region (Amplifiers)
VGS2
VGS3
VGS1
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MOS Equations in Triode Region (Small VDS)
9
[Sedra/Smith]
DSDSTGSOXnDS
V
CSTGSOXn
L
DS
nTCSGSOXDS
nn
TCSGSTGC
TGCOXd
d
VVVVLWCI
xdvxVVVWCdxI
dxxdvVxVVWCII
dxxdvxE
VxVVVxV
VxVWCxQ
xQdtdx
dxdQ
dtdQI
DS
21
))((
))((
:VelocityElectron
)( :Voltage Channel-to-Gate
)()( :Density Charge lIncrementa
)( :Drain toSource fromCurrent
00
DSII
n :mobilityElectron
:area gateunit per eCapacitanc
ox
oxox t
C
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Triode or Linear Region
• Channel depth and transistor current is a function of the overdrive voltage, VGS-VT, and VDS
• Because VDS is small, VGC is roughly constant across channel length and channel depth is roughly uniform
10
x=0 x=L
VDS
DSDSTnGSOXnDS VVVVCLWI 5.0
00 V DSVLV LxVxV DS
LxVVxVVxV DSGSGSGC
TnGSox
DS
VVCLWR
1
For small VDS
[Silva]
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TAMU-474-09 J. Silva-Martinez
MOS Equations in Linear Region
L
W
tox
N+ N+
VDSGNDVGS
Drain current: Expression used in SPICE level 1
DSDSTGSOXnD VV5.0VVCLWI
W
tox
N+ N+
VDSGNDVGS
Non-linear channel
Linear approximation
VDS
ID
VOV=VGS-VT
IDSAT
VGS > VT
• This expression peaks whenVDS=VGS-VT, which we will call the “overdrive voltage” or VOV
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Triode Region Channel Profile
12
[Sedra/Smith]
• If VGC is always above VT throughout the channel length, the transistor current obeys the triode region current equation
• Recall that the channel charge density is (VGC(x) - VT)
Channel Voltage, V(x)
LxVVVxVVVxV DSOVTGSTGC
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Saturation Region Channel Profile
13
[Sedra/Smith]
• When VDS VGS-VT=VOV, VGC no longer exceeds VT, resulting in the channel “pinching off” and the current saturating to a value that is no longer a function of VDS (ideally)
LxVVVxVVVxV DSOVTGSTGC
Channel Voltage, V(x)
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LxVVVxVVVxV DSOVTGSTGC
Saturation Region
• Channel “pinches-off” when VDS=VGS-VT and the current saturates• After channel charge goes to 0, the high lateral field “sweeps” the
carriers to the drain and drops the extra VDS voltage
14
x=0 x=L
VDSsat=VGS-VT
00 V DSVLV LxVxV DS
VDS-VDSsat
TnGSOV VVV
[Silva]
22 TnGS
OXnDS VV
LWCI
22 TnGSOXn
VVVDS
DSTnGSOXnDS VV
LWCVVVV
LWCI
TnGSDS
x=L’
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NMOS ID – VDS Characteristics
15
TNGSOV VVV [Sedra/Smith]
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MOS “Large-Signal” Output Characteristic
16
[Sedra/Smith]
Note: Vov=VGS-VT
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What about the PMOS device?
• The current equations for the PMOS device are the same as the NMOS EXCEPT you swap the current direction and all the voltage polarities
17
DSDSTnGSOXnDS VVVVCLWI 5.0 SDSDTpSGOXpSD VVVVC
LWI 5.0
22 TnGSOXnDS VVCL
WI 22 TpSGOXpSD VVCL
WI
Linear:
Saturation:
NMOS PMOS
NMOS PMOS
[Silva]
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PMOS ID – VSD Characteristics
18
[Karsilayan]
(Saturation)
TPSGOV VVV
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Body Effect
• As VS becomes positive w.r.t. VB, a larger depletion region forms, which requires a higher VG to form a channel
• The net result is that VTincreases due to this “body effect”
• Note, it also works in reverse, as if you increase VB w.r.t. VS, then VT lowers
19
[Razavi]• If the body and source potential are
equal, a certain VG=VT0 is required to form an inversion layer
FFMSox
depFMST C
QV 222 0
0
21
0
0.4V to0.3 from ranges typically
2 t,coefficieneffect Body
22
ox
subsi
FSBFTT
CNq
VVV
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TAMU-474-08 J. Silva-Martinez
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MOS MODEL: SPICE LEVEL-II
•Drain current, Triode region
•Drain Current, Saturation region
•Threshold voltage (zero bias)
•Threshold voltage
•KP and (Spice Model)
DSDSTnGSOXnDS VVVVCLWI 5.0 :NMOS
SDSDTpSGOXpSD VVVVCLWI 5.0 :PMOS
22
:NMOS TnGSOXnDS VVCL
WI
22
:PMOS TpSGOXpSD VVCL
WI
000 22
SBVTFSBFTT VVVV
OX
subsiOX C
NqCKP
2;
FFMSTV 220
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Subthreshold Region
• So far we have assumed that ID=0 when VGS<VT
• However, in reality an exponentially decreasing current exists for VGS<VT
21
• VT values are often set by extrapolating above threshold data to current values of zero or infinite Ron
• A rough value often used is the VGS which yields ID/W=1A/m
1 with 1dec./60mV is slope ldsubthreshosteepest The
factory nonidealit a is 1
current scale a is where
exp :region ldsubthreshoIn
0
0
I
kTqVII GS
D
[Razavi]
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Subthreshold Current & VT Scaling
22
• This subthreshold current prevents lowering VT excessively
• Assuming VT=300mV and has an 80mV subthresholdslope, then the Ion/Ioff ratio is only on the order of 10^(300/80)=5.6e3
• Reducing VT to 200mV drops the Ion/Ioff ratio to near 316
• If we have a large number of “off” transistors on our chip these subthreshold currents add up quickly, resulting in significant power dissipation
• This is a huge barrier in CMOS technology scaling and one of the main reasons Vdd scaling has slowed
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Next Time
• MOS Transistor Modeling• Small-Signal Model• Spice Models
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