Final Exam ECE3670 December 12, 2013 1:30 pm Time: 3 Hours Instructions 1. Read all questions 2. Answer all questions 3. Assume open circuit loads unless otherwise specified Rubric for design problems (Questions 1-3) 100% - Correct answer with complete explanation -30% - Fails to meet one design criteria, but other wise correct -60% - Fails to meet two design criteria, but other wise correct -10% - Incorrect units, but otherwise correct answer -20% - Exceeds limits for power supply or otherwise biases devices in an useable state -10 to 20% - Math or analysis error per incidence (more if it is serious)

Unless otherwise specified assume For BJTs assume 2N3904 For MOSFETs assume Vt=1.5V, k=10 mA/V2

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Marks

10 1. Design an H-biased common emitter amplifier with a) output bias point of 4-8V, b) gain greater than 30 and a total power of less than 1 mW dissipated in RC. VCC=+9V Find R1, R2, RC and RE

10 2. Design a differential amplifier to achieve a) single sided gain greater than 15, b) Rin>2 0k ohms. Output differential voltage swing should be greater than 3Vp-p. Use a current mirror to bias the amplifier. For biasing purposes assume the inputs are grounded. Vdd=15V Vss=-15V If a common mode voltage of +3V were added, how would the power dissipation change in each transistor?

Marks

10 3. Design an emitter follower based regulated power supply. The output voltage is to be 5.7-

6.3V. VIN will range from 10 to 12V. If the maximum power that can be dissipated in the transistor is 1W, what is the maximum current that can be supplied to the load resistor RL?

Marks

8 4. For a common emitter amplifier, if the supply voltage is increased will the high frequency cutoff frequency change? Assume IC remains constant. Why?

8 5. Draw the equivalent circuit diagram for the common emitter amplifier shown below

including the parasitic capacitance C1. In terms of the amplifier gain what would the formula be for the equivalent input capacitance including only C1?

8 6. What is the gain of the common source amplifier with an RS of 2k? VCC=+9V. Rb is assumed to be large. How much power is dissipated in T1?

8 7. Design a Wein-bridge oscillator for an oscillation frequency of 1500Hz. Include some

form of non-linear gain to prevent saturation of the output. What would the output amplitude of your oscillator be?

8 8. For an CMOS inverter µPCox = 40 µA/V2 , Vth= 0.25V and VDD=1.8 V. For a CL=200 fF, what W/L ratio is required to achieve a risetime of 0.1 ns. Assuming output rising to 0.9 VDD. How much energy is dissipated each clock cycle?

Formula Sheet

BJT

€

gm =ICVT

€

re =VTIE

≈VTIC

€

rπ =VTIB

= βVTIC

$

% &

'

( ) rO =

VAIC

€

α =β

β +1 iC = ISe

vBEVT

€

VT = 26mV T = 25°C( ) FET

gm = knVOV =2IDVOV

ID =12kn VGS −Vt( )2 = 1

2knVOV

2

ID = kn VGS −Vt( )VDS −

12VDS2"

#$

%

&'2

For CE amplifier

€

Rin = RB β +1( ) re + RE( )

€

Av = −α RC RL( )re + RE

€

Rout = RC

For Emitter follower

€

Rin = RB β +1( ) re + ro RL( )[ ]

€

Av ≈1

€

Rout = ro re +RSIG RB

β +1#

$ %

&

' (

€

Cπ = τ fICVT

+C je

1− Vbe

V je

%

& ' '

(

) * *

mje

€

Cµ =C jc

1+Vcb

V jc

"

# $ $

%

& ' '

mjc

For CE amplifier

€

RL' = ro RC RL

€

Cin = Cπ + Cµ 1+ gmRL'( )

€

RSIG' = rπ rx + RB RSIG( )[ ]

€

f H =1

2πCinRSIG'

For CS amplifier

Rin =∞ Av =−gm RD RL( )1+ gmRS

Rout = RD Av =−2RDIDVOV

For Differential amplifier

€

Ad = −gmRC ≈RC

re + RE

single side ½

€

ACM = −αRC2REE

€

CMRR = gmREE Rout = 2 RC ro( )

€

CMRR = 20log Ad

ACM

€

Rid = 2 β +1( ) re + RE( ) Active load

€

Ad = gm roNPN roPNP( )

Wien Bridge Oscillator

€

ωo =1CR

€

R2R1

= 2

€

L jω( ) =1+

R2R1

3+ j ωCR − 1ωCR

$

% &

'

( )

Digital Circuits

Ron ≈1

µCOXWL

"

#$

%

&' VDD − Vth( )

=1

kn' WL

"

#$

%

&' VDD − Vth( )

€

trise ≈43RonpCL

€

t fall ≈43RonnCL

€

Pav =CLVDD

2

τ= fCLVDD

2

I peak ≈

12kn

WL

"

#$

%

&'VDD2− Vth

"

#$

%

&'2

Relaxation oscillator

€

β =R1

R1 + R2

€

τ = CR

€

T = 2τ log 1+ β1−β%

& '

(

) *

2N3904

Zener  Data