ece 353: digital systems design fall 2011 slide set #2: combinational logic textbook: sections 2.9 -...

ECE 353: Digital Systems Design Fall 2011

Slide Set #2: Combinational LogicTextbook: Sections 2.9 - 2.10

Review Material: Sections 2.1-2.8

Instructor: Dr. Tor [email protected]

Slide Set 2,

Introduction to Slide Set #2

• In this slide set we review what a digital system is, and then talk about the overall design flow. Following this, we’ll learn talk about VHDL and what it is and is not. Then we’ll learn some basic VHDL syntax.

Slide Set 2,

Learning Objectives• By the time we finish talking about this slide set in lectures you

should be able to:– Describe the high level organization of a typical digital circuit.– Define the term “combination logic” and list several ways of specifying a

combinational logic circuit.– Explain what VHDL is in general terms; explain why VHDL is important;

and list the different levels of design possible using VHDL.– Describe the steps in the digital system design flow.– Define the term “synthesis” (gate level synthesis) in the context of digital

system design and explain the relationship of VHDL and synthesis

Slide Set 2,

Digital Systems Overview

Input OutputControl Datapath

Memory

CPU

Mostly sequential Mostly combinational

Von Neumann model of a computer

Slide Set 2,

Combinational Circuits

A combinational logic block (CLB) is defined as having its output(s) depending only on its current inputs at any given time.

CLBinputs outputs

Can be implemented using logic gates, look-up tables (LUTs), or other means.

Slide Set 2,

How to specify the behaviour of a CLB?

1. English: “The block has an output of 1 when an even number of inputs are 1”. Note: sometimes ambiguous

2. Truth table:

a b c f 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0

Slide Set 2,

3. A Boolean Equation:

f = a’ b’ c’ + a b’ c’ + a’ b c’ + …….

Exercise: fill in the rest of the equation Note this can be simplified:

f = a xor b xor c

4. A schematic diagram:

Exercise: draw a schematic diagram for this circuit

5. VHDL or Verilog

We’ll talk about this soon

Slide Set 2,

What you should remember about combinational logic:

1. How to write a logic equation from an English description

2. How to minimize a logic equation (ie. produce an equivalent equation with fewer literals)

- using KMAPs - Section 4.1 - 4.3 in the textbook (review if necessary!) - Really, these minimization techniques are usually performed automatically by CAD tools, so we won’t focus on them here.

Slide Set 2,

What is VHDL?It is NOT a programming language!It is an IEEE Standard method of describing hardware.

Why do we need a new method to describe hardware? What is wrong with schematics?

With VHDL, you can specify hardware in two ways: Structurally: what the hardware looks like (like schematics) Behaviourally: what the hardware does

But the real power of VHDL is that it lets you combine structural and behavioural descriptions in the same design!

Slide Set 2,

Example: Some possible ways of describing a processor in VHDL.

Entirely Behavioural: You could write a single piece of VHDL code that describes exactly what the processor will do.

Why you might do this: - eliminates any misunderstandings among designers what the processor will do - you can simulate the design to make sure there is nothing you haven’t thought about (what if you forgot to include a carry bit?) - you can send off another team of software engineers to create a compiler (they will have a complete functional model of the design to work with).

Note: at this stage, you have NOT done the hardware design yet. You have specified what the hardware will do.

Slide Set 2,

Behavioural Functional Units: You might divide the design into major functional units, and then write behavioural code to specify what

each block does. Then, you can write structural code to specify how the blocks are connected.

Why you might do this: - allows you to farm out work to individual designers (each designer will know exactly what his/her block is to do) - allows you to experiment with different architectural decisions (how wide should the bus be, should we have a separate floating point unit, etc). - allows you to swap in/out detailed designs for each module as they are completed.

Note: at this point, you still have not done the hardware design. You have broken the design into major functional units and made major architectural decisions.

Slide Set 2,

RTL-Level Design: For each functional unit, specify what the hardware

looks like, in terms of basic building blocks (ie. mux, combinational blocks, state machines, etc).

Why you might do this: - It allows you do determine exactly what the hardware will look like. You can simulate the design to make sure it matches the behavioural code created earlier, or if you did not create the behavioural code, you can make sure it matches your understanding of the design. - You can simulate it with descriptions of the other functional units (either behavioural or RTL versions) to make sure there are no unintended interactions - Can accurately estimate how fast/big your chip will be - This description can serve as a source for synthesis (more on this later)

Slide Set 2,

Gate-Level Design: Can specify your design in terms of individualgates. Often this is created automatically from the RTL description(more on this later) but you might want to specify

- exactly how certain blocks should be constructed (ie. if you think you can do a better job at state assignment than the synthesis tool, if you think you can implement the circuit in some clever, tricky way that the synthesis tool might not figure out)

- In most cases, humans are smarter than synthesis tools! - at least, today that is often the case - a few years from now, if researchers have their way, that might not be the case

So, the fact that you can specify hardware at all thesedifferent levels is why VHDL is becoming so popular

Slide Set 2,

Another use of VHDL: A Source for Synthesis

Today’s definition of Synthesis: Automatically creating an optimized gate-level description from an RTL-level description:

Tomorrow’s definition of Synthesis: Automatically creating an optimized gate-level description from a behavioural description

Synthesis Tool(Synopsys, Quartus II, ISE...)

RTL-LevelVHDL Code

RequiredSpeed/Size

ImplementationTarget

Optimized Gate-Level Description of Circuit

Slide Set 2,

Engineers design before starting to build. This is as true in Digital Systems Design as it is in Civil Engineering.

You probably would not want to live in a house that was put together without forethought as to whether it was strong enough to stand up. A circuit that is not well thought out before hand is less likely to work correctly.

Slide Set 2,

Design Flow

B&V: Figure 2.29. A typical CAD system.

Design conception

VHDLSchematic capture

DESIGN ENTRY

Design correct?

Functional simulation

No

Yes

No

Synthesis

Physical design

Chip configuration

Timing requirements met?

Timing simulation

Step 1: Describe System, e.g. “flow chart”, “requirements”.

Step 2: Think about the hardware you want to build! Consider which hardware building blocks are appropriate.

Step 3: Only then, write VHDL

WARNING: If you do step 3 without or before the other two, you are (very likely) going to end up with a circuit that does not work or only works “some of the time” (which is not good enough)

Slide Set 2,

So then what is Verilog?

Verilog is another hardware description language

Verilog can also be used as a source for synthesis

Verilog and VHDL are about equally common -> Who will win?

But, once you learn VHDL, you can pick up Verilog real fast!-> In EECE 479, you will learn Verilog, just to make sure you

are bilingual

Slide Set 2,

The most important thing to remember from this lecture:

VHDL was not meant as a hardware design languageIt was meant as a hardware description language

There are many things that we can describe, but can not build

Therefore, we should not expect all VHDL code to be “synthesizable”

Slide Set 2,

Combinational Logic in VHDL:

The basic construct for modeling a digital system in VHDL is calleda design entity. Each hardware block is described in one designentity.

A VHDL Design Entity consists of two parts:

An Interface description: - describes the inputs and outputs of the block - in VHDL, denoted by the keyword entity

A Body: - describes either what the block does and/or what it is composed of - in VHDL, denoted by the keyword architecture

Slide Set 2,

Example:VHDL description of an Exclusive-Or gate:

entity XOR_GATE isport (a, b: in BIT;

z: out BIT);end XOR_GATE; -- (“end entity” would work as well)architecture XOR_BEHAV of XOR_GATE isbegin

z<=a xor b;end XOR_BEHAV; -- (“end architecture” would work as well)

Slide Set 2,

Example: a more complex circuit

entity BIG_CIRCUIT isport ( a, b, c : in BIT;

z : out BIT);end BIG_CIRCUIT;architecture BIG_BEHAV of BIG_CIRCUIT isbegin

z <= (not a and b) or (b and not c);end BIG_BEHAV;

Slide Set 2,

Things to note about the entity part:

Ports are signals that flow into or out of the designThe direction of flow is called the mode of the port

Possible modes: in, out, inout, linkage, bufferType information (eg. BIT) declares a set of legal values for the

port. A signal of type BIT can be either a 1 or 0. Other types are possible (more on this later)

Things to note about the architecture part:Each entity might have several architectures (one behavioural,

one structural for example). Therefore, must name each architecture (eg. MY_DEFN). Common names are BEHAVIOURAL, STRUCTURAL, DATAFLOW, etc.

Slide Set 2,

A circuit with multiple outputs:

entity MULTI_BLOCK isport (A, B,C,D : in BIT;

X,Y,Z : out BIT);end MULTI_BLOCK;architecture MY_ARCH of MULTI_BLOCK isbegin

X <= A and B and C;Y <= C and not D;Z <= A xor B xor D;

end MY_ARCH;

Note: all three outputs performed concurrently.

Slide Set 2,

Logic circuits and VHDLOne more example:

entity UNKNOWN isport ( IN1, IN2, IN3 : in BIT;

OUT1, OUT2 : out BIT);end UNKNOWN ;architecture MY_ARCH of UNKNOWN isbegin

OUT1 <= IN1 xor IN2 xor IN3;OUT2 <= (IN1 and IN2) or (IN1 and IN3) or (IN2 and IN3);

end MY_ARCH;

Slide Set 2,

SignalsAn alternative definition of the XOR gate:

entity ALT_XOR isport ( a, b: in BIT; z: out BIT);

end entity ALT_XOR;architecture ALT_ARCH of ALT_XOR is

signal s1, s2: BIT;begin

s1 <=not a and b;s2<=not b and a;z <=s1 or s2;

end architecture;

Exercise: Show that this the same as an exclusive or gate.We have defined two INTERNAL signals. Sometimes this results in simpler definitions (not in this case, though)

Two Internal Signals(NOTE: we put these before “begin”)

Slide Set 2,

Modes of Ports:Ports can be in, out, or inoutRule: signals that are in can not be written to (can not appear onthe left side of a signal assignment) and signals that are out cannot be read from (can not appear on the right side of a signalassignment statement).

Seems obvious, but it means this is illegal:

entity BAD_EXAMPLE isport (A, B, C, D : in bit; X, Y_BAR : out bit);

end BAD_EXAMPLE ;architecture BAD_ARCH of BAD_EXAMPLE isbegin

X <= (A and B) or C;Y_BAR <= X nand D;

end BAD_ARCH;

ILLEGAL! (X is an output)

Slide Set 2,

Use an internal signal to fix this problem:

entity GOOD_EXAMPLE isport (A, B, C, D : in bit;

X, Y_BAR : out bit);end GOOD_EXAMPLE ;architecture GOOD_ARCH of GOOD_EXAMPLE is

signal s1: BIT;begin

s1 <= (A and B) or C;X <= s1;Y_BAR <= s1 nand D;

end GOOD_ARCH;

Add internal signal s1, assign X <= s1, and use s1 for the final assignment of Y_BAR

Note: ports can also be inout; in that case, there are no restrictions

Slide Set 2,

So a recipe for specifying combinational logic in VHDL:

1. Write a boolean expression for each output

2. Include each boolean expression as a signal assignment within an architecture description (as in the full-adder example earlier).

This will work, and you can use it. But, there are more efficient and easier ways to do it. Coming soon...

Slide Set 2,

By the way,

- VHDL is case-insensitive, and spaces and new lines can appear anywhere (except in the middle of a keyword)

- Comments can appear anywhere, using two dashes

-- The rest of this line is a comment

In your assignments (and any VHDL code you might write out in the real world), please use lots of comments!

Slide Set 2,

ece 353: digital systems design fall 2011 slide set #2: combinational logic textbook: sections 2.9 -...

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