combinational design, part 3: functional blocks chapter 3 (sections 6, 7, 8, 9)
TRANSCRIPT
Combinational Design,Part 3: Functional
Blocks
Chapter 3(Sections 6, 7, 8, 9)
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Topics
• Rudimentary Logic Functions:Value fixing, Transferring, and Inverting
• Common Logic Functions♦ Decoders♦ Encoders♦ Multiplexers
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Value Fixing, Transferring, Inverting
• 4 possible functions of one variable
• constants (0,1)
• Transfer• Invert
Table 3-3
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Enable
• Enable is a common input to logic functions
• See it in memories, and logic building blocksWhich we will Discuss next
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Decoders
• Typically n inputs and 2n outputs • The output line corresponding to
the input code is high
1-to-2 Line Decoder
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2-to-4-Line Decoder
Note that the 2-4-line made up of 2 1-to-2- line decoders and 4 AND gates.
Decoder Examples
A1
0
0
1
1
A0
0
1
0
1
D0
1
0
0
0
D1
0
1
0
0
D2
0
0
1
0
D3
0
0
0
1
(a)
D0 A1 A0
D1 A1 A0
D2 A1 A0
D3 A1 A0
(b)
A1
A0
=
=
=
=
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2-to-4 Decoder with Enable
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Truth Table, 3-to-8 Decoder
• Notice the outputs are minterms
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Multi-Level 3-to-8 Decoder
Level 13-to-8 Line decoder
Level 22-to-4 Line decoder using
Level 3:1-to-2 Line decoder
Build 3-to-8 Line decoder
usinglevel 2 & level 1 decoders with 8 2-input AND gates
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Enable Used for Expansion
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Multi-Level 6-to-64 Decoder
…....
B0, B
1, B2, …
, B
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C0, C
1, C2, …
, C
7
= C0B0
= C7B7
D7= C0B7
D8= C1B0
D15= C1B7
….…
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Uses for Decoders
• Binary number might serve to select some operation♦ Computer operation codes are
encoded•Decoder lines might select add
operation, or subtract operation, or multiply operation, etc.
• Memory address lines
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Variations
• At right♦ Enable not♦ Inverted outputs
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Combinational Logic Implementation ExampleUsing a Decoder and OR Gates
Implement the following 3 odd parity functions of the 4 variables (A7, A6, A5, A4)P1 = A7 A5 A4
P2 = A7 A6 A4
P4 = A7 A6 A5
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Implement the following set of odd parity functions of (A7, A6, A5, A4)P1 = A7 A5 A4
P2 = A7 A6 A4
P4 = A7 A6 A5
Finding sum ofminterms expressions
P1 = m(1,2,5,6,8,11,12,15)P2 = m(1,3,4,6,8,10,13,15)P4 = m(2,3,4,5,8,9,14,15)
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Combinational Logic Implementation Example Using a Decoder and OR Gates
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Decoder and OR Gates Example
Implement the following set of odd parity functions of (A7, A6, A5, A4)P1 = A7 A5 A4
P2 = A7 A6 A4
P4 = A7 A6 A5
Finding sum ofminterms expressions
P1 = m(1,2,5,6,8,11,12,15)P2 = m(1,3,4,6,8,10,13,15)P4 = m(2,3,4,5,8,9,14,15)
Find circuit
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0 1 2 3 4 5 6 7 8 9101112131415
A7
A6
A5
A4
P1
P4
P2
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In General: Combinational Logic Implementation Using a Decoder and OR Gates
Implement m functions of n variables with:• Sum-of-minterms expressions
1 decoder; n-to-2n-line (e.g. 4-to-16-line decoder) m OR gates, one for each function (e.g. m = 3)
Solution
• Find the minterms for each output function• OR the minterms together
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Encoder
• Encoder is the opposite of decoder
• 2n inputs♦ or less – 10 inputs in “Decimal to BCD”
encoder: I0, I1, I2, I3, …, I9
• n outputs♦ 4 output lines “Decimal to BCD”encoder
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Truth Table: 8-to-3 Binary Encoder
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Inputs are Minterms
• Can OR the minterms appropriately to get each of the outputs A0, A1, A2
• Example: A0 = D1 + D3 + D5 + D7
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Generating Outputs using OR of Minterms
• A0 = D1 + D3 + D5 + D7
• A1 = D2 + D3 + D6 + D7
• A2 = D4 + D5 + D6 + D7
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What’s the Problem?
• What if D3 and D6 both high?♦ A0 = D1 + D3 + D5 + D7
♦ A1 = D2 + D3 + D6 + D7
♦ A2 = D4 + D5 + D6 + D7
• Simple OR circuits will set A (the output) to 7
= 1
= 1
= 1
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Priority Encoder
• if more than one input is true, produce the code of the input with highest priority♦ i.e. Largest number, usually
• Note “don’t cares”
What if all inputs are zero?
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Need Another Output
• A “Valid” output
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Valid is OR of inputs
Hide
Figure 4-12 Logic Diagram of a 4-Input Priority EncoderFigure 3-24
Hide
Hide
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K Map for A0
• X on an input means the circuit must generate the specified output value for both input possibilities: 0, 1
• A0 = D3 + D1 D2’
• A1 = D2+ D3
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Circuit of Priority Encoder
Figure 4-12 Logic Diagram of a 4-Input Priority EncoderFigure 3-24
A0 = D3 + D1 D2’
A1 = D2 + D3
V = D1+ D2 + D3
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Multiplexers Example: Two Input
Multiplexer
• If s = 0, Y = I0 , else Y = I1
Data Selector(2 to 1 Multiplexer)
I0
I1
Y
s
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Two Input Mux
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Two Input Mux
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Multiplexers:
A multiplexer selects information from an input line and directs the information to an output line
A typical multiplexer has
• n selection control inputs (Sn 1, … S0)
• 2n information data inputs (I2n
1, … I0)
• one output Y
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Multiplexers (continued)
A multiplexer can be designed to have• n selection inputs• m information inputs with m 2n
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A Single Bit 4-to-1 Line Multiplexer
4-to-1-Line Multiplexer
I0
I1
I2
I3
I0
I1
I2
I3
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A Single Bit 4-to-1 Line Multiplexer(cont.)
Logic is a Decoder Plus4 X 2-Input AND gates feeding an OR gate
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2-to-1 Mux
• Select 1 of 2 sets of lines: A & B;
• Practical use:Select a whole 64-bit data bus from one of two sources
each set has 4 lines
Quad
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Three-State Implementation:A Single Bit 4-to-1 Line Multiplexer
Gate input count is 18
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Binary Tree StyleThree-State Implementation:A Single Bit 4-to-1 Line Multiplexer
Gate input count is 14
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Multiplexer-Based Combinational Circuits- Approach 1
Implement m functions of n variables with:• Sum-of-minterms expressions• Use an m-wide 2n-to-1-line multiplexer
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Example: Gray to Binary Code Converter
Design a circuit to convert a 3-bit Gray code to a binary code
Implement m=3 functions (x,y,z)
of n=3 variables (A,B,C) with:• Sum-of-minterms expressions
• Use an m-wide (3-wide) 2n-to-1-line
(8-to-1) multiplexer
GrayA B C
Binaryx y z
0 0 0 0 0 01 0 0 0 0 11 1 0 0 1 00 1 0 0 1 10 1 1 1 0 01 1 1 1 0 11 0 1 1 1 00 0 1 1 1 1
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Example: Gray to Binary Code Converter
It is obvious from thistable that X = C, howeverY and Z are more complex
GrayA B C
Binaryx y z
0 0 0 0 0 01 0 0 0 0 11 1 0 0 1 00 1 0 0 1 10 1 1 1 0 01 1 1 1 0 11 0 1 1 1 00 0 1 1 1 1
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Gray to Binary (continued) Rearrange the table so
that the input combinationsare in counting order
x = C; functions y and z can be implemented usinga dual 8-to-1-line multiplexers as follows:• connect A, B, and C to the multiplexer select
inputs: S2, S1, S0• place y and z on the two multiplexer outputs• apply their respective truth table values to the
inputs
GrayA B C
Binaryx y z
0 0 0 0 0 00 0 1 1 1 10 1 0 0 1 10 1 1 1 0 01 0 0 0 0 11 0 1 1 1 01 1 0 0 1 01 1 1 1 0 1
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Gray to Binary (continued)
D04D05D06D07
S1S0
AB
S2
D03D02D01D00
Out
C
1
1
11
0
00
0
Y
8-to-1MUX
D14D15D16D17
S1S0
AB
S2
D13D12D11D10
Out
C
1
1
11
00
0
0
Z
8-to-1MUX
GrayA B C
Binaryx y z
0 0 0 0 0 00 0 1 1 1 10 1 0 0 1 10 1 1 1 0 01 0 0 0 0 11 0 1 1 1 01 1 0 0 1 01 1 1 1 0 1
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Implementation of any m functions of n variables using an m-wide 2n-to-1 multiplexer: Approach 1
Find the truth table for the functions In the order they appear in the truth table:
• Apply the function input variables to the multiplexer selection control inputs Sn 1, … , S0
• Label the outputs of the multiplexer with the output functions
• Value-fix the information inputs of the multiplexer using the values from the truth table (for don’t cares, apply either 0 or 1)
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Combinational Logic Implementation- Multiplexer Approach 2
Implement any m functions of n + 1 variables by using:• An m-wide 2n-to-1-line multiplexer• A single inverter
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Example: Gray to Binary Code Converter Implement any m
functions of n + 1 variables using:
An m-wide 2n-to-1-line multiplexer
A single inverter
GrayA B C
Binaryx y z
0 0 0 0 0 01 0 0 0 0 11 1 0 0 1 00 1 0 0 1 10 1 1 1 0 01 1 1 1 0 11 0 1 1 1 00 0 1 1 1 1
Implement any 3 functions of 2 + 1 variables using:
An 3-wide 22-to-1-line multiplexer
A single inverter
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Example: Gray to Binary Code Converter
Implement the 3 functions: x, y, z of 2 (A, B) + 1 (C) variables by using:• An 3-wide 22-to-
1-line multiplexer• A single inverter
GrayA B C
Binaryx y z
0 0 0 0 0 01 0 0 0 0 11 1 0 0 1 00 1 0 0 1 10 1 1 1 0 01 1 1 1 0 11 0 1 1 1 00 0 1 1 1 1
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Gray to Binary (continued) Rearrange the table so that the input combinations are in
counting order
• pair rows
• find rudimentary functions
Gray
A B C
Binary
x y z
Rudimentary
Functions of C for y
Rudimentary Functions of
C for z
0 0 0 0 0 0
0 0 1 1 1 1
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 0 0 1
1 0 1 1 1 0
1 1 0 0 1 0
1 1 1 1 0 1
F = C
F = C
F = C
F = C
F = C
F = CF = C
F = C
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Assign the variables & functions to the multiplexer inputs/outputs
Note that this approach (Approach 2) reduces the cost by almost half compared to Approach 1.
Gray to Binary (continued)
S1S0
AB
D03D02D01D00
Out Y
4-to-1MUX
C
C
C
C D13D12D11D10
Out Z
4-to-1MUX
S1S0
AB
C
C
C
CC C
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Combinational Logic Implementation- Multiplexer Approach 2
Implement any m functions of n + 1 variables by using:• An m-wide 2n-to-1-line multiplexer• A single inverter
Design:• Find the truth table for the functions.• Based on the values of the first n variables, separate the truth
table rows into pairs• If the n+1 variable is C, then the set of rudimentary functions
defined on C is S = (0, 1, C, )• For each pair of rows of the truth table and output, choose the
correct rudimentary function, F(C) of the variable C from the set S
• Using the first n variables as the index, value-fix the information inputs to the multiplexer with the corresponding rudimentary functions
• Use the inverter to generate the rudimentary function
C
C
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Demultiplexer
• Takes one input• Out to one of 2n possible
outputs
1-to-4-Line Demultiplexer
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Demux is a Decoder with an Enable
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A Demux Using NAND Gates:A Decoder with an Enable