ECE 331 – Digital System Design

Single-bit Adder Circuitsand

Adder Circuits in VHDL

(Lecture #11)

The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,

and were used with permission from Cengage Learning.

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The Half Adder (HA)

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The Half Adder

0 0 1 1+ 0 + 1 + 0 + 1 0 1 1 10

Sum Carry Sum

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The Half Adder

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Truth Table

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The Half Adder

Exercise:

1. Derive the Boolean expressions for the sum and the carry outputs.2. Draw the associated combinational logic

circuit diagrams.

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The Full Adder (FA)

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The Full Adder

0 0 0 00 0 1 1

+ 0 + 1 + 0 + 1 0 1 1 10

Carry-out Sum

1 1 1 10 0 1 1

+ 0 + 1 + 0 + 1 1 10 10 11

Carry-in

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The Full Adder

A B Cin Sum Cout0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Truth Table

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The Full Adder

Exercise:

1. Derive the Boolean expressions for the sum and the carry outputs.2. Draw the associated combinational logic

circuit diagrams.

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The Full Adder

Exercise:

Design a Full Adder using

2 Half Adders1 OR gate

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The Full Adder

Half Adder

Half Adder

A

B

CinSum

Cout

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More VHDL Fundamentals

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VHDL: Components Specify the logical sub-circuits (i.e. components) that

will be used in a hierarchical design. Define the interface to the sub-circuit.

Uses the same format as the Entity Statement.

Sub-circuits are interconnected using “wires”. This is known as Structural VHDL.

The architecture statement for the sub-circuit may be included in the same file as the upper level design or in a separate file.

If included in a separate file, it must be compiled prior to compilation of the upper level design.

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VHDL: Components

COMPONENT <component name> PORT ( <interface signals> : mode

type ) ;END COMPONENT ;

Component Statement

Component Instantiation<instance name> : <component name> PORT MAP ( <component port names> => <signal names> ) ;

<instance name> : <component name> PORT MAP ( <signal names> ) ;

named association

positional association

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VHDL: Packages

Packages (and libraries) allow frequently used functions and components to be “centrally” located.

Component declarations are included in package files rather than in the VHDL code for the hierarchical design.

The associated VHDL models for the components are included in separate files.

The compiled VHDL models are typically included in the same library.

When the package file is compiled, the package is created and stored in the working directory.

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VHDL: Packages

Package DeclarationLIBRARY ieee ;USE ieee.std_logic_1164.all ;

PACKAGE <package name> IS<package declarations> ;

END <package name> ;

Package InstantiationLIBRARY work ;USE work.<package name>.all ;

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Adder Circuits in VHDL

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The Half Adder in VHDL

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The Half Adder in VHDL

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The Full Adder in VHDL

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The Full Adder in VHDL

Construct Full Adder from two Half Adders Use Structural VHDL Realize using hierarchical design

Design half adder Interconnect half adders Include any additional logic

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The Full Adder in VHDL

(Using the structural model)

Half Adder (ha1)

Half Adder (ha2)

A

B

CinSum

Cout

inputports

Entity

outputports

Architecturesignals

s1

c1

c2

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The Full Adder in VHDL

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The Full Adder in VHDL(The Package File)

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

PACKAGE halfadd_package ISCOMPONENT halfadd

PORT ( A, B: IN STD_LOGIC ; Sum, Cout: OUT

STD_LOGIC ) ;END COMPONENT ;

END halfadd_package ;

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The Full Adder in VHDL(The Design File)

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE work.halfadd_package.all ;

ENTITY fulladd ISPORT ( Cin, A, B : IN STD_LOGIC ; Sum, Cout : OUT STD_LOGIC ) ;

END fulladd ;

ARCHITECTURE Structure OF fulladd IS SIGNAL s1, c1, c2: STD_LOGIC ;BEGIN ha1 : halfadd PORT MAP ( A => A, B => B, Sum => s1, Cout => c1 ) ; ha2 : halfadd PORT MAP ( s1, Cin, Sum, c2 ); Cout <= c1 OR c2 ;END Structure ;

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Questions?