1

ECE 3150 Homework 8 Solutions

Problem 8.1: (Designing a cascade transresistance amplifier)

a) This is a common gate stage followed by a common source stage. b) One can ignore n in the calculation of the FET width:

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2121

W

ACL

WVV

koxnTNGS

n

c) One can again ignore p in the calculation of the FET width:

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2222

W

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WVV

koxpTPGS

p

d) inR would just be the input resistance of the NFET common gate stage (from the lecture handouts)

that is connected to an infinite LR but where the resistance on the drain side is 1ocr :

1 111

1on oc oc

inmn on mn on

r r rR

g r g r

e) outR would just be the output resistance of the PFET common source stage (from the lecture

handouts) that has a very large resistance on the drain side (because of the ideal current source 3BIASI ):

3||out op oc opR r r r

f) The problem can be solved in two steps; first we find siv1 and then we find 1vvout . Since the input resistance of stage 2 (i.e. the PFET common source stage) is infinite, there will be no inter-stage voltage division and one can write,

2

1

1

v

v

i

vR out

sm

In the small signal model, the current si divides into the input resistance of the common gate stage:

1 111

1on oc oc

inmn on mn on

r r rR

g r g r

and the resistance of the current source 1BIASI sitting at the bottom. Therefore,

1

1

ocin s s

in oc

ri i i

R r

The last equality follows from the fact that 1in ocR r . Therefore, 1 1s ocv i r .

For the second common source stage,

31

||outmp op oc mp op

vg r r g r

v

Therefore,

11

1

outm mp op oc

s

vvR g r r

i v

g)

Assuming the current source 4BIASI is nearly ideal, the output resistance of the amplifier will be the output resistance of the common drain stage and equals:

mnon

onmn

ocoutg

r

rg

rR

111

4

I choose k 1outR then mS 1mng . I choose 4BIASI to equal 200 A. Other values will work too. Since,

3

m200

50

2

3

3

WL

W

Ikg Dnmn

I choose, 1.4 VOUTV ,

2 233 3 1.4 0.7 200

2 23 2.5 V

nGS TN n ox

WkV V C V A

LV

M2 will be safely operating in the saturation region (to keep M2 in saturation, V3 needs to be less than 4 V). The voltage gain of the last stage is approximately unity, so all specs are met. Problem 8.2: (A Differential Amplifier)

The amplifier is DC biased such that VI1 = VI2. M3 and M4 are matched. M1 and M2 are matched. And M5 and M6 are matched. a) M6 and M5 provide the current biasing needed to bias the amplifier. b) and c) The small signal model of the amplifier will resemble the one in the lecture handouts (except that PFETs will replace NFETs and vice versa and M6 will replace the current biasing source). So the answers can be pretty much copied from the lecture handouts. Assuming, 221 idii vvv Then,

||odvd mp on op

id

vA g r r

v

And,

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mpop

co mnvc

ic mn opop op mp mbp op opmn

gr

v gA

v g rr r g g r rg

4

d) It is easiest to calculate the work done by the voltage sources. This equals 4 IBIAS VDD, which is 5 mW.

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