ece 15b computer organization spring 2010 dmitri strukov lecture 9 and 10: wrap-up of hardware...
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ECE 15B Computer OrganizationSpring 2010
Dmitri Strukov
Lecture 9 and 10: Wrap-up of hardware
Partially adapted from Computer Organization and Design, 4th edition, Patterson and Hennessy,
ECE 15B Spring 2010
Agenda
Wrap-up of HW part (except for floating point)• Instruction formats• Addressing modes
Advanced topics
ECE 15B Spring 2010
Instruction formats
op rs rt rd shamt funct
6 bits 6 bits5 bits 5 bits 5 bits 5 bits
R-format:
op rs rt constant or address6 bits 5 bits 5 bits 16 bits
op address6 bits 26 bits
I-format:
J-format:
ECE 15B Spring 2010
Instruction formats
Why stick to fixed formats?
rigid and just few formats + fixed instruction size simple decoding faster clock cycle ( hopefully faster execution)
note that it is always a tradeoff: too rigid and simple instruction set could be result in the large number of instructions
several visual example later…
R-format Example
add $t0, $s1, $s2
special $s1 $s2 $t0 0 add
0 17 18 8 0 32
000000 10001 10010 01000 00000 100000
000000100011001001000000001000002 = 0232402016
op rs rt rd shamt funct6 bits 6 bits5 bits 5 bits 5 bits 5 bits
note the order!(green card)
ECE 15B Spring 2010
ECE 15B Spring 2010
Basic addressing modes
Very important aspect of ISA identifying how operands are defined for each operation
Typically one (or two) operands is (are) register(s), i.e. general purpose one or PC, while another one is either
• Immediate • Register• Memory (may use imm but the actual operand is
memory)
This how you define basic immediate, register or memory classes of addressing modes
ECE 15B Spring 2010
Basic addressing modes
To figure out which mode is used use operation column on the green card, e.g.
R[rd] = R[rs] + R[rt] Reg R[rt] = R[rs] + SignExtImm Imm R[rt] = M[R[rs] + SignExtImm] Mem PC = JumpAddr Imm? PC = R[rs] Reg?
Some of the addressing modes might have specific names (but still map onto the three basic addressing modes)
Many other (specific) addressing modes in various ISAs
MIPS PC-relative or branch addressing
• Branch instructions specify– Opcode, two registers, target address
• Most branch targets are near branch– Forward or backward
op rs rt constant or address6 bits 5 bits 5 bits 16 bits
PC-relative addressing Target address = PC + offset × 4 PC already incremented by 4 by this time
ECE 15B Spring 2010
Pseudodirect or Jump Addressing• Jump (j and jal) targets could be anywhere
in text segment– Encode full address in instruction
op address6 bits 26 bits
(Pseudo)Direct jump addressing Target address = PC31…28 : (address × 4)
ECE 15B Spring 2010
Target Addressing Example• Loop code from earlier example
– Assume Loop at location 80000
Loop: sll $t1, $s3, 2 80000 0 0 19 9 4 0
add $t1, $t1, $s6 80004 0 9 22 9 0 32
lw $t0, 0($t1) 80008 35 9 8 0
bne $t0, $s5, Exit 80012 5 8 21 2
addi $s3, $s3, 1 80016 8 19 19 1
j Loop 80020 2 20000
Exit: … 80024
ECE 15B Spring 2010
ECE 15B Spring 2010
Note on the PC incrementing
• Technical term for auto-incrementat of PC is “delayed branch”
• By default in SPIM “delayed branch” is not checked. To see you SPIM settings look at simulator settings
• You can also check it by loading code to SPIM to check
main : bne $s0, $s0, main
Branching Far Away
• If branch target is too far to encode with 16-bit offset, assembler rewrites the code
• Examplebeq $s0,$s1, L1
↓bne $s0,$s1, L2j L1
L2: …
ECE 15B Spring 2010
ECE 15B Spring 2010
Various specific addressing modes in other ISAs
• Absolute address• Immediate data• Inherent address• Register direct• Register indirect• Base register• Register indirect with index register• Register indirect with index register and displacement• Register indirect with index register scaled• Absolute address with index register• Memory indirect• Program counter relative
Example: Basic x86 Addressing Modes
• Two operands per instructionSource/dest operand Second source operand
Register Register
Register Immediate
Register Memory
Memory Register
Memory Immediate
Memory addressing modes Address in register Address = Rbase + displacement Address = Rbase + 2scale × Rindex (scale = 0, 1, 2, or 3) Address = Rbase + 2scale × Rindex + displacement
ECE 15B Spring 2010
Simple datapath picture
Let’s add more details on this figure to see why instruction decoding could be simple and to see what is happening with for different instructions ECE 15B Spring 2010
Implementing Jumps
• Jump uses word address• Update PC with concatenation of
– Top 4 bits of old PC– 26-bit jump address– 00
• Need an extra control signal decoded from opcode
2 address
31:26 25:0
Jump
ECE 15B Spring 2010
I/O Data Transfer
• Polling and interrupt-driven I/O– CPU transfers data between memory and I/O data
registers– Time consuming for high-speed devices
• Direct memory access (DMA)– OS provides starting address in memory– I/O controller transfers to/from memory
autonomously– Controller interrupts on completion or error
ECE 15B Spring 2010
Interrupts
• When a device is ready or error occurs– Controller interrupts CPU
• Interrupt is like an exception– But not synchronized to instruction execution– Can invoke handler between instructions– Cause information often identifies the interrupting
device• Priority interrupts
– Devices needing more urgent attention get higher priority
– Can interrupt handler for a lower priority interruptECE 15B Spring 2010
Polling
• Periodically check I/O status register– If device ready, do operation– If error, take action
• Common in small or low-performance real-time embedded systems– Predictable timing– Low hardware cost
• In other systems, wastes CPU time
ECE 15B Spring 2010
I/O Register Mapping
• Memory mapped I/O– Registers are addressed in same space as memory– Address decoder distinguishes between them– OS uses address translation mechanism to make them only
accessible to kernel– Memory addresses xffff0000 and above are used for I/O
devices.• I/O instructions
– Separate instructions to access I/O registers– Can only be executed in kernel mode– Example: x86
ECE 15B Spring 2010
Example: Communicating with the Keyboard
• The keyboard has 2 registers associated with it– Receiver control at address xffff0000– Receiver data at address xffff0004
• The rightmost bit of control register is 1 when there is a value ready to be read, 0 otherwise
• The receiver data register will have the character pressed on the keyboard (only when the receiver control register has a 1 in the rightmost bit)
ECE 15B Spring 2010
Polling Example
• Check control bit in the loop and read value if last bit is 1
li $t0, 0xffff0000 #address of control addr
again: lw $t1,0($t0) #get control valueandi $t1, $t1, 1 #get rightmost bitbeqz $t1, again #if not ready check
againlw $t1, 4($t0) #get char. from data
ECE 15B Spring 2010
Notes for working with Memory Mapped I/O in SPIM
• When using memory mapped I/O in SPIM, you must check the Mapped I/O box in the options.
• Must make sure you empty the data register before key is pressed again.
• Accessing the data register resets the status register.
ECE 15B Spring 2010
ECE 15B Spring 2010
Advanced topics: Cache design basics
• You will learn more in detail about cache in computer architecture class
• We cover basics here to address the question– Instructions and data are located in the main
memory but datapath (i.e. viewgraphs above) has two separate locations for instructions and data
• WHY?
– Actually this is cache which holds copies (small chunks) of the data from the main memory
Principle of Locality
• Programs access a small proportion of their address space at any time
• Temporal locality– Items accessed recently are likely to be accessed again
soon– e.g., instructions in a loop, induction variables
• Spatial locality– Items near those accessed recently are likely to be
accessed soon– E.g., sequential instruction access, array data
ECE 15B Spring 2010
Taking Advantage of Locality
• Memory hierarchy• Store everything on disk• Copy recently accessed (and nearby) items
from disk to smaller DRAM memory– Main memory
• Copy more recently accessed (and nearby) items from DRAM to smaller SRAM memory– Cache memory attached to CPU
ECE 15B Spring 2010
Direct Mapped Cache• Location determined by address• Direct mapped: only one choice
– (Block address) modulo (#Blocks in cache)
#Blocks is a power of 2
Use low-order address bits
ECE 15B Spring 2010
Tags and Valid Bits
• How do we know which particular block is stored in a cache location?– Store block address as well as the data– Actually, only need the high-order bits– Called the tag
• What if there is no data in a location?– Valid bit: 1 = present, 0 = not present– Initially 0
ECE 15B Spring 2010
Pipelining Analogy• Pipelined laundry: overlapping execution
– Parallelism improves performance
Four loads: Speedup
= 8/3.5 = 2.3 Non-stop:
Speedup= 2n/0.5n + 1.5 ≈ 4= number of stages
ECE 15B Spring 2010
Pipeline registers• Need registers between stages
– To hold information produced in previous cycle
ECE 15B Spring 2010