ece 15b computer organization spring 2010 dmitri strukov lecture 2: overview of computer...
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ECE 15B Computer OrganizationSpring 2010
Dmitri Strukov
Lecture 2: Overview of Computer Organization
Partially adapted from Computer Organization and Design, 4th edition, Patterson and Hennessy, and classes taught by Patterson at Berkeley, Ryan Kastner at UCSB and Mary Jane Irwin at Penn State
ECE 15B Spring 2010
“Von-Neumann” Computer
Processor
Computer
Control
Datapath
Memory
(where programs, data live whenrunning)
Devices
Input
Output
Keyboard, Mouse
Display, Printer
Disk (where programs, data live whennot running)
Store –programmed concept was not invented by John von Neumann only
Other inventors Presper Eckert and John Mauchly ENIAC 1943University of Pensilvania
ECE 15B Spring 2010
Need Many Layers to Handle Complexity
I/O systemProcessor
CompilerOperatingSystem(Mac OSX)
Application (ex: browser)
Digital DesignCircuit Design
Instruction Set Architecture
Datapath & Control
transistors
MemoryHardware
Software Assembler
Layers of AbstractionThis class is about this region
Below the Program
lw $t0, 0($2)lw $t1, 4($2)sw $t1, 0($2)sw $t0, 4($2)
High Level Language Program (e.g., C)
Assembly Language Program (e.g.,MIPS)
Machine Language Program (MIPS)
Hardware Architecture Description (e.g., block diagrams)
Compiler
Assembler
Machine Interpretation
temp = v[k];v[k] = v[k+1];v[k+1] = temp;
0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111
Logic Circuit Description(Circuit Schematic Diagrams)
Architecture Implementation
Review: Unsigned Binary Representation
Hex Binary Decimal0x00000000 0…0000 0
0x00000001 0…0001 1
0x00000002 0…0010 2
0x00000003 0…0011 3
0x00000004 0…0100 4
0x00000005 0…0101 5
0x00000006 0…0110 6
0x00000007 0…0111 7
0x00000008 0…1000 8
0x00000009 0…1001 9
…
0xFFFFFFFC 1…1100
0xFFFFFFFD 1…1101
0xFFFFFFFE 1…1110
0xFFFFFFFF 1…1111 232 - 1232 - 2
232 - 3232 - 4
232 - 1
1 1 1 . . . 1 1 1 1 bit
31 30 29 . . . 3 2 1 0 bit position
231 230 229 . . . 23 22 21 20 bit weight
1 0 0 0 . . . 0 0 0 0 - 1
ECE 15B Spring 2010
ECE 15B Spring 2010
Data input: Analog Digital
• Real world is analog!• To import analog
information, we must do two things– Sample
• E.g., for a CD, every 44,100ths of a second, we ask a music signal how loud it is.
– Quantize• For every one of these
samples, we figure out where, on a 16-bit (65,536 tic-mark) “yardstick”, it lies.
www.joshuadysart.com/journal/archives/digital_sampling.gif
ECE 15B Spring 2010
Logic Design Basics
• Information encoded in binary– Low voltage = 0, High voltage = 1– One wire per bit– Multi-bit data encoded on multi-wire buses
ECE 15B Spring 2010
Grouping of signals
Why binary?
Other logic styles allow for implementations of multilevel logic (e.g. threshold logic)
CMOS digital design style, which is the most power efficient and therefore currently dominating, enforces binary signal representation
ECE 15B Spring 2010
The lowest layer of hierarchy
ECE 15B Spring 2010
ECE 15B Spring 2010
How to build combinational elements?
• AND-gate– Y = A & B
AB
Y
I0I1
YMux
S
Multiplexer Y = S ? I1 : I0
A
B
Y+
A
B
YALU
F
Adder Y = A + B
Arithmetic/Logic Unit Y = F(A, B)
Gate level design: NAND
N instances of 1-bit wide multiplexor
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1-bit-wide multiplexor
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Implementation of 1-bit-wide multiplexor
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4-to-1 multiplexor
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Hierarchical construction of MUXes
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Building adder
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Building adder
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Building adder
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Ripple carry adder
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Circuit delay
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Simple ALU
ECE 15B Spring 2010
ECE 15B Spring 2010
Combinational logic
• Complex logic blocks are built from basic AND, OR, NOT building blocks we will see shortly
• A combinational logic block is one in which the output us a function only of its current input
• Combination logic cannot have memory
Sequential logic = Flip Flops + combination logic
ECE 15B Spring 2010
How to implement?
ECE 15B Spring 2010
ECE 15B Spring 2010
Will that work?
ECE 15B Spring 2010
Sequential Elements• Flip flop: stores data in a circuit– Uses a clock signal to determine when to update
the stored value– Edge-triggered: update when Clk changes from 0
to 1
D
Clk
QClk
D
Q
ECE 15B Spring 2010
Sequential Elements
• Flip flop with write control– Only updates on clock edge when write control
input is 1– Used when stored value is required later
D
Clk
Q
Write
Write
D
Q
Clk
ECE 15B Spring 2010
Register
ECE 15B Spring 2010
D flip flop gate design
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Second try for previous example
ECE 15B Spring 2010
• Clock rate (clock cycles per second in MHz or GHz) is inverse of clock cycle time (clock period)
CC = 1 / CR
one clock period
10 nsec clock cycle => 100 MHz clock rate
5 nsec clock cycle => 200 MHz clock rate
2 nsec clock cycle => 500 MHz clock rate
1 nsec (10-9) clock cycle => 1 GHz (109) clock rate
500 psec clock cycle => 2 GHz clock rate
250 psec clock cycle => 4 GHz clock rate
200 psec clock cycle => 5 GHz clock rate
Clock + sequential logic = synchronous design
ECE 15B Spring 2010
Clocking Methodology• Combinational logic transforms data during
clock cycles– Between clock edges– Input from state elements, output to state
element– Longest delay determines clock period
ECE 15B Spring 2010
CPU Overview
ECE 15B Spring 2010
… with muxes Can’t just join wires
together Use multiplexers
… with muxes
ECE 15B Spring 2010