ec25 reference design - dragino.com
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EC25 Reference Design
LTE Module Series
Rev. EC25_Reference_Design_Rev.E
Date: 2017-04-06
www.quectel.com
LTE Module Series EC25 Reference Design
EC25_Reference_Design Confidential / Released 1 / 5
Our aim is to provide customers with timely and comprehensive service. For any
assistance, please contact our company headquarters:
Quectel Wireless Solutions Co., Ltd.
Office 501, Building 13, No.99, Tianzhou Road, Shanghai, China, 200233
Tel: +86 21 5108 6236
Email: [email protected]
Or our local office. For more information, please visit:
http://www.quectel.com/support/salesupport.aspx
For technical support, or to report documentation errors, please visit:
http://www.quectel.com/support/techsupport.aspx
Or email to: [email protected]
GENERAL NOTES
QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION
PROVIDED IS BASED UPON CUSTOMERS’ REQUIREMENTS. QUECTEL MAKES EVERY EFFORT
TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT
MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN, AND DOES NOT ACCEPT
ANY LIABILITY FOR ANY INJURY, LOSS OR DAMAGE OF ANY KIND INCURRED BY USE OF OR
RELIANCE UPON THE INFORMATION. ALL INFORMATION SUPPLIED HEREIN IS SUBJECT TO
CHANGE WITHOUT PRIOR NOTICE.
COPYRIGHT
THE INFORMATION CONTAINED HERE IS PROPRIETARY TECHNICAL INFORMATION OF
QUECTEL CO., LTD. TRANSMITTING, REPRODUCTION, DISSEMINATION AND EDITING OF THIS
DOCUMENT AS WELL AS UTILIZATION OF THE CONTENT ARE FORBIDDEN WITHOUT
PERMISSION. OFFENDERS WILL BE HELD LIABLE FOR PAYMENT OF DAMAGES. ALL RIGHTS
ARE RESERVED IN THE EVENT OF A PATENT GRANT OR REGISTRATION OF A UTILITY MODEL
OR DESIGN.
Copyright © Quectel Wireless Solutions Co., Ltd. 2017. All rights reserved.
Quectel
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LTE Module Series EC25 Reference Design
EC25_Reference_Design Confidential / Released 2 / 5
About the Document
History
Revision Date Author Description
A 2016-04-01 Winter CHEN Initial
B 2016-08-22 Yeoman CHEN
1. Added ADC interface design in Sheet 1
2. Added power supply for codec in Sheet 3
3. Added note for UART Translator (Transistor
Solution) in Sheet 4
4. Changed some DGND to AGND in audio
design in Sheet 5
C 2016-10-14 Eden LIU Added the reference design of SGMII and FC20
module
D 2016-11-11 Power JIN
1. Modified the connection of network name
PCM_IN_BT and PCM_OUT_BT in Sheet 1
2. Added note 7 in Sheet 7
3. Added note 6 in Sheet 9
E 2017-04-06 Eden LIU
1. Newly opened pins 37~40 for BT UART, and
removed the multiplexing between Main
UART and BT UART in Sheet 1
2. Newly opened the SD card interface
3. Added the power supply control pin of SD
card interface in Sheet 2
4. Modified network name TXD_MCU as RXD,
RXD_MCU as TXD, CTS_MCU as CTS,
RTS_MCU as RTS, RI_MCU as RI,
DCD_MCU as DCD, DTR_MCU as DTR in
Sheet 2 and Sheet 4
5. Modified the power supply circuit for PCM
Codec in Sheet 3
6. R0904 is not mounted because SDIO_CLK in
FC20 is pulled up internally
Quectel
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LTE Module Series EC25 Reference Design
EC25_Reference_Design Confidential / Released 3 / 5
7. Modified network name PCM_IN_BT as
PCM_OUT_BT, PCM_OUT_BT as
PCM_IN_BT in Sheet 1 and Sheet 9
8. Modified the unidirectional off-page
connectors of SDIO_CMD, SDIO_D0,
SDIO_D1, SDIO_D2 and SDIO_D3 to
bidirectional ones in Sheet 1 and Sheet 9
9. Removed resistors R912, R913 and added
resistor R0920 in Sheet 9
10. Added the reference design for SD card
interface in Sheet 10
11. Modified the drive circuit of indicator STATUS
in Sheet 11
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LTE Module Series EC25 Reference Design
EC25_Reference_Design Confidential / Released 4 / 5
Contents
About the Document ................................................................................................................................ 2
Contents .................................................................................................................................................... 4
1 Reference Design .............................................................................................................................. 5
1.1. Introduction ............................................................................................................................. 5
1.2. Schematics ............................................................................................................................. 5
Quectel
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LTE Module Series EC25 Reference Design
EC25_Reference_Design Confidential / Released 5 / 5
1 Reference Design
1.1. Introduction
This document provides the reference design for Quectel EC25 module.
1.2. Schematics
The schematics illustrated in the following pages are provided for your reference only.
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Module Interface
Note 1
Note 2
Note 3
Note 5
Note 4
Reference Design
7. Keep all RESERVED and unused pins unconnected, and all GND pins are connected to the ground network.
Notes:
5. C0101/C0102 must be close to the SGMII interface of the module.
1. It is recommended to reserve the test points for upgrading the firmware over USB interface and minimize the stub length of USB test signals.
4. ADC pin can not be directly connected to the power supply and must not exceed the voltage range.
2. Do not pull up WAKEUP_IN_MODULE unless the module starts up sucessfully.3. Do not pull up NET_MODE unless the module starts up sucessfully.
9. PCM_***_BT network is used for the communication with FC20 module and CODEC_PCM_*** network is used for the communication with CODEC. FC20 and CODEC cannot be connected to the same PCM interface at the same time.
8. Pins 73～84 are unused in the design, and can be ignored in schematic, PCB decal and the keepout area of pins 73～84.
6. COEX_UART_TX, COEX_UART_RX and WLAN_EN must be at low level before the module starts up successfully.
R0112 0R
R0110 0RR0111 NM_0R
R0109 NM_0R
R0113 100K
R0114 100K
R0116100K
R01
1510
0K
C0101 100nFC0102 100nF
R0117 NM_0RR0118 0R
R0119 NM_0RR0120 0R
R0121 NM_0RR0122 0R
R0123 NM_0RR0124 0R
1 WAKEUP_IN2 AP_READY3 RESERVED4 W_DISABLE#5 NET_MODE6 NET_STATUS7 VDD_EXT
8 GND9 GND
10 USIM_GND11 DBG_RXD12 DBG_TXD13 USIM_PRESENCE14 USIM_VDD15 USIM_DATA16 USIM_CLK17 USIM_RST18 RESERVED
19G
ND
20R
ESET
_N
21PW
RKE
Y
22G
ND
23SD
2_IN
S_D
ET
24PC
M_I
N
25PC
M_O
UT
26PC
M_S
YNC
27PC
M_C
LK
28SD
2_D
ATA3
29SD
2_D
ATA2
30SD
2_D
ATA1
31SD
2_D
ATA0
32SD
2_C
LK
33SD
2_C
MD
34VD
D_S
DIO
35AN
T_D
IV
36G
ND
37BT_RTS
38BT_TXD
39BT_RXD
40BT_CTS
41I2C_SCL
42I2C_SDA
43RESERVED
44ADC1
45ADC0
46GND
47ANT_GNSS
48GND
49ANT_MAIN
50GND
51GND
52GND
53GND
54GND
55R
ESER
VED
56G
ND
57VB
AT_R
F58
VBAT
_RF
59VB
AT_B
B60
VBAT
_BB
61ST
ATU
S62
RI
63D
CD
64C
TS65
RTS
66D
TR67
TXD
68R
XD69
USB
_DP
70U
SB_D
M71
USB
_VBU
S72
GN
D11
5U
SB_B
OO
T11
6R
ESER
VED
113
RES
ERVE
D11
4R
ESER
VED
141 RESERVED142 RESERVED 143RESERVED
144RESERVED
U0101-A
EC25
85 GND86 GND87 GND88 GND89 GND90 GND91 GND92 GND93 GND94 GND95 GND96 GND97 GND98 GND99 GND
100 GND101 GND102 GND103 GND104 GND105 GND106 GND107 GND108 GND109 GND110 GND 111GND
112GND
117RESERVED
118WLAN_SLP_CLK
119EPHY_RST_N
120EPHY_INT_N
121SGMII_MDATA
122SGMII_MCLK
123SGMII_TX_M
124SGMII_TX_P
125SGMII_RX_P
126SGMII_RX_M
127PM_ENABLE
128USIM2_VDD
129SDC1_DATA3
130SDC1_DATA2
131SDC1_DATA1
132SDC1_DATA0
133SDC1_CLK
134SDC1_CMD
135WAKE_ON_WIRELESS
136WLAN_EN
137COEX_UART_RX
138COEX_UART_TX
139BT_EN
140RESERVED
U0101-B
EC25
R0107 0R
R0103 0RR0105 0R
R0101 0R
[4] USIM_GND[11] DBG_RXD[11] DBG_TXD
[4] USIM_VDD
[4] USIM_CLK[4] USIM_RST
[4] USIM_DATA
[2,3,4,7,9,10,11] VDD_EXT
[11] NET_STATUS
[11] NET_MODE
[2] W_DISABLE_MODULE
[2] AP_READY_MODULE
[2] RESET_N[2,11] PWRKEY
[6] A
NT_
DIV
[6]ANT_MAIN
[6]ANT_GNSS
[2,11] USB_VBUS
[2] USB_DM
[2] USB_DP
[4] RXD_MODULE
[4] TXD_MODULE
[4]
DTR
_MO
DU
LE
[4] RTS_MODULE[4] CTS_MODULE
[4]
DC
D_M
OD
ULE [4
]R
I_M
OD
ULE [1
1]ST
ATU
S [1,3
,11]
VBAT
[1,3
,11]
VBAT
[4] USIM_PRESENCE
[5] CODEC_PCM_IN
[5] CODEC_PCM_OUT
[5] CODEC_PCM_SYNC
[5] CODEC_PCM_CLK
[5]I2C_SDA
[11] USB_DM_TEST
[11] USB_DP_TEST
ADC0_INPUTADC1_INPUT
[5]I2C_SCL
[9] BT_EN[9]COEX_UART_TX[9]COEX_UART_RX
[9]WLAN_EN[9]WAKE_ON_WIRELESS
[9]SDIO_CMD[9]SDIO_CLK[9]SDIO_D0[9]SDIO_D1[9]SDIO_D2[9]SDIO_D3
[7]SGMII_RX_M[7]SGMII_RX_P[7]SGMII_TX_P[7]SGMII_TX_M
[7]SGMII_MDIO_CLK[7]SGMII_MDIO_DAT
[7]EPHY_INT_N[7]EPHY_RST_N
[9] PCM_IN_BT
[9] PCM_OUT_BT
[9] PCM_SYNC_BT
[9] PCM_CLK_BT
[11] USB_BOOT
[7]USIM2_VDD
[2] WAKEUP_IN_MODULE
[3]PM_ENABLE
[9]WLAN_SLP_CLK
[9]CTS_BT[9]RXD_BT[9]TXD_BT[9]RTS_BT
[10] SD2_INS_DET
[10]
SD2_
DAT
A3[1
0]SD
2_D
ATA2
[10]
SD2_
DAT
A1[1
0]SD
2_D
ATA0
[10]
SD2_
CLK
[10]
SD2_
CM
D[1
0]VD
D_S
DIO
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MCU Interface
Reference Design
Notes:1. U0201 represents customer's MCU.2. EC25 can only work as a USB device and supports Full Speed and High Speed modes. To communicate with USB interface,
MCU needs to support USB host or OTG function. The VBUS pins of MCU and EC25 should be powered bya 5V power system for USB detection, and VBUS-CTRL is used to turn on/off VBUS power supply.
3. AP_READY can be configured to high level detection and low level detection. For more details about AP_READY,please refer to
4. Transistor circuits (Q0201~Q0205) are used for level translation.Quectel_EC25&EC21_AT_Commands_Manual.Quectel_EC25_Hardware_Design and
When VBUS_CTRL is at high level, USB_VBUS will be powered on.
It is used to turn on or off the module. It is used to reset the module.
5V power source from main board.
Keep WAKEUP_IN_MODULE at low levelbefore module starts up successfully.
VBUS_CTRL = High level, USB_VBUS is powered on.
AP_READY_MODULE low level detection.
VDDGNDTXDRXDCTSRTS
USB_VBUSUSB_D+USB_D-
GPIO_01GPIO_02GPIO_03
USB_ID
GPIO_04GPIO_05GPIO_06GPIO_07GPIO_08GPIO_09GPIO_10GPIO_11GPIO_12GPIO_13
RIDCDDTR
U0201
G
S D
Q0206
SI2333CDS-T1
Q0207
DTC043ZE
R0204
10K
Q0202
DTC043ZE
Q0201
DTC043ZE
Q0205
2SC4617TLQ
R0201
4.7K
R02024.7K
Q0203
DTC043ZE
C0201
470nF
R0203100K
Q0204
DTC043ZE
VDD_MCU
[4]TXD[4]RXD
[1]USB_DP[1]USB_DM
[1,2,11]USB_VBUS
[2]ON/OFF_MCU[2]RESET_MCU
[2]VBUS_CTRL
[2]W_DISABLE_M[2]SLEEP_STATUS
[4]CTS[4]RTS
[3]VBAT_EN
[4]RI[4]DCD[4]DTR
[3]CODEC_POWER_EN[2]WAKEUP_IN_MCU
[10]SD_PWR_EN
[3,11] DC_5V [1,2,11]USB_VBUS
[2] VBUS_CTRL
[1]RESET_N
[2] RESET_MCU
[1,11]PWRKEY
[2] ON/OFF_MCU
[1] AP_READY_MODULE [2]SLEEP_STATUS
VDD_EXT VDD_EXT
[1]W_DISABLE_MODULE
[2] W_DISABLE_M
[2] WAKEUP_IN_MCU
[1]WAKEUP_IN_MODULE
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EC25
TITLE
Reference Design
VDD_1V8 = (R0310/R0312+1)*1.207 = 1.8V
Power Supply Design
DC-DC ApplicationIt is used when the input voltage is above 7V. Use a DC-DC converter to convert a high input voltage
e.g. DC12V INDC-DC
DC 5V OUTLDO DC 3.8V 2.0A
LDO DC 1.8V
LDO DC 3.3V
VBAT = (R301/R306+1)*1.24 = 3.88V
Recommended load current is greater than 10mA.
Codec
Power Supply for FC20, SGMII and SD Card
VDD3V3 = (R0314/R0317+1)*1.24 = 3.3V
LDO FC20DC 3.3V 3.0A
SGMII
EC25
into 5V output, and then the LDOs will generate 3.8V, 3.3V and 1.8V typical voltages.
LDO Application
It is used when the input voltage is below 7V.
Note:
1. Recommended load current of MIC29302WU is greater than 10mA.Notes:
Close to the module VBAT pins.Notes:
2. VBAT should be routed in star mode to VBAT_BB and VBAT_RF pins.
VBAT DesignConnect to VBAT_BB pins.
Connect to VBAT_RF pins.
1. The power supply must be able to provide sufficient current up to 2A or more.
3. The recommended operating voltage of VBAT is 3.3V~4.3V.
Power Supply for PCM Codec
Note 2
2. RC circuit, which is assembled with R0318 and C0327, is used to delay the start-up of MOSFET switch circuit.
Note 1
SD Card
2. To ensure that ALC5616 works normally, please follow the power ON and OFF sequences of its power supply.
Notes:
Power ON Sequence: power on VDD_1V8 first, then VDD_3V3.Power OFF Sequence: power off VDD_3V3 first, then VDD_1V8.
VDD_3.3V = (R0305/R0308+1)*1.207 = 3.3V
1. CODEC_POWER_EN must be at low level in order to ensure the normal output voltage of VDD_3.3V.If VDD_3.3V power supply needs to be switched off, please keep CODEC_POWER_EN at high level.
1 IN
3 EN
5OUT
4BP
2G
ND
U0303
SGM2019-ADJYN5G/TR
C0320
4.7uF
R0310
39K±1%
R0312
75K±1%
C0318
100nF
C0321
100nF
C0322
33pF
C0319
1uF
R0311100K
R0309
0R
+ C0323
470uF
1EN
2 IN
3G
ND
4OUT
5AD
J
U0304
MIC29302WU
C0324
100nFC0326
100nF
+ C0325
470uF
R0314
75K±
1%
R0317
47K±
1%
R031351K
R0315330R
R031610K
G
S D
Q0302
SI2333
C0327
100nFR0318
100K
Q03
03
+ C0311
470uF
1EN
2 IN
3G
ND
4OUT
5AD
J
U0301 MIC29302WU
C0312
100nFC0310
100nF
+ C0309
470uF
R0301
100K
±1%
R0306
47K±
1%
R0302330R
D0302
TVS
Q0301
R0303
51K
+
C0301
100uF
D0301
PZ3D4V2H
C0302
100nF
C0303
33pF
C0304
10pF
C0306
100nF
C0307
33pF
C0308
10pF
+
C0305
100uF
C0315
4.7uF
R030573.2K±1%
R030842.2K±1%
C0316
100nF
C0313
1uF
C0314
100nF
1 IN
3 EN
5OUT
4BP
2G
ND
U0302
SGM2019-ADJYN5G/TR
C0317
33pFR0304
10K
Q0304
DTC043ZE
VDD_1V8[3,8,10] VDD3V3
[1,2,4,7,9,10,11] VDD_EXT
[2,3,11] DC_5V
VDD3V3
[1] PM_ENABLE
[9]VDD3V3_FC20
[2,3,11] DC_5V VBAT
[2] VBAT_EN
[1,3,11]VBAT
[1,3,11]VBAT
VBAT
VDD_3.3V[2,3,11] DC_5V
[2] CODEC_POWER_EN
[3,5
]VD
D_1
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EC25 Reference Design
3. R0401~R0403 are applied to suppress the EMI spurious transmission and enhance the ESD protection.
5. R0404 can improve anti-jamming capability of the (U)SIM circuit and it should be placed close to the (U)SIM card connector.
(U)SIM and UART Designs
UART Translation - IC Solution (Recommended)
UART Translation - Transistor Solution
2. The supply voltage range of VCCA should not exceed the one of VCCB.
3. If high baud rate needs to be enabled, it is highly recommended to install four 1nF capacitors (C0407/C0408/C0409/C0410) on transistor circuit.
4. The DTR transistor circuit is similar to the one of RTS interface.
4. It is recommended to take electrostatic discharge (ESD) protection measures near the (U)SIM card connector.The TVS diode with junction capacitance less than 50 pF must be placed as close as possible to the (U)SIM card connector.
(U)SIM Card Interface
2. EC25 module provides an input pin (USIM_PRESENCE) to detect whether the (U)SIM card exists or not. It supports both low level and high level detections. For more details, please refer to
1. The decouple capacitor of USIM_VDD should be less than 1uF and must be near to (U)SIM card connector.Notes:
Notes:1. It is recommended to use an IC conversion chip for UART translation.
The transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps.
Quectel_EC25_Hardware_Design.
For more information about TXS0108E, please refer to its datasheet from TI.
The RI and DCD transistor circuits are similar to the ones of CTS interface.
C0401 100nF
1
2
3 4 5 6
U0401 ESDA6V8AV6
C0403
33pF
C0404
33pF
C0402
33pF
R0401 22R
R0402 22R
R0403 22R
R040415K
C0405100nF
R0406 120K
R0405 10K
C0406 100nF
Q0401
2SC4617TLQ
Q0402
2SC4617TLQ
R04084.7K
R04074.7K
C04071nF
R04094.7K
R04104.7K
C0408
1nF
Q0403
2SC4617TLQ
R04124.7K
R04114.7K
Q0404
2SC4617TLQ
R04134.7K
R04144.7K
6 A5
7 A6
8 A7
9 A8
10 OE
5 A4
4 A3
19VCCB
20B1
18B2
14B6
13B7
12B8
11GND
3 A2
2 VCCA
1 A1
17B3
16B4
15B5
U0402
TXS0108E
GND
VPP
I/OCLK
RST
VCC
PRESENCE
J0401
(U)SIM card connector
R041551K
C0409
1nFC0410
1nF
USIM_VDD
[1] USIM_RST
[1] USIM_CLK
[1] USIM_DATA
USIM_VDD
[1]USIM_GND
VDD_EXT
VDD_EXT VDD_MCU
[1,4] TXD_MODULE
[1,4] RXD_MODULE
[1] RI_MODULE
[1] DTR_MODULE
[2,4]TXD
[2,4]RXD
[2]DTR
[2]RI
[2,4] RXD [1,4]RXD_MODULE
VDD_EXTVDD_EXT
[2,4] TXD [1,4]TXD_MODULE
VDD_EXTVDD_MCU
VDD_EXT
[1,4]RTS_MODULE[2,4] RTS
VDD_EXTVDD_MCU
[2,4] CTS [1,4]CTS_MODULE
VDD_EXT
[2,4]CTS
[2,4]RTS
[1,4] CTS_MODULE
[1,4] RTS_MODULE
[1] DCD_MODULE [2]DCD
VDD_EXT
[1] USIM_PRESENCE
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TITLEReference Design
CTIA OMTPR0519/R0521R0518/R0520 M
MNMNM
Audio Design
Audio - Earphone Application Audio - Handset Application
To ensure that ALC5616 works normally, please follow the power ON and OFF sequences of its power supply.Note:
For more details, please refer to ALC5616 datasheet.
Close to earphone interface.
1. The analog output only drives earphone and headset. For larger power loads such as speakers, the design needs to incease the audio power amplifier.
2. The maximum capacitive loading for SPK is 330 pF and the maximum capacitive loading for MIC is 250 pF.
Notes:
Power ON Sequence: power on DBVDD/AVDD/DACREF/CPVDD first, then MICVDD.Power OFF Sequence: power off MICVDD first, then DBVDD/AVDD/DACREF/CPVDD.
4132
J0502
D0504
ESD9X5.0ST5G
D0505C0537
33pF
C0539
33pF
C0540
10pF
C0538
10pF
C0541
33pF
C0536
10pF
C0544
10pF
C0545
33pF
C0546
10pF
C0547
33pFC054333pF
C054210pF
C0527
10pF
C0528
33pF
C0529
4.7uF
F0501 0R
F0502 0R
F0504 0RF0503 0R
D0506
PESD5V0S1BL
D0507
2 IN1P/DMC_DAT
3 IN2P4 IN2N/JD2
5D
ACR
EF6
AVD
D7
AGN
D10LOUTR/N
11CPN2
12CPP2
13CPN1
14CPP1
15C
PVD
D16CPVPP
18CPVREF
19CPVEE
20HPO_L
21 ADCDAT1
22 DACDAT1
23 LRCK1
26SCL
27SDA
28 GPIO1/IRQ1
29D
BVD
D
30D
CVD
D
31M
ICVD
D
32 MICBIAS1
8VREF2
24 BCLK1
1 JD1
9LOUTL/P
17HPO_R
25 MCLK
33D
GN
D
U0501
ALC5616
C0505
4.7uF
C0504
4.7uF
C0503
100nF
R0501 0R
C0501
4.7uF
C0502
100nF
C05
092.
2uF
C05
1010
0nF
C0506
4.7uF
C0507
100nF
C05
082.
2uF
C0515 2.2uF
C0516 2.2uF
C0511 4.7uF R0503
0R
R0508
NM_10K
R05
104.
7K
R05
094.
7K
C0523 4.7uF
C0521 2.2uFC0522 2.2uF
R0517 0R
R-0805R0504 0R
R0505 0R
R0506 0R
R0507 0R
C0512
NM
C0513
NM
C0514
NM
C0524 2.2uF
C0525 2.2uF
R05161K
R05141.5K
R0513
1K
R0515
1.5K
C0526
10uF
R0502 0R
1
2
3
45
J0501
C0517 1uFC0518 1uF
C0519 1uFC0520 1uF
R0511 0R
R0512 0R
C0530
10pF
C0531
33pF
D0501
ESD9X5.0ST5G
R0519 NM_0R
R0518 0R
R0520 0R
R0521 NM_0R
D0502
PESD5V0S1BL
C0532
10pF
C0533
33pF
D0503
PESD5V0S1BL
C0534
10pF
C0535
33pF
R0522 0R
R0523 0R
C0549
NM_33pF
C0548
NM_33pF
[5] SPK_P
[5] MIC_P[5] MIC_N
[5] MIC_N
[5] SPK_N
VDD_3.3V
VDD_1V8
VDD_3.3V
[1]I2C_SDA[1]I2C_SCL
VDD
_1V8
VDD_1V8
[1] CODEC_PCM_OUT[1] CODEC_PCM_IN
[1] CODEC_PCM_CLK[1] CODEC_PCM_SYNC
[5] MIC+[5] MIC-
[5]SPK_P[5]SPK_N
MICBIAS
[5] MIC_P
[5] MIC_N
MICBIAS
[5]MIC+
[5]MIC-
VDD_1V8
[5]SPK_R[5]SPK_L
[5] SPK_R
[5] SPK_L
[5] MIC_P
[5]MIC_P
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A Quectel Wireless SolutionsPROJECT
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VERE
EC25
TITLEReference Design
RF and GNSS Design
Main Antenna Interface Diversity Antenna Interface
GNSS Antenna CircuitFC20 Antenna Circuit
Notes:1. The main antenna circuit, diversity receiving antenna circuit and FC20 antenna circuit are recommended to use PI type circuit, which is convenient for subsequent debugging.2. The diversity reception function is ON by default. If diversity antenna is not used, there is a need to use AT command to turn off diversity reception.
5. ESD protection devices should be added to the GNSS antenna interface, and the parasitic capacitance should be less than 0.05pF.
3. An external LDO can be used to supply power for active antenna.4. If antenna circuit is designed with passive antenna, R0603 and L0601 are not needed.
Active Antenna / Passive Antenna
6. The impedance of the RF signal line must be controlled as 50Ω when routing.
C0601
NM
R0601 0R
J0601
C0602
NM
C0603
NM
R0602 0R
J0602
C0604
NM
L0601
47nH
C0605
0.1uF
R060310R
C0608
100pF
J0604
C0609
NM
C0610
NM
C0606
NM
R0604 0R
J0603
C0607
NM
[1]ANT_MAIN[1]ANT_DIV
[1]ANT_GNSS
VDD
[9]FC20_ANT
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EC25
A2
L0701, C0709 and C0710 are close to Pin 3.
Selected when external
75R @100MHz, DCR=0.1R
Add one 0.1uF capacitor
MODE 2
MODE 1
MODE 0
MODE 3
PHY_
AD2
PHY_AD1PHY_AD0
AV
DD
_1V
1
Close to AR8033.
SGMII Design (Part 1)
Note 2
Note 3Note 4
Note 5
beside the module.
Note 1
Note 6
interupt is required.
the clock and MDI interface traces), and the trace width needs to be at least 25 mils.
Notes:
3. R0715 must be close to AR8033. The traces of the resistor must be away from other traces (especially
4. The two capacitors should be selected according to the actual load capacitance of crystal andthe board-level test results, at full load application temperature and voltage range.
5. The differential trace impedance of SGMII must be limited to 100Ω.
2. To minimize crosstalk, the reset trace must be at least 20 mils away from other signal traces.1. SGMII_MDIO_DAT should be connected to the USIM2_VDD beside the module with a 1.5K pull-up resistor.
6. EMI filter is reserved. If LED pins are not used, keep C0714, C0719, C0721=470pF.7. The space between SGMII differential pair (RX and TX traces) should be 3 times of the trace width at least.
Also, SGMII should keep a distance of 3 times of its trace width from other signal lines.
1 MDC2 RSTN3 LX4 VDD335 INT6 XTLO7 XTLI8 AVDDL9 RBIAS
10 VDDH_REG11 TRXP012 TRXN0
13AV
DD
L14
TRXP
115
TRXN
116
AVD
D33
17TR
XP2
18TR
XN2
19AV
DD
L20
TRXP
321
TRXN
322
NC
23LE
D_A
CT
24LE
D_1
000
25CLK_25M
26LED_10_100
27RXD3
28RXD2
29VDDIO_REG
30RXD1
31RXD0
32RX_DV
33RX_CLK
34TX_EN
35GTX_CLK
36TXD0
37TX
D1
38TX
D2
39TX
D3
40W
OL_
INT
41SD
42SO
N43
SOP
44AV
DD
L45
SIN
46SI
P47
DVD
DL
48M
DIO
49G
ND
U0701
AR8033-AL1B-R
R0703 NM_100K C0706 NM_1uF
R07
15
2.37
K 1%
R0706 10K
R704 NM_10K
C0718
0.1uF
C0722 0.1uF
C07
200.
1uF
C0701 2.2uF
C0707
10uF
C0723
1uF
C0724
0.1uF
FB0702
BLM15AX700SN1D
C0717
1uF
C0712
0.1uF
C0711
100pF
1XTAL
2 GND 3XTAL
4 GND
Y0701
25MHz C0715
10pF
C0716
10pF
C0721 NM/470pF
C0719 NM/470pF
C0713
NM
C0714
NM/470pF D0701GREEN
R0714 510R
C0702 0.1uF
C0703 0.1uF
C0705 0.1uF
R0705 0R
R0711 0R
C0708
0.1uF
FB0701
BLM15AX700SN1D
R702 NM/10K
L0701 4.7uH
C0709
10uF
C0710
0.1uF
C07040.1uF
R0713 10K
R0707 10K
R0712 10K
R0708 10KR0709 10KR0710 10K
R0716 10K
R0717 10K
R0701 1.5K
[1] EPHY_RST_N
[1] EPHY_INT_N
AVD
D_1
V1
[7,8]VDD33_SGMII
[1]SGMII_TX_M
[1]SGMII_RX_P[1]SGMII_RX_M
[1]SGMII_TX_P
AVD
D33
_PH
Y
[7,8] VDD33_SGMII
[7]VDDH_2V5
[7] VDDH_2V5[8] TRXP0[8] TRXN0
[8]TRXP1
[8]TRXN1
[8]TRXP2
[8]TRXN2
[8]TRXP3[8]TRXN3
[8]LED_ACT
[8]LED_1000
[1] SGMII_MDIO_DAT
[1] SGMII_MDIO_CLK
[7,8] VDD33_SGMII
CLK_25M
[1,2,3,4,9,10,11] VDD_EXT
[7] VDDH_2V5
[7]AVDD_1V1
[7] AVDD_1V1
[7] DVDD_1V1
[7] DVDD_1V1
[7]AVDD_1V1
[7] AVDD_1V1
[7]VDDH_2V5
[1] USIM2_VDD
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Reference DesignEC25
A2
SGMII Design (Part 2)
Description
PHY_AD[2:0] set the lower three bits of the physical address.
The upper two bits of the physical address are set to 00.
Default internal
1
PHY core
PHY_AD2
PHY_AD1
PHY_AD0
MODE 3
MODE 2
MODE 1
MODE 0
EXT_INT_SEL
weak pull-up/downconfiguration signal
0
0
0
0
0
0
0
0
0
0
0
0
1
1 0
weak pull-up/down
Application external
Mode select bit 3
Mode select bit 2
Mode select bit 1
Mode select bit 0
An external 10K pull-down resistor is required.
0=Pull-down, 1=Pull-up.
1. Differential pair P/N skew must be less than 20 mils, and the maximum trace length must be less than10 inches.2. Using the 100Ω±10% differential impedance with 50Ω±10% single-ended impedance for SerDes traces is recommended.3. To minimize crosstalk, the distance between separate adjacent pairs that are on the same layer must be equal to or larger than 40 mils.
Notes:
4. Copper filling around transformers is prohibited for better ESD protection performance. 5. For better EMI suppression performance, do not route in top layer.
R0801 0R
+ C0804100uF
C0802
33pF
C0801
10pF
C0803
100nF
1 TCT12 TD1+3 TD1-4 TCT25 TD2+6 TD2-7 TCT38 TD3+9 TD3-
10 TCT411 TD4+12 TD4- 13MX4-
14MX4+
15MCT4
16MX3-
17MX3+
18MCT3
19MX2-
20MX2+
21MCT2
22MX1-
23MX1+
24MCT1
U0801
FC3004C0806
0.1uF
C0807
0.1uF
C0808
0.1uF
C0809
0.1uF
1 TA+
14H
213
H1
3 TB+
5 TC-
7 TD+
2 TA-
4 TC+
6 TB-
8 TD-
9G-
10G+
11Y-
12Y+
J0801FC601-56-LED
R0802 75R 1%
R0804 75R 1%
R0805 75R 1%
R0807 75R 1%
C08051000pF/2KV_NM
C0810
1000pF/2KV
R0803 510R
R0808 510R
R0806
0R
[7] VDD33_SGMII [3,10]VDD3V3
[7]LED_ACT
[7]LED_1000
[7] TRXP0[7] TRXN0
[7] TRXP1[7] TRXN1
[7] TRXP2[7] TRXN2
[7] TRXP3[7] TRXN3
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A2
1. Keep all RESERVED and unused pins unconnected.Notes:
Reserved for debugging
2. BT function of FC20 is under development.
FC20 Design
R806 must be mounted.
3. SDIO_DATA2 is a signal that affects the boot of the module, and should be kept at high level when the power supply resets.4. The impedance of the SDIO data signal line must be controlled as 50Ω when routing.5. SDIO data lines should be wrapped together by GND lines; SDIO_CMD and SDIO_CLK network lines should be wrapped with GND lines separately.
R09
04N
M_1
0K
C0909
100nF
C0908
33pF
C0907
10pF
+ C0910
100uF
R0902 0R
R090110K
R0912NM_10K
C0902
NM_0.1uF
C0903
10uF
C0904
100nF
C0905
33pF
C0906
10pF
R0919 0R
C0912
NM
R091810K
R0913NM_10K
C0911
NM_0.1uF
R090310K
1 GND
2 RESERVED
3 RESERVED
4 DBG_TXD
5 LTE_UART_TXD
6 LTE_UART_RXD
7 BT_UART_RTS
8 BT_UART_CTS
9 WLAN_EN
10 BT_EN
11 VIO
12 GND 20GND
21VDD_3V3
22SDIO_D3
23SDIO_D2
24SDIO_D1
25SDIO_D0
26SDIO_CLK
27SDIO_CMD
28GND
29GND
30RF_ANT
31GND
13PC
M_I
N
14PC
M_S
YNC
15PC
M_C
LK
16PC
M_O
UT
17BT
_UAR
T_TX
D
18BT
_UAR
T_R
XD
1932
KHZ_
IN32
WAK
E_O
N_W
IREL
ESS
33R
ESER
VED
34R
ESER
VED
35R
ESER
VED
36G
ND
37R
ESER
VED
38G
ND
U0901-A
FC20
39 GND
40 GND
41 RESERVED
42 RESERVED
43G
ND
44G
ND
45G
ND
46RESERVED
47RESERVED
48GND
49GND
50G
ND
51G
ND
52G
ND
U0901-B
FC20
R0917 0R
R0916 0R
R0914 0R
R0911 0R
R0910 0R
R0915 0R
R09
05N
M_1
0K
R09
0610
K
R09
07N
M_1
0K
R09
08N
M_1
0K
R09
09N
M_1
0K
C09
01N
M_1
0nF
[6]FC20_ANT
[1]SDIO_CMD
[1]SDIO_CLK
[1]SDIO_D0
[1]SDIO_D1
[1]SDIO_D2
[1]SDIO_D3
[3]VDD3V3_FC20
[1,2
,3,4
,7,9
,10,
11]
VDD
_EXT
[1,2,3,4,7,9,10,11]VDD_EXT
[1]WAKE_ON_WIRELESS
[11] DBG_TXD_FC20
[1,2
,3,4
,7,9
,10,
11]
VDD
_EXT
[1] WLAN_EN
[1,2,3,4,7,9,10,11] VDD_EXT
[1]WLAN_SLP_CLK[1] PCM_OUT_BT
[1]PCM_SYNC_BT
[1] PCM_CLK_BT
[1] PCM_IN_BT[1]TXD_BT[1]RXD_BT
[1,2,3,4,7,9,10,11] VDD_EXT
[1] BT_EN
[1] CTS_BT
[1] RTS_BT
[1] COEX_UART_RX
[1] COEX_UART_TX[1
,2,3
,4,7
,9,1
0,11
]VD
D_E
XT
[1,2
,3,4
,7,9
,10,
11]
VDD
_EXT
[1,2,3,4,7,9,10,11]VDD_EXT
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VER
1110
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DATE 2017/4/6
Reference DesignEC25
A2
SD Card Interface Design
Notes:
8. Route SD card lines with 50Ω impedance. It is important to route the SDIO signal traces with total grounding.
10. It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1mm and the exterior total trace length should be less than 23mm.
7. Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals, etc, as well as noisy signals such as clock signals, DCDC signals, etc.
1. VDD_SDIO can only be used for SDIO pull-up resistors and its maximum output current is 50mA.
3. To maximally limit the surge current caused by SD card insertion, the bypass capacitor (C1002) of the power supply for SD card interface should not exceed 5uF.4. To avoid the jitter of bus, resistors R1005~R1009 are needed to pull up SDIO to VDD_SDIO. The value of these resistors is among 10~100kohm and the recommended value is 100kohm.5. In order to improve signal quality, it is recommended to add 0Ω resistors R1010~R1015 in series between the module and the SD card connector.
The bypass capacitors C1003~C1008 are reserved with no mounting by default. All resistors and bypass capacitors should be placed close to the module.
9. Make sure the adjacent trace spacing is two times of the trace width and the bus capacitance is less than 40pF.
6. It is recommended to add ESD components near the pins of SD card connector. The parasitic capacitance of ESD components should be smaller than 15pF.
2. The supply voltage range of VDD for SD card interface is 2.7~3.6V and sufficient current up to 0.8A needs to be provided.
11. The pin DETECT of SD card connector must be connected to the module when SD card function is used.
C1002
100nF
R1010 33R
R1011 0R
R1013 0R
R1014 0R
R1015 0R
R1016120K
D1007
ESD9X3.3ST5G
R10171K
CMD
DATA3
DATA2
DATA0
DATA1
VSS
VDD
CLK
DETECT
J1001
SD card connector
C1003
NM
C1004
NM
C1005
NM
C1006
NM
C1007
NM
C1008
NM
R1005100K
R1006100K
R1007100K
R1008100K
R1009100K
R1012 0R
D1001
ESD9L5.0ST5G
D1002 D1003 D1004 D1005 D1006
R100210K
G
S D
Q1001
SI2333
C1001
100nF
R1003100K
Q1002
DTC043ZE
R1001 0R
VDD_EXT
[1]SD2_INS_DET
[2] SD_PWR_EN
[1] SD2_CLK
[1] SD2_CMD
[1] SD2_DATA3
[1] SD2_DATA2
[1] SD2_DATA1
[1] SD2_DATA0
[1] VDD_SDIO
[3,8] VDD3V3
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Indicators and Test Points
Indicators
Reserved Test Points
2. For more details about NET_MODE and NET_STATUS, please refer to
Notes:1. The STATUS is an open drain output pin, and its drive current is less than 1mA.
Notes:1. Both USB and debug UART interfaces are reserved for software debugging.
3. Keep USB test points as close as possible to USB pins.2. USB interface also can be used to upgrade firmware.
Junction capacitance of ESD component on USB data lines might influence the signal,please pay attention to it. Typically, the capacitance should be less than 1pF.
Note:
when USB_BOOT is at high level.
Quectel_EC25_Hardware_Design.
USB_BOOT is kept open by default and the module will be forced into download mode
3. If the current consumption is required as low as possible when the device is in sleep, replace the power supply of indicators with controllable one.Turn off the power when the module enters sleep mode.
4. DBG interfaces support 1.8V power domain.A level translator should be used if the power domain of customers' application is 3.3V.
D1106
SD12
C.T
CT
D1107
SESD
3Z5V
D1105
ESD
9L5.
0ST5
G
D1104
ESD
9L5.
0ST5
G
D1108
ESD
9X3.
3ST5
G
D1109
ESD
9X3.
3ST5
G
Q1102
DTC043ZE
R11032.2K
D1103
Q1101
DTC043ZE
R11022.2K
D1102
D1110
ESD
9X3.
3ST5
G
1 2
J1101
T-PIN-1X2
R1104
10K
3
1
2
Q1103
2SA1037AKT146
R110547K
R11012.2K
D1101
R1106
4.7K
4
5
6
3
2
1
7
8
9
J1102
Connector
[1,3]VBAT
[1,2]PWRKEY
[1]USB_DP_TEST
[1]USB_DM_TEST
[1,2]USB_VBUS
[1]DBG_RXD
[1]DBG_TXD
[1] NET_STATUS
DC_5V
[1] NET_MODE
DC_5V
[1] STATUS
DC_5V
[1,2,3,4,7,9,10] VDD_EXT [1]USB_BOOT
[9]DBG_TXD_FC20
DC_5V
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