ec ii lab manual prince college

8/13/2019 EC II Lab Manual Prince College

1/105

EXPT. NO: 1A

DATE:

AIM:

To design, construct and study the frequency response of current series amplifier with orwithout feedback and to calculate the input and output impedance.

APPARATUS REQUIRED:

S.No Name Value / Range Quantity

1. Transistor BC107 1. !esistors !"#1$%, ! C# &.7$%,

!1,!

1

'. Capacitors 0.1(f(f

1

&. )unction *enerator 0+ 10- 1/. C! '0- 1

. !egulated 2ower

3upply

40+'056 1

7. Bread Board 1

TEOR!:

)eedback is used in the amplifier to improe its performance and to make it moreideal. 8n the process of feedback, a part of output is sampled and fed back to the input of theamplifier. Therefore, at input we hae two signals9 8nput signal and part of the output which isfed back to the input. Both these signals may be in phase or out of phase. :hen input signal andpart of output signal are in phase, the feedback is called positie feedback. n the other hand,when they are in out of phase, the feedback is called negatie feedback.

The positie feedback results in oscillations and hence not used in amplifiers. Therefore,the noise in amplifier can be reduced by using negatie feedback. 8t reduces the gain of theamplifier, but it has the adantages of reduced distortion, increased stability in gain andincreased bandwidth. :hen 5CC is increased, the base oltage 45B6 increases thereby increasingthe base current 48B6. Then the collector current 48C6 also increases which in turn decreases the

collector oltage 45C6. Because of high collector current 48C6, emitter current 48"6 increasesthereby increasing the emitter oltage 45"6. This increase in emitter oltage 45"6 decreases thebase+emitter oltage 45B"6. :hen 5B" goes down then base current 48B6 decreases so thatcollector current 48C6 also decreases.

"IR"UIT DIA#RAM: "URRENT SERIES AMP$I%IER &ITOUT %EED'A"(

"URRENT SERIES %EED'A"( AMP$I%IER


2/105

%ig. 1. &ITOUT %EED'A"(

TA'U$ATION: "URRENT SERIES AMP$I%IER &ITOUT %EED'A"( $eep the input oltage constant, )Vin* +

%,e-ueny

)in *

Out0ut Voltage )Vo*

)in olt2*

#ain+ 34 log)Vo/Vin*

)in 5'*

"IR"UIT DIA#RAM: "URRENT SERIES AMP$I%IER &IT %EED'A"(

FG


3/105

%ig. 3. &IT %EED'A"(

TA'U$ATION: "URRENT SERIES AMP$I%IER &IT %EED'A"(

$eep the input oltage constant, )Vin* +

%,e-ueny

)in *

Out0ut Voltage

)Vo*

)in olt2*


)in 5'*

)or the increased base oltage, the decreased collector oltage 45C6 and the collectorcurrent 48C* are gien as feedback to the input signal. Therefore both the signals are in out ofphase, hence negatie feedback is used. -ere the feedback is gien through the current andhence it is called as current series feedback. The feedback is proided for the current seriesfeedback amplifier by remoing the bypass capacitor C". )or series current feedback amplifier,the input and output resistance increases.

FG


4/105

PRO"EDURE:

1. The circuit is connected as shown in circuit diagram fig 416 without feedback.. The input signal is set using the function generator.

'. Check the output using C! and note the corresponding output oltage.&. The gain is calculated using the formula, *ain 4in dB6 # 0 log 45in ; 5o6./. The circuit fig 46 is connected as shown in circuit diagram with feedback.

4by eliminating C"6.. 3teps , ', & were repeated.7. < graph was drawn between *ain 4in dB6 and frequency 4in -6 for both cases.=. )rom the graph, bandwidth and cut+off frequencies were calculated.

MEASUREMENT O% INPUT AND OUTPUT RESISTAN"E:1. easure ac oltage5acand ac current8acat the input side between base and

ground in fig. 1 without feedback using multimeter.. )rom the 5acand 8acmeasured at the input, calculate the input resistance.'. easure ac oltage5acand ac current8acat the output side between collector

and ground in fig. 1 without feedback using multimeter.&. )rom the 5acand 8acmeasured at the output, calculate the output resistance./. !epeat steps 1 to & for the circuit in fig. with feedback.

MODE$ #RAP:

)>? >ower cut+off frequency without feedback)@? @pper cut+off frequency without feedback)>f? >ower cut+off frequency with feedback)@f ? @pper cut+off frequency with feedbackBandwidth 4without feedback6 # )@+ )>Bandwidth 4with feedback6 # )@f+ )>f


5/105

DESI#N:

5cc # 1 5 8c # 1.m %ee56a? &it>out %ee56a?

In0ut Re2i2tane

Out0ut Re2i2tane

RESU$T:


7/105

Thus the current series feedback amplifier was designed and implemented and its

frequency response characteristics were studied. The gain, bandwidth, input resistance and

output resistance are as follows.

&it> %ee56a? &it>out %ee56a?

#ain

'an5@i5t>

In0ut Re2i2tane

Out0ut Re2i2tane

REVIE& QUESTIONS:

1. :hat is feedback amplifierM. :hat are the adantages of negatie feedback in amplifiersM'. 8s positie feedback used in amplifiersM :hyM&. :hat is meant by current series feedback amplifierM/. :hat is the feedback factor for current feedbackM


8/105

EXPT. NO: 1'

DATE:

AIM:To design, construct and study the frequency response of oltage shunt amplifier with or

without feedback and to calculate the input and output resistance.APPARATUS REQUIRED:

S.No. Name Value / Range Quantity

1. Transistor BC107 1

. !esistors ! "#1$%,!C#&.7$%,

!1# ,!#

1

'. Capacitors 0.1(f

(f

1&. )unction *enerator 0+ 10- 1

/. C! '0 - 1

. !egulated 2ower 3upply 40+'056 1

7. Bread Board 1

TEOR!:

)eedback is used in the amplifier to improe its performance and to make it more ideal.

8n the process of feedback, a part of output is sampled and fed back to the input of the amplifier.

Therefore, at input we hae two signals9 8nput signal and part of the output which is fed back to

the input. Both these signals may be in phase or out of phase.

:hen input signal and part of output signal are in phase, the feedback is called positie

feedback. n the other hand, when they are in out of phase, the feedback is called negatie

feedback. The positie feedback results in oscillations and hence not used in amplifiers.

Therefore, the noise in amplifier can be reduced by using negatie feedback. 8t reduces the gain

of the amplifier, but it has the adantages of reduced distortion, increased stability in gain and

increased bandwidth.

VO$TA#E SUNT %EED'A"( AMP$I%IER


9/105

8n this feedback amplifier, when the base oltage 45B6 increases, base current 48B6

increases. Hue to this increase in base current 48B6, collector current 48C6 also increases. This

increase in collector current 48C6 reduces the collector oltage 45C6. Now this oltage signal is

"IR"UIT DIA#RAM: oltage 2>unt am0liie, @it>out ee56a?

%ig. 1. &ITOUT %EED'A"(

TA'U$ATION: oltage 2>unt am0liie, @it>out ee56a?

$eep the input oltage constant, )Vin* +%,e-ueny

)in *

Out0ut Voltage )Vo*

)in olt2*


)in 5'*


10/105

"IR"UIT DIA#RAM:

%ig. 3. &IT %EED'A"(

TA'U$ATION: oltage 2>unt am0liie, @it> ee56a?$eep the input oltage constant, 4Vin* +

%,e-ueny

)in *

Out0ut Voltage )Vo*

)in olt2*


)in 5'*


11/105

gien as input through feedback. That is, the output oltage at collector is added to input oltage

at base.

)or the increased base oltage, the decreased collector oltage 45C6 signal is gien as

feedback to the input signal. Therefore both the signals are in out of phase, hence negatie

feedback is used. -ere the feedback is gien through the oltage and hence it is called as oltage

shunt feedback. The feedback is proided for the oltage shunt feedback amplifier by including

the feedback resistance!) and the feedback capacitor C) in the feedback path from the collectorto the base.

PRO"EDURE:

1. The circuit is connected as shown in circuit diagram fig 416 without feedback.

. The input signal is set using the function generator.

'. Check the output using C! and note the corresponding output oltage.

&. The gain is calculated using the formula, *ain 4in dB6 # 0 log 45in ; 5o6.

/. The circuit fig 46 is connected as shown in circuit diagram with feedback.

4by including !) and C)6.

. 3teps , ', & were repeated.

7. < graph was drawn between *ain 4in dB6 and frequency 4in -6 for both cases.

=. )rom the graph, bandwidth and cut+off frequencies were calculated.


12/105

MEASUREMENT O% INPUT AND OUTPUT RESISTAN"E:

1. easure ac oltage5acand ac current8acat the input side between base and

ground in fig. 1 without feedback using multimeter.

. )rom the 5acand 8acmeasured at the input, calculate the input resistance.

'. easure ac oltage5acand ac current8acat the output side between collector

and ground in fig. 1 without feedback using multimeter.

&. )rom the 5acand 8acmeasured at the output, calculate the output resistance.

/. !epeat steps 1 to & for the circuit in fig. with feedback.

MODE$ #RAP:

)>? >ower cut+off frequency without feedback)@? @pper cut+off frequency without feedback)>f? >ower cut+off frequency with feedback)@f ? @pper cut+off frequency with feedbackBandwidth 4without feedback6 # )@+ )>Bandwidth 4with feedback6 # )@f+ )>f

DESI#N:

5cc # 1 5 8c # 1.mout %ee56a?

#ain

'an5@i5t>

In0ut Re2i2tane

Out0ut Re2i2tane

REVIE& QUESTIONS:

1. :hat is the effect of oltage shunt feedback on input resistanceM. :hat is oltage shunt feedbackM'. -ow does negatie feedback influence the noise and the input output impedancesM&. :hy negatie feedback is employed in high gain amplifiersM/. Hefine positie and negatie feedback.EXPT NO: 3A R" PASE SI%T OS"I$$ATOR DATE :

AIM:To design a !C phase shift oscillator and to obsere the output waeforms.

APPARATUS REQUIRED9


1. Transistor BC107 1. !esistors ! "#1$P , ! C#&.7$P,

!1 # ,!#

! #/$P

1

1

''. Capacitors C C1,C C #0.1Qf, C" # Qf

C#0.01 Qf

1

'&. )unction *enerator 0+ 10- 1/. C! '0- 1. !egulated 2ower 3upply 40+'056 1

7. Bread Board 1

"IR"UIT DIA#RAM:


16/105

MODE$ #RAP:

TA'U$ATION:

S.NOAMP$ITUDE

)Volt2*TIME)m2e*

%REQUEN"!)e,t*

%ORMU$A:

The Theoretical frequency of !C 2hase 3hift scillator is gien by


17/105

:here $# !C ; !

TEOR!:)or !C 2hase shift oscillator Common "mitter single stage amplifier is used and for

phase shifting network three identical !C networks are used. The output of the feedback network

gets loaded due to low input impedance of a transistor. -ence an emitter follower input stage

before the C" configuration amplifier stage can be used. But if only single stage is to be used

then the oltage shunt feedback is to be used and it is denoted by !' connected in series with the

amplifier input resistance.

PRO"EDURE:

1. Connect the circuit as per the circuit diagram.

. @sing the function generator set the input oltage for 1 $-.

'. bsere the output waeforms for 1 $-.

&. 2lot the graph for the obsered outputs.

DESI#N:

5cc # 1 5 8c # 1.mC oscillator circuit of using two capacitie reactance and one

inductie reactance in its feedback network for the frequency of oscillation /./ $-.

APPARATUS REQUIRED:

S.No. Name Value / Range Quantity1. Transistor BC107 1. !esistors ! "#1$% , !C#&.7$%

!1# ,!#

1

1'. Capacitors 0.1(f ,(f,

0.01 (f

1&. 8nductor 1m-, =0 m- 1


20/105

/. )unction *enerator 0+ 10- 1. C! + 17. !egulated 2ower 3upply 40+'056 1=. Bread Board + 1

"IR"UIT DIA#RAM:

%ig. 1. ART$E! OS"I$$ATOR

MODE$ #RAP:

TA'U$ATION:


21/105

S.NOAMP$ITUDE

)Volt2*TIME)m2e*

%REQUEN"!)e,t*

TEOR!:

The amplifier stage uses an actie deice as a transistor in C" configurationproides a phase shift of 1=0. :hereas in feedback network, the centre of >1 and > isgrounded, where upper end becomes positie, the lower becomes negatie and ice ersa. 3o the>C feedback network gies an additional phase shift of 1=0 necessary to satisfy oscillationsconditions. 8t can be used for frequencies between 1 - /00 -.%ORMU$A:

The Theoretical frequency of -artley scillator is gien by

f # 1; 4URC 4>eq66

where >eq# >1 E >PRO"EDURE:

1. The circuit connected as shown in fig.1. The output is measured across collector and ground using C!.'. The amplitude, time and frequency are obsered and graph is plotted.

DESI#N:

5cc # 1 5 8c # 1.m1 # 1 m-, > # =0 m-The theoretical frequency of -artley oscillator is gien by

) # 1;4OR4C >eq6 where >eq#>1E >Choose c#0.01(f and f# /./$- and substituting in the aboe formula we get>eqS=1 m-

>et >1 # 1 m-, > # =0 m-, C # 0.01 (f

RESU$T:The -artley oscillator for the gien frequency is designed and tested.

Theoretical frequency f #btained frequency f #

REVIE& QUESTIONS:1. :hat is -artley scillatorM. *ie the condition and frequency of scillation of a -artley scillator.'. :hat is the Barhausen criterion for the feedback scillatorsM&. :hat type of reactance determines the frequency of scillations in a -artley

scillatorM/. -ow does -artley scillator differ from ColpittVs scillator in constructionM

EXPT. NO: B' "O$PITTS OS"I$$ATOR

DATE :AIM:

To design and test >C oscillator circuit of using two capacitie reactance and oneinductie reactance in its feedback network for the frequency of oscillation =.' $-

APPARATUS REQUIRED:S.No. Name Value / Range Quantity

1. Transistor BC107 1

. !esistors ! "#1$% ,!C#&.7 $%,

!1# ,!#

1


24/105

'. Capacitors 0.1(f

(f,0. (f,0.0 (f

1&. 8nductor 0m- 1

/. )unction *enerator 0+ 10- 1

. C! '0- 1

7. !egulated 2ower 3upply 40+'056 1

=. Bread Board + 1

"IR"UIT DIA#RAM:

%ig.1. "O$PITTS OS"I$$ATOR

MODE$ #RAP:

BC107

C2

CRO

VCC

R1

R2

RC

RE C

EC1

L

CC1

CC2

Vo


25/105

TA'U$ATION:

S.NOAMP$ITUDE

)Volt2*TIME)m2e*

%REQUEN"!)e,t*

TEOR!:

< >C oscillator which uses two capacitie reactances and one inductie reactance

in the feedback network, which is a tank circuit is called colpittVs oscillator. The amplifier stage

uses an actie deice as a transistor in C" configuration. The basic circuit is same as

transistoried -artley oscillator, eWcept the tank circuit. The common emitter amplifier proidesa phase shift of 1=0. :hereas in feedback network, the centre of C1 and C is grounded where

upper end becomes positie, the lower becomes negatie and ice ersa. 3o the >C feedback

network gies an additional phase shift of 1=0 necessary to satisfy oscillating conditions. 8t can

be used for frequencies between 1 - to /00 -.

%ORMU$A:

The Theoretical frequency of Colpitts scillator is gien by

f # 1; 4UR >Ceq6 where Ceq# 4C1C6; 4C1EC6PRO"EDURE:

1. The circuit connected as shown in fig.1

. The output is measured across collector and ground using C!.

'. The amplitude, time and frequency are obsered and graph is plotted.

DESI#N:

5cc # 1 5 8c # 1.m # 0 m-The theoretical frequency of -artley oscillator is gien by) # 1;4OR4> Ceq6 where Ceq#4C1C6;4C1E C6Choose C1# 0.(f, C#0.0(f and f# =.'$- and substituting in the aboe formula we

get > S0 m->et C1# 0.(f, C#0.0(f , > # 0 m-

RESU$T:

The Colpitts oscillator for the gien frequency is designed and tested.Theoretical frequency f #btained frequency f #

REVIE& QUESTIONS:1. :hat is Colpitts scillatorM. ention the eWpression for frequency of scillations for Colpitts scillator.'. :hat type of reactance determines the frequency of scillations in a Colpitts

scillatorM&. :hat are the basic mathematical conditions for sustaining scillations in an

scillatorM/. :hat are the >+C scillators preferred oer !+C oscillators at high frequencies say in

- rangeMEXPT. NO: C TUNED "$ASS " AMP$I%IER

DATE:AIM:

To design, construct and study the frequency response of tuned class C amplifier and to

estimate its resonant frequency and bandwidth.

APPARATUS REQUIRED:


28/105


1. Transistor ;BC107 1

. !esistors ! "#1$%, !B#10 $% 1

'. Capacitors0.01(f

0.1 (f

'

1

&. 8nductor /m- 1

/. )unction *enerator 0+ 10- 1

. C! '0- 1

7. !egulated 2ower 3upply 40+'056 1

=. Bread Board 1

"IR"UIT DIA#RAM:


29/105

%ig. 1. TUNED "$ASS " AMP$I%IER

MODE$ #RAP:

TEOR!:

FG CRO


30/105

The amplifier is said to be class C amplifier if the X+point and the input signal are

selected such that the output signal is obtained for less than half a cycle, for a full input cycle.

That is, for class C amplifier the operating point is chosen beyond the cut+off region. Hue to such

a selection of the X+point, transistor remains actie, for less than a half cycle. -ence only that

part is reproduced at the output. )or remaining cycle of the input cycle, the transistor remains

cut+off and no signal is produced at the output.

-ere a parallel resonant circuit acts as load impedance. C

PRO"EDURE

1. The circuit is connected as shown in circuit diagram. 4)ig. 16

. The input signal 5inis set using the function generator.

'. $eeping the input oltage constant, ary the frequency from 1 $- to 10 -

in regular steps and note down the corresponding output oltage 5o.&. The gain is calculated using the formula, *ain 4in dB6 # 0 log 45in ; 5o6.

/. 2lot the graph, *ain 4in dB6 5s frequency 4in -6.

. Calculate the resonant frequency and its bandwidth.

DESI#N:*ien 5cc # 1 5

The resonant frequency is gien by

fr # 1; JR>C

Therefore, ># 1; &JfC


31/105

1;JfCe# 0.1 K 1000# 100

1;JK100#fCe

fCe # 0.001/L', where f# 10 $-

"e# 0.001/L'; 10000 # 0.1/LK 10++ 4.1

TA'U$ATION:

$eep the input oltage constant, )Vin* +

%,e-ueny

)in *

Out0ut Voltage )Vo*

)in olt2*


)in 5'*

RESU$T:

Thus the tuned class C amplifier was designed and its frequency response was studied. 8ts

estimated alues are9

!esonant )requency #

Bandwidth #

REVIE& QUESTIONS:


32/105

1. :hat is resonance frequencyM :rite the formula for resonant frequency of an >C tankcircuit.

. :hy is a combination of > and C called as tank circuitM'. :hat are the applications of class C tuned amplifierM&. -ow the operating point is chosen for the class C tuned amplifierM

/. *ie the adantages and disadantages of tuned amplifier.

EXPT. NO: DI%%ERENTIATORF INTE#RATORF

"$IPPERS AND "$AMPERS


33/105

DATE:

AIM:

To design a differentiator, integrator, clipper and clamper circuit and to obsere the

output waeform.

APPARATUS REQUIRED:


1. Hiode 1N&001 or 1N&007

. !esistors 10$% 1

'. Capacitors 0.1(f 1

&. )unction *enerator 0+ 10- 1

/. C! '0- 1


7. Bread Board 1

TEOR!:

DI%%ERENTIATOR:

< differentiator is a simple !C network, whose time constant 4T#!C6 is ery small4!CYY G 6 in comparison with the time required for the input signal to make an appropriatechange. The oltage drop across ! will be ery small in comparison to the drop across capacitorC. 3o the current is determined entirely by the capacitor. Therefore, the output oltage is gienby,

i#C 4d;dt6

5o# i!# C 4d;dt6 !# !C 4d;dt6Thus the output is proportional to the deriatie of the input.

INTE#RATOR:

The !C network haing the time constant 4!C6 is ery large 4!CYYG6 in comparisonwith the time required for the input signal to make an appropriate change, then it can be called as


34/105

integrator. The oltage drop across capacitor C will be ery small in comparison to the dropacross resistor !. 3o the current is determined entirely by the resistor !. Therefore, the outputoltage is gien by,

5o# H1;C Z i dt ! # 1;!C Z i dtThus the output is proportional to the integration of input.

"$IPPERS:The circuit, with which the waeform is shaped by remoing 4or clipping6 a certainportion of the input signal oltage aboe or below a certain leel, is called as [Clipper\. 8t is alsoknown as oltage 4or current6 limiters, amplitude selectors or slicers.< clipping circuit requires a minimum of one diode 4either in series or parallel6 and one resistor.Hepending on the orientation of the diode and the polarity of the reference oltage, the inputsignal will clip. 2ower supply is often used to set the arious clipping leels. Hifferent types ofclipper circuits are

1. 2ositie Clipper . Negatie Clipper '. Biased Clipper &. Combinational Clipper

"$AMPERS:

The clamping network is one that will clamp an input signal to a different dc leel. Thenetwork consists of a capacitor, a diode and a resistance, but it can also hae an independent HCsupply to introduce an additional HC shift. They are also called as dc restorer or dc insertercircuits. The magnitude of ! and C must be chosen such that the time constant, G # !C, is largeenough to ensure that the oltage across the capacitor does not discharge significantly during theinteral when the diode is non+conducting. Hifferent types of clamping circuits are9

1. 2ositie Clamper .Negatie Clamper DESI#N:

1* DI%%ERENTIATOR AND INTE#RATOR9

To find ! and C,>et choose frequency )# 1 $-Time 2eriod T# 1; ) # 1ms

Time Constant G # !C# T# 1mset choose frequency )# 1 $-

Consider T# 1;f #G # !C# 1msec


35/105

%ig.1. DI%%ERENTIATOR

MODE$ #RAP:

%# C!


36/105

%ig.3. INTE#RATOR

MODE$ #RAP:

"$IPPERS:

FG C!O


37/105

%ig. B. POSITIVE "$IPPER )&ITOUT 'IAS*

MODE$ #RAP:

FG C!O


38/105

%ig. C. POSITIVE "$IPPER )&IT 'IAS*

MODE$ #RAP:


39/105

%ig. . NE#ATIVE "$IPPER )&ITOUT 'IAS*

MODE$ #RAP:


40/105

%ig.


41/105

%ig. . "OM'INATIONA$ "$IPPER

MODE$ #RAP:


42/105

"$AMPERS:

%ig. J. POSITIVE "$AMPER

MODE$ #RAP:


43/105

%ig. K. NE#ATIVE "$AMPER

MODE$ #RAP:

PRO"EDURE:1. Connect the circuit as per the circuit diagram.. 3et input oltage 5i# /5 and frequency f# 1 $- using signal generator.


44/105

'. bsere the output waeform using C! and sketch it out.TA'U$ATION:

Ty0e o "i,uit In0ut &aeo,m Out0ut &aeo,mAm0litu5e

)V*

Time

)m2e*

Am0litu5e

)V*

Time

)m2e*Hifferentiatorwhen !C# T

!C]]T

!CYYT8ntegratorwhen !C# T

!C]]T

!CYYT2ositie Clipper :ith Bias

:ithout BiasNegatie Clipper:ith Bias

:ithout BiasCombinational

Clipper2ositie Clamper

Negatie Clamper

RESU$T:

Thus integrator, differentiator, clipper and clamper circuits were designed and theiroutput waeforms were studied and drawn.

REVIE& QUESTIONS:1. :hen does a high pass filter circuit acts as a differentiatorM. :hat is the difference between linear and non linear wae shaping circuitsM'. :hat is the draw back of haing a diode as a series element in a clipperM&. >ist two uses of clamping circuits./. :hat is the difference between clipping and clampingM


45/105

EXPT. NO: &EIN 'RID#E OS"I$$ATOR

DATE :

AIM:

To design and test :ein Bridge oscillator for a frequency of / $-.APPARATUS REQUIRED9


1. Transistor BC107<

. !esistors

/'. Capacitors 1

&. )unction *enerator 0+ 10- 1

/. C! '0- 1


7. Bread Board 1"IR"UIT DIA#RAM:

%ig.1. &EIN 'RID#E OS"I$$ATOR


46/105

MODEL GRAPH:

DESI#N PRO"EDURE: %o, t,an2i2to, Q1

5cc # 1 5 8c # 1.m%E )o,* +=====F TON+3.%ER")"OOSE R $ESS TAN >%ER"*R1+R3+R+========

TO%% + 4.


54/105

the collector current of one stage is at a maWimum when the collector current of the other is cut

off.


55/105


56/105

AIM:

To design and implement a monostable multiibrator circuit.

APPARATUS REQUIRED9

S.No. Name Value / Range Quantity1. Transistor BC107 . !esistors ,! ', !&

!C1, !C

1

1'. Capacitors 1&. )unction *enerator 0+ 10- 1/. C! '0- 1. !egulated 2ower 3upply 40+'056 1

7. Bread Board 1

"IR"UIT DIA#RAM:

%ig.1. MONOSTA'$E MU$TIVI'RATOR

MODE$ #RAP:


57/105

DESI#N:

T# 0.L !TCT

>et !T # &7$P and


58/105

CT# 0.0Qf

T# 0.L W &7W 10'W 0.0 W 10+

>et C# 0.1^f, !'# /0 P

5CC#15, 5BB#+5, 8C#m


59/105

TEOR!:

ultiibrator is a type of relaWation oscillator consisting of a two stage resistancecoupled amplifier, with the output of each stage coupled regeneratie to the other. 8n operation,


off.


60/105

S.NOAm0litu5e

)olt2*Time)2e2*

%,e-ueny)e,t*

13

BC

V61V1

V63V3

RESU$T:

Thus the monostable multiibrator circuit was designed and implemented.

REVIE& QUESTIONS:

1. :hat is a onostable ultiibratorM. :hat does the triggering rate depend on in a onostable ultiibratorM'. :hat are the adantages of negatie collector triggering of a onostable

ultiibratorM

&. :hat are the applications of onostable ultiibratorM/. -ow a onostable ultiibrator circuit can be made from an


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"IR"UIT DIA#RAM:

%ig. 1. 'ISTA'$E MU$TIVI'RATOR

MODE$ #RAP:


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DESI#N PRO"EDURE:

V""+13VF V"E)SAT*+4.BF I")SAT*+3mAF >e+=======

!C1#!C#!C# 45CC+5C"43


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#DDDDDDD.

!#5!;8

#DDDDDDD

81#8BE8

#DDDDDDDD

!CE!1#45CC+5B"16;81

!1# 445CC+5B"16;816+!C

#DDDDDDD

TEOR!:

ulti ibrator is a type of relaWation oscillator consisting of a two stage resistance

coupled amplifier, with the output of each stage coupled regeneratie to the other. 8n operation,


off.


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PRO"EDURE:

1. The circuit is connected as shown in circuit diagram.

. < trigger pulse is applied to the set and reset terminal.

'. The output waeforms at the collector X1 and X were noted.

&. The graphs are plotted for the obsered output.

TA'U$ATION:

S.NOAm0litu5e

)olt2*Pul2e@i5t>

Time)2e2*

%,e-ueny)e,t*

RESU$T:

Thus the bistable multiibrator circuit was designed and implemented.

REVIE& QUESTIONS:

1. Hefine [stable state\ of a bistable multiibrator.. -ow is loading aoided in bistable multiibratorM


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'. :here is bistable multiibrator usedM&. :hy the bistable multiibrator is also called the flip flop multiibratorM/. :hat is the function of commutating capacitors in multiibratorsM


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EXPT. NO: 1DATE: DI%%ERENTIA$ AMP$I%IER

AIM:To implement differential amplifier using 2328C".

APPARATUS REQUIRED:

2C :8T- 328C" 3imulation 3oftware

"IR"UIT DIA#RAM: DI%%ERENTIA$ AMP$I%IER"ommon mo5e


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1 2 . 0 0 V

5 . 2 6 4 V

Q b r e a k N

Q 1

0

- 1 9 . 8 1 m V

5 . 2 6 4 V

R 1

R b r e a k

6 . 8 k

R 3

5 . 6 k

Q b r e a k N

Q 2

V 2

1 2 v

- 7 9 3 . 8 m V

V + V -

R 2

R b r e a k

6 . 8 k

V 3

- 1 2

0

0

R 5

1 k

V 12 0 m v

0 V d c

DI%%ERENTIA$ MODE


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- 7 8 3 . 9 m V

V 2

1 2 v

Q b r e a k N

Q 2

0

R 2

R b r e a k

6 . 8 k

V +

0

R 5

1 k

V 12 0 m v

0 V d c

0

Q b r e a k N

Q 1

V 3

- 1 2

V -

R 4

1 k

5 . 2 5 8 V

- 9 . 9 1 6 m V

5 . 2 5 8 V

R 3

5 . 6 k

R 1

R b r e a k

6 . 8 k

0

1 2 . 0 0 V

NET$IST:Common mode netlist9KKK 0';'1;1 '91791/ KKKKKKKKK 23pice L. 4ar 0006 KKKKKKKK 8H` 0 KKKKKKKKKK 2rofile9 3C-""


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XDX1 N00=0L N10'L7 N00&L XbreakN!D!1 N00=0L N00=7/ !break .=k5D5' N0='='1 0 +1XDX N00=& N10'L7 N00&L XbreakN!D! N00=& N00=7/ !break .=k

!D!' N0='='1 N00&L !break /.kKKKK !"3@8N* common mode+schematic1+ert.sim.cir KKKK."NH

Hifferential mode Netlist9

KKKK 0';'1;1 '9&9L KKKKKKKKK 23pice L. 4ar 0006 KKKKKKKK 8H` 0 KKKKKKKK KK 2rofile9 3C-""


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"OMMON MODE:

DI%%ERENTIA$ MODE:

TEOR!:

< differential amplifier amplifies the difference between two oltages 51and 5. The

output of the differential amplifier is dependent on the difference between two signals and the

common mode signal. 3ince it finds the difference between two inputs,it can be used as a

subtractor. The output of differential amplifier is5o # ! f; !145 ? 516

PRO"EDURE:

1. *o to start program ? rcad release L.1 ? C


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. Hraw the circuit diagram and mark the nodes. 3ae the file.

'. *o to file ? open simulation and create a new simulation file.

&. *o to simulation !@N. Now the result can be iewed either in the output file or in

graphical simulation file.

RESU$T:

Thus a differential amplifier was implemented using 2328C".

REVIE& QUESTIONS.1. Hefine C!.. :hat is meant by Hifferential mode gainM'. :hat is meant by differential amplifierM&. :hat are the applications of differential amplifierM/. :hat is meant by Common mode gainM


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EXPT. NO: 3a

DATE: SE"OND ORDER $O&PASS I# PASS %I$TER

AIM:To design the 3econd rder >ow pass )ilter using 2+328C".

APPARATUS REQUIRED:

2C :8T- 328C" 3imulation 3oftware"IR"UIT DIA#RAM: Seon5 O,5e, $o@ 0a22 %ilte,

C 1

0 . 1

V 11 V a c

0 V d c 4 . 7 5 9 V

V

C 2

0 . 1

- 1 0 . 2 4 V

- 8 0 . 9 3 V

R 1

1 k

- 2 4 2 . 4 V

V 2

1 5 v

0 V- 1 6 1 . 9 V

R 2

1 k

0

0 V

! 1

" # 7 4 1

3

2

7

4

6

1

5+

-

V

+

V

-

O ! $

O % 1

O % 2

NET$IST

KKKK 0';'1;1 '909/ KKKKKKKKK 23pice L. 4ar 0006 KKKKKKKK 8H` 0 KKKKKKKKKK 2rofile9 3C-""


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KKKK 8NC>@H8N* order+3C-"


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RESU$T:

Thus the low pass filter was designed and implemented using 2328C".

REVIE& QUESTIONS:

1. :hat is meant by filterM. :rite the different types of filterM'. :hat is meant by >2) filterM&. :hat is meant by B2) filterM


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EXPT. NO: 36

DATE: SE"OND ORDER I# PASS %I$TER

AIM:To design the 3econd rder -igh pass filter using 2328C".

APPARATUS REQUIRED:


"IR"UIT DIA#RAM:

Seon5 o,5e, 'utte,@o,t> ig> 0a22 ilte,

C 4

0 . 1

R 5

1 k! 1

" # 7 4 13

2

7

4

6

1

5+

-

V

+

V

-

O ! $

O % 1

O % 2

4 . 7 5 9 V

0

V

R 6

1 k

V 2

1 5 v

0 V

- 2 4 2 . 3 V

0 VR 3

1 k

R 4

1 k - 1 0 . 2 4 V

C 3

0 . 1

V 11 V a c0 V d c

- 8 0 . 9 3 V

- 1 6 1 . 5 V

- 2 4 2 . 3 V

NET$IST:

3econd order Butterworth -igh pass filter Netlist

KKKK 0';'1;1 9/917 KKKKKKKKK 23pice L. 4ar 0006 KKKKKKKK 8H` 0 KKKKKKKKKK 2rofile9 3C-""


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.


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EXPT NO:Ba

DATE: ASTA'$E MU$TIVI'RATOR

AIM:

To implement the astable multiibrator and to plot the output.

APPARATUS REQUIRED:


"IR"UIT DIA#RAM:"


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.lib nom.libK


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:hen 5cc is applied, each transistors conducts and capacitors C1 and C take on charge

as the oltage increases. < perfect balance of the initial collector current is impossible. The

unbalance starts multiibrator action. The condition of unbalance is cumulatie and quickly

results in the collector current of one transistor reaching its maWimum while the collector current

of other is cut off. Hue to the capacitie coupling, howeer neither transistor can remain cut off

permanently. 8nstead the circuit has two quasi stable states. Thus astable multiibrator is self

starting and free running.

PRO"EDURE:



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EXPT. NO: B6

DATE: MONOSTA'$E MU$TIVI'RATOR

AIM:To plot the transient response of onostable ultiibrator using 2328C".

APPARATUS REQUIRED:

2C :8T- 2328C" 3imulation 3oftware"IR"UIT DIA#RAM:

onostableultiibrator

NET$IST: MONOSTA'$E

KKKK 0';'1;1 '90L9/1 KKKKKKKKK 23pice L. 4ar 0006 KKKKKKKK 8H` 0 KKKKKKKKKK 2rofile9 3C-""


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.8NC ._mononew+3C-"@H8N* mononew+3C-"


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graphical simulation file

RESU$T:

The onostable multiibrator was designed and transient response was plotted using2328C".


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EXPT. NO:B

DATE: 'ISTA'$E MU$TIVI'RATOR

AIM:To implement the bi+stable multiibrator and to plot the output.

APPARATUS REQUIRED:

2C :8T- 2328C" 3imulation 3oftware"IR"UIT DIA#RAM:

Bistableultiibrator

R 3

1 0 k

R 5

3 9 0 k

0

0C 4

2 0 0 & '

0 V

Q b r e a k N

Q 1

V

0

V 2

$ ( ) 0

$ F ) 1 * , ) 5 0

R ) 1 0 0

V 1 ) 0

$ R ) 1 *

V 2 ) 1 0

C 2

2 0 0 & '

0 V

2 . 9 5 4 V

R 6

3 9 0 k

0

1 0 . 0 0 V

R 1

3 9 k

C 3

2 0 0 & '

( 5

( 1 N 9 1 4

V 1

1 0

4 . 6 3 4 V

0 V

0

R 2

3 9 k

0 V

2 . 9 5 4 V

V 3

- 1 0

R 4

1 0 k

0 V

8 1 7 . 2 m V

C 1

2 0 0 & '

0

R 7

1 k

( 3

( 1 N 9 1 4

Q b r e a k N

Q 2

V

R 8

1 k

- 1 0 . 0 0 V

8 2 4 . 5 m V

V

4 . 6 3 4 V

0 V

NET$IST: 'ISTA'$EKKKK 0&;01;1 19//9&0 KKKKKKKKK 23pice L. 4ar 0006 KKKKKKKK 8H` 0 KKKKKKKKKK 2rofile9 3C-"


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KKKK C8!C@8T H"3C!82T8NKKKKKKKKKcreating circuit file bistable1+schematic1+f.sim.cir KK :> *"N"!3" 0 10 0 1n 1n /0u 100uHDH' N01' N017= H1NL1&KKKK !"3@8N* bistable1+schematic1+f.sim.cir KKKK."NH


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OUTPUT &AVE%ORM:

TEOR!:

The bi+stable multiibrator has two stable states. The multiibrator can eWist indefinitely

in either of the two stable states. 8t requires an eWternal trigger pulse to change from one stable

state to another. The circuit remains in one stable state until an eWternal trigger pulse is applied.

The bi+stable multiibrator is used for the performance of many digital operations such as

counting and storing of binary information. The multiibrator also finds an application in

generation and pulse type waeform.

PRO"EDURE:1. *o to start program ? rcad release L.1 ? C


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'. :hat meant by


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EXPT. NO: C6

DATE: A/D "ONVERTER

AIM:

To deelop the 2328C" programs for analog to digital conerter and analye its

frequency response characteristics.

APPARATUS REQUIRED:

2C :8T- 2328C" 3imulation 3oftware.

"IR"UIT DIA#RAM:


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TEOR!:

The analog signal obtained from the transducer is band limited by antialiasing filter. The signal is

then sampled frequency rate more than twice maWimum frequency of the band limited signal.The sampled signal has to be held constant while conersion is taking place in


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. :hat is meant by !esolutionM'. :hat is meant by


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. easuring of real power

'. Hetecting phase ?angle difference between two signals of equal frequency.

PRO"EDURE:



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"MOS INVERTER

EXPT. NO


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V 2

$ ( ) 0

$ F ) 1 * , ) 2 0 0 * R ) 4 0 0 *

V 1 ) 0

$ R ) 1 *

V 2 ) 5 v

V

0

# 4

# b r e a k

0

0

0 V

0 V

V

V 3

5 v5 . 0 0 0 V

5 . 0 0 0 V

# 1

# b r e a k N

NET$IST: "MOS INVERTERKKKK 0';'1;1 '9'9'' KKKKKKKKK 23pice L. 4ar 0006 KKKKKKKK 8H` 0 KKKKKKKKKK 2rofile9 3C-"@H8N* inerter+3C-"3" 0 / 0 1n 1n 00n &00n5D5' N01'7/ 0 /KKKK !"3@8N* inerter+3C-"


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OUTPUT &AVE%ORM:

TEOR!:

The main adantage of a C3 gate is its remarkably low static power dissipation.

These circuits take adantage of the fact that both N3 and 23 transistors can be

fabricated on the same substrate. C3 circuit consists of both types of 3 deicesinterconnected to form logic functions. >ow power consumption is one of the maor adantages.

PRO"EDURE:



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&. :hat is meant by 23M/. :hat is meant by N3M

EXPT. NO:


100/105

0 V

# 3

# b r e a k

V 3

5 v

0 V

2 . 5 0 0 V

V

V 1

$ ( ) 1 0 *

$ F ) 1 * , ) 1 0 0 * R ) 2 0 0 *

V 1 ) 0

$ R ) 1 *

V 2 ) 5

0 VV

5 . 0 0 0 V

0

0

V

# 4

# b r e a k

0

5 . 0 0 0 V

# 1

# b r e a k N

0

# 2

# b r e a k N V 2

$ ( ) 2 5 *

$ F ) 1 * , ) 1 0 0 * R ) 2 0 0 *

V 1 ) 0

$ R ) 1 *

V 2 ) 5

%ig.1 "MOS NAND #ATE

NET$IST:C3 N@H8N* cmos nand+3C-"


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E2@>3" 0 / 10n 1n 1n 100n 00n5D5 N0107& 0E2@>3" 0 / /n 1n 1n 100n 00n5D5' N00/7L 0 /KKKK !"3@8N* cmos nand+3C-"


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REVIE& QUESTIONS.

1. :rite the Truth table of


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V

0

0

# 4

# b r e a k N

V

0

V 3

$ ( ) 2 5 *

$ F ) 1 * , ) 2 0 0 * R ) 4 0 0 *

V 1 ) 0 v

$ R ) 1 *

V 2 ) 5

0 V

V 2

$ ( ) 1 0 *

$ F ) 1 * , ) 1 0 0 * R ) 2 0 0 *

V 1 ) 5

$ R ) 1 *

V 2 ) 0

V 1

5 v

5 . 0 0 0 V

# 6

# b r e a k

# 3

# b r e a k N

# 5

# b r e a k

5 . 0 0 0 V

0 V

V

7 0 7 . 7 V

0

5 0 . 0 9 * V

%ig.1 "MOS NOR #ATENET$IST: "MOS NOR

KKKK 0';'1;1 '9&&9'1 KKKKKKKKK 23pice L. 4ar 0006 KKKKKKKK 8H` 0 KKKKKKKKKK 2rofile9 3C-"@H8N* cmos nor+3C-"


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E2@>3" 0 / /n 1n 1n 00n &00nD/ N0&&/& N010/L N01''L N01''Lbreak2D N0&/&7 N00L70 N0&&/& N0&&/&break25D51 N01''L 0 /5D5 N010/L 0

E2@>3" / 0 10n 1n 1n 100n 00nD' N0&/&7 N00L70 0 0 breakNKKKK !"3@8N* cmos nor+3C-"


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REVIE& QUESTIONS. 1. :rite the Truth table of ! *

ec ii lab manual prince college

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