e4.lee1 software/hardware reconfigurable network processor for space networks clement lee andrew...

Lee 1 E4.

Software/Hardware Reconfigurable Network Processor for Space

Networks

Clement Lee

Andrew Gray, Jeff Srinivasan, Allen Farrington, Valerie Stanton, Ken Peters, Yong Chong

Lee 2 E4.

Introduction

• Motivations for software reconfigurable paradigm in space applications

• Description of a reconfigurable architecture

• Design methodologies

• NavaTyrr: prototype transceiver for space-based applications based on this architecture

• Potential technology infusion to missions– ST-5

– StarLight

• Future development

Lee 3 E4.

Software Reconfigurable Paradigm

• The primary motivations behind the space-based software reconfigurable network processor are the following:– Providing long-life communications infrastructure enabled by on-orbit

processor reconfiguration.

– Providing greatly improved science instrumentation and processing capabilities through on-orbit science-driven reconfiguration.

– Enabling rapid laboratory prototyping and rapid uploading designs of communications, navigation, and science signal processing functions to spacecraft.

Lee 4 E4.

•Motivation: Long Life Numerous potential applications and network interactions cannot be anticipated at mission launch. Moreover, the value of adapting to these unpredictable needs is extremely high, driving the need for reconfigurability. Space missions last for many years beyond the technology.


Lee 5 E4.


Science ProcessingR equirm ents

M iss ion C om m unicationsand N avigation R equirem ents

Engineering D esign, H igh Level D evelopm entLanguages, C AD T ools, R eal-T im e O perating

System s, H ardware D escription Languages

G round T est R econfigurab leN etwork P rocessor

O n-O rb it R econfiguration ofN etwork P rocessor

Science-Driven System Architecture

Deep Space Hardware/SoftwareConfiguration File Upload:

Infusion Into Science M issions

Science D ata G athering andProcess ing and

T ransm iss ion to Earth

Science and EngineeringC om m unity

G round

S pace

•Motivation: Providing greatly improved science instrumentation and processing capabilities

Lee 6 E4.


• Motivation: To enable rapid laboratory prototyping and rapid space-qualified implementations of communications, navigation, and science signal processing functions

• Advanced technologies in the following areas make this rapid prototyping effort possible– Flexible design platform using microprocessors and FPGAs

– State-of-the art computer aided design tools• Accelerate design and development

• Eliminate human error

• Quick turn around for changes

Lee 7 E4.

Reconfigurable ArchitectureRISC (Reduced Instruction Set Computer) Processor, FPGA (Field Programmable Gate Array), and RTOS (Real-Time Operating System):

Software Processor(G3 Power PC)

Physical Layer(Software-D efined R adio)

D ata L ink Layer

N etwork Layer

Application Layer

Reconfigurable Hardware(Xilinx FPGA)

Processing Im plem ented inPower E ffic ient

R econfigurable H ardware

Processing Im plem ented inF lex ib le Software

C onfigureSoftware and

H ardwareProcessing

T ransport Layer

Lee 8 E4.

Reconfigurable Architecture

Hardware for NavaTyrr

Analog Devices ADC/DAC evaluation boards, Xilinx Virtex XCV1000 on an Alpha Data PMC card, and Motorola PowerPC

Lee 9 E4.

Hardware Interfaces - Chassis Level

ZX412U6MCP750

cPCI

A/DAC A/DAC

ADM XRC

Power OnlySystem Slot

9

9

PMC

16

EIA-422

Ethernet

Ethernet

Ethernet

OUT

CL

K IND INS OUT

CL

K IND INS


Lee 10 E4.


FPGA to Processor Interface

PowerPCProcessor

Xilinx FP G A

Decode

Tx

Rx

D/A

A/D

8/

8/

testm ux

Clock

AnalogS ignal

Processing

To LogicAnalyzer

Rx Buffer

Tx Buffer

1/

1/

PLX 9080FPGA PCIInterface

Nava Tyrr Chassis

Address 24 bitsData 32 bits

Control

16/


Control


Control

Lee 11 E4.


• Microprocessor: MCP750 with Motorola PowerPC 750 MHz– High MIPS/Watt ratio– Board package support– Driver support– Previous JPL flight experience with PowerPC processor– Radiation tolerant part available

• FPGA: Xilinx Virtex XCV1000 – Ability to partially reconfigure FPGA with support using modular design tools– Immunity to latch ups– Radiation tolerant part available– Usage in another JPL mission: Mars Exploration Rover (MER)

• Interface Card: Alpha Data ADM-XRC– Has a user input/output interface for debugging– PCI Mezzanine Card (PMC) provides ease of use with industry standard

connections

Lee 12 E4.


• RTOS: Integrity from Green Hills Software (GHS)– Hardware memory protection (secure tasks, device drivers, inter-

process communications)– Pre-emptive multi-tasking (true real-time scheduler)– Good vendor support (GHS works with JPL in updating RTOS)– Uses virtual memory– Field upgrade and debugging– Complete front-end and back-end tools from GHS

• Other RTOS considered– Rogue OS (JPL developed)

• Lacks back-end tools and documentation

– VX Works WindRiver • Lacks memory protection and virtual memory

Lee 13 E4.

Design Methodologies

• Very modular and hierarchical designs – Software:

• Object oriented• Fine granularity libraries• Allows for on-board linking

– FPGA (Hardware):• Design path flows from high-level design tools (SPW) to HDL to

configuration files– Lower level designs implemented by tools

• Well tested and documented modular designs (sometimes COTS product)

– Signal processing blocks– Navigation processing blocks– Science processing blocks

Lee 14 E4.

Design Methodologies

• Design Tools: Signal Processing Works (SPW)– High level signal processing design and simulation tool– A commercial standard tool for signal processing and communications

research– Ability to generate Hardware Description Language (HDL)

• Verilog, VHDL, etc. (machine generated code)

• FPGA (Hardware) Tools: Xilinx tools– Foundation ISE, static timing analyzer

• Software Tools: GHS Multi builder– C, C++, embedded C++, Ada 95 optimizing compilers– Event analyzer, RTOS simulator, debugger, and editor

Lee 15 E4.

NavaTyrr Prototype Transceiver

Science Instrumentationand Processing

Application Layer

N etwork Layer

D ata L ink Layer

Physica l Layer

T ransport Layer

Navigation Processing

Lower 3 layers of the OSI are implemented in NavaTyrr.Other layers are commercially available and are used todemonstrate the NavaTyrr.

Lee 16 E4.


• Physical Layer: Digital Baseband Modulator/Demodulator – Demodulator Specifications

• BPSK with NRZ and Manchester pulse waveforms• Data rates: 1kbps to 4 Mbps • 400 kHz to 0.1 Hz loop filter bandwidths (2nd order)• Programmable carrier frequency• For SNR (EB/NO) 0 dB

– Demodulator Basic Building Blocks• Costas Loop (carrier phase recovery for NRZ data)

• Phased Locked Loop (carrier recovery for a tone or Manchester coded data)

• Data Transition Tracking Loop, symbol timing-clock recovery

• Digital Automatic gain control (AGC) to compensate for analog wide band AGC

• Frequency Acquisition using open loop FFT algorithm

• Costas Loop, PLL lock detection with I-Q power estimation

Lee 17 E4.


Physical Layer: Block Diagram of Demodulator

Sum /Dum pFilter

NCO4 MHz

Re

Im

Sum /Dum pFilter

(DTTL)

A \ DAnalog

AGCInput

Left/R ightShift Gain


16 MHz

Costas Loop

| x |

| x |

F(z)

Threshold

R eceiver

| x |

AGC Loop Filter

Lee 18 E4.

Physical Layer: Costas Loop


2nd OrderLoop Filter

23 bitSum /Dum p

Filter

8-bitsin LUT

11/

11/

11/

37/

C ostas Loop

Not used forManchester data

DTTL11/

11/

Clock OutData Out

| x |

| x |23 bit

Sum /Dum pFilter

23 bitSum /Dum p

Filter

11/

11/



32 bitPhase

Accum ulator

8/

8-bitcos LUT G1Coeff

14 bitsNCODeltaPhase

32 bitsG2Coeff26 bits

see fig?

Arm Gain5 bits

Arm Gain?5 bits

Arm Gain?5 bits

B iPhaseLOn

LockPowerI11 bits

LockPowerQ11 bits

CostasOn

Rx

Decode

8/

Dat

aRat

eSte

p14

bits

NC

OD

elta

Pha

se32

bits

NC

OP

hase

Off

set

8 bi

ts

BiP

hase

LOn

1 bi

t

DT

TLO

n1

bit

Cos

tasO

n1

bit

RxR

eset

1 bi

t

DT

TLR

eset

1 bi

t

Cos

tasR

eset

1 bi

t

G2C

oeff

26 b

its

Sym bol Rate

Sym bol Rate

LockDetector

LockDetect

Lee 19 E4.

Physical Layer: DTTL


Sum /Dum pFilter

[0, T/2]z -T/2

-1

+1

21kk aa

Sum /Dum pFilter

[T/2,T]

Sum /Dum pFilter

[T/4, 3T/4]

Sum /Dum pFilter

[3T/4, 5T/4]

11/

11/

z -T/411/

2nd OrderLoop Filter

PhaseAcc.

NCO37/

28/

Tim ingLogic

14/

D TTL

1/

Clocks control Sum /Dum pFilters

11/

For B iPhaseLcoded data only

z -3T/4

W indow size = 0.5

NRZ +BiPhaseL -

NRZ -B iPhaseL +

Data Out

Clock Out

11/

To Costas Loop

1/

1/

Note: Sum /Dum p Filters are norm alized to have Gain = 1. Sum /Dum p Filters have 23 bit resolution.

11/

G1Coeff14 bits

G2Coeff26 bits

Arm Gain

Arm Gain

Arm Gain

Arm Gain5 bits

DataRateStep14 bits

PhaseInit14 bits

T/2delay4 bits

T/4delay4 bits

DTTLon

BiPhaseLOn

BiPhaseLOn

BiPhaseLOn

DTTLReset

Lee 20 E4.


Physical Layer: PerformanceNava Tyrr Transceiver Performance

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

0 2 4 6 8 10 12

Eb/No (dB)

BE

R

Ideal 1000 kbps

Lee 21 E4.


Physical Layer: PerformanceNava Tyrr Costas Loop Performance

(N = 128 samples/symbol)

20.00

25.00

30.00

35.00

40.00

45.00

0 1 2 3 4 5 6 7 8 9 10

ES/N0 (dB)

Lo

op

SN

R (

dB

)

Theory Simulation

Lee 22 E4.


• Data link layer: Proximity-1 protocol– Intended for space communications around Mars

– Specifies physical layer characteristics (frequencies, modulation, channel coding, data rates, and link acquisition procedures)

– Primarily emphasizes point to point connection (expanding Prox-1 to one to many connections is currently being done)

– Specifies a reliable link mode as well as an unreliable link mode

– Full duplex link

– Software controller of the hardware, turning on/off parts of the transceiver when necessary, changing data rates, etc.

Lee 23 E4.


• Data link layer: Proximity-1 protocol (continued)– Software/hardware Attached Synchronization Marker (ASM)

determines frame synchronization

– Hardware buffer in transmitter and receiver• Accommodates high data rates with a relatively low speed software

interrupt

• Sized at 4 kilobytes for the highest data rate

• Software reads one half buffer during interrupt

• Interrupt triggered when buffer pointer reaches half or full

• Implemented using Xilinx circulating dual port RAM

Lee 24 E4.


• Network layer: Ethernet bridge– Acts as driver to interface Proximity-1 packets to data packetized

for higher level protocols, i.e. TCP/IP

– Analogous to a commercial router (but this one will be in space using RF links

• Upper layers of OSI:– Other layers beyond TCP/IP already implemented by commercial

plug and play software

– Application layer: Apple’s QuickTime

Lee 25 E4.


USO

refxmt rcv xmtrcv

USO

ref

Play MP3s

LAN

LAN

Full-Duplex Communications Demonstration Features

• Digital Carrier @ Baseband• BPSK Modulation of Proximity-1 Framed “Data”• Convolutional Coding• Digital-to-Analog Conversion •••• Analog-to-Digital Conversion• Carrier Tracking• Symbol Tracking• Viterbi Decoding• Extraction of “Data” from Proximity-1 Frames

Reconfigurable Transceiver Components

• PowerPC 750 + Xilinx Virtex V1000 FPGA• Analog Devices ADC & DAC components• C++ and Verilog Software Modules

Spacecraft One

• Encodes/Streams Video

Spacecraft Two

• Decode & Play Video

Lee 26 E4.


• Preliminary performance:– Effective data rate

• 90% of actual data rate from Proximity-1

• 50% of actual data rate from Ethernet bridge and Proximity-1 overhead

– Network latency• High

• Buffer implementation not optimal for sending acknowledgements and retransmissions

• Future implementation of buffer will decrease network latency

Lee 27 E4.


• Reconfigurability demonstrated– Full reconfiguration using microprocessor

• At any given time, we can load any configuration file into the FPGA using the processor

• Scrubbing reprograms the entire FPGA to ensure that no portion of the chip has been corrupted by radiation or other effects

– Partial reconfiguration for testing radiation mitigation effects• We manually corrupted the FPGA by partially reconfiguring a small

part of the FPGA to simulate radiation effects

– Partial reconfigurable design• Currently working on

Lee 28 E4.

Space Applications

• Space Technology 5’s (ST-5) Constellation Communications Transceiver (CCNT) in ‘03– Dynamic downloads

• different modes of operation will involve downloading a different entire FPGA configuration file

– Similar hardware platform (uses flight qualified evolution of the NavaTyrr commercial hardware)

• Atmel-Grenoble PPC750 (CGA package)

• Xilinx XQRV 1000 rad-tolerant (CGA package)

• RS-422 interfaces instead of Ethernet

• StarLight’s Autonomous Formation Flyer (AFF) in ‘06– Similar to CCNT

Lee 29 E4.

Future Development

• Space Reconfiguration• Memory storage• Complete file upload

• Reliability• Large-Scale Partial Reconfiguration

– Multiple channels with different modulation and coding schemes

• More complex networks– Multi-User Network prototype

• Multiple channels operating in each processor• Develop laboratory prototype with larger number of nodes

– More complex protocols • Improved Proximity-1

Lee 30 E4.

Summary

• Software Reconfigurable Paradigm– Long life

– Providing greatly improved science instrumentation and

processing capabilities – rapid prototyping and rapid development

• Reconfigurable Architecture– FPGA– RISC processor– RTOS

• Design Methodologies– High level, modular, hierarchical designs– Tools create lower level designs

e4.lee1 software/hardware reconfigurable network processor for space networks clement lee andrew...

Documents

processor interface

changes slide

motorola powerpc slide

yong chong slide

computer processor

space missions

spacebased applications

space applications description