dsps in wireless communication systems
DESCRIPTION
DSPs in Wireless Communication Systems. Vishwas Sundaramurthy {[email protected]} Electrical and Computer Engineering Department, Rice University, Houston,TX. Organization. What are DSPs? Comparison with other processors DSPs in Wireless communications Prototyping using DSPs - PowerPoint PPT PresentationTRANSCRIPT
DSPs in Wireless Communication Systems
Vishwas Sundaramurthy
Electrical and Computer Engineering Department,
Rice University, Houston,TX.
Organization
•What are DSPs? –Comparison with other processors
•DSPs in Wireless communications
•Prototyping using DSPs–use of DSP boards
•Fixed point analysis
•We use DSPs for …
What are DSPs?
Digital Signal Processors
Optimized for signal processing
Work on a stream of data from the external world– “Real-Time” operation
Power efficient
Low cost
Why DSPs?
Digital signal processors Vs. Analog components
– No variation in behavior with external factors
– Easy duplication of specifications
– Flexibility in setting parameters
DSPs Vs. general purpose processors
Harvard Architecture Von Neumann Architecture
Processor Core
Memory
Address Bus
Data Bus
Processor Core
Memory - A
Address Buses
Data Buses
Memory - B
MAC - Multiply Accumulate
X +
Single cycle multiply
Faster clock speeds
Expensive
Use of MACs
X
+
D D D
+ +
X XX
Eg. - FIR filter
DSPs Vs. GPPs
Data flow
– Real time
Program “flow”
Data In Data OutDSP
Section - A
Function - B
Section - C
Simpler Programming
– High level languages
Flexibility to programmer
–
Coding in “C”
–
Optimization in assembly
Fixed point versions
Cool! Hot!
Application Areas in Wireless Communication Systems
Digital cellular phones
Cellular base stations
Wireless data applications
Wireless local loops
Cordless phones
Pagers
GPS systems
A Cellular Handset
TRANSMITTER
RECEIVER
Switch
RF section A/D conv. Baseband section
Detection
Channel Decoding
Channel Coding
Spreading
Modulation
Source decoding
Source Coding
RF Amplification
&De/Modulation
A to D
D to A
DSP
Demodulation
Speaker
Mic.
A Cellular Base-station
SOURCE CODING
CHANNEL CODING
SPREADING
TRANSMITTERK users
Noise
MULTIUSER RECEIVER
DECODER DETECTOR DEMODULATION
CHANNEL ESTIMATOR
(RF)
A/D
SWITCHINGDSPs
DSPs
MODULATION
(RF)
System-on-a-chip Solutions
Viterbi decoder
demodulatorand
synchronization
keypadinterface
protocol
control
de- interleaver
speechdecoder
voicerecognition DSP
core
P coreRAM
&
ROM
Other logic
A
D
downconversion
Analog
C - CODE
Algorithm Implemented using C - CODE
MATLAB Compiler
Algorithm Implemented as a MATLAB program
C-code generator
Algorithm implemented using a block diagram tool (SIMULINK)
C - CODE
DSP CODE GENERATION TOOLS
C - Compiler
Assembler
Linker
C - CODE
ASM-CODE MACHINE LANGUAGE
DSP EXECUTABLE
DOWNLOADED TO DSP
DSP
DEBUGGER
DSP Algorithm to be implemented
Algorithm development: high-level evaluation to DSP implementation
Design flow for ASIC implementation
COSSAP/SPW based analysis
Fixed point analysis of blocks
VHDL DSP function library
VHDL description and simulation : Eg. Mentor Graphics' ModelSim
VLSI design tools: area estimate : Eg. Synopsis' Design Compiler
Example: Adaptive Filtering Algorithms
Interference cancellation in the synchronous downlink by channel equalization
x(i)x(i+F) x(i-F)
AN-1 AN-2 A1 A1* AN-2
* AN-1*
x(i+1)
x(i-1)
z(i)
...
Discretize
Update Coefficients
Compare
TrainingSequence
r(t)
...
Chip-matched filter
Griffith's Chip Estimator
)()()( iii nuHr
)()()(ˆ H iiiu rw
)(ˆ)()()()()1( * iuiiiii u rCww r
)(ˆ)()()()()1( *0
2 iuiiiii u rhww
Received downlink signal model:
Griffith's chip estimator
Correlator
Channel impulse response
r : received signal
H : channel and pulse shaping
filter
response
u : signal elements
n : noise
Estimate for u(i) (filter output):
Adaptive filter coefficients
)(00100)()()(E)( 02T2 iiiuii uuu hHrCr with
Filter coefficient (without preamble)
LMS-filter VHDL Model
T y p e U n i t O r D e p a r t m e n t H e r eT y p e Y o u r N a m e H e r e
y kX
kT W
k=
Wk 1+
Wk 2
kX
k+=
Filter Output:
Filter coefficients update:
Wk: filter weight vector
: gain constant,
k dkyk: the error,
Xk : the input sample vector
dk : the desired response.
Z-1
xk Z
-1Z
-1...
w0kk wLkkw1kk
+ + yk
...
Reference system
Downlink simulations in COSSAP
Bit Source
Channel Encoding
InterleavingAdd Pilot
Interfering users
Base station transmitter
(spreading and scrambling)
3-path Raleigh fading
channel
AWGN
Chip-matched
filter
Griffith's chip
estimator
Channel estimate
De-spreading
De-interleaving
Decoding
Statistics
Fixed-point Analysis
COSSAP based simulation analysis Fixed-point version of of the Adaptive filter only
Cossap block diagramCossap block diagram
Floating-point to integer
integer to Floating-point
Griffith'sAlgorithm
(integer)
Fixed-point Scaling
ALU-1
MAC
Coefficient Update
Coefficient Update
ALU-2Filter
updateFilter
update
X_i, X_q(^28 )
W_I, W_q(^214) Fil_i, Fil_q
(^222 )
Downscale(v 228)
W(+)_i, W(+)_q(^242 )
Downscale (v 26)
(^216 )
X
Step-Size (^ 218)
(^224 )
Fixed-point Scaling
Observed signal range: chip matched filter output : –50 to +50 channel coefficients: -0.5 to 0.5
Fixed-point scalings
Signal Float-Pt. Range Scaling Integer Range
Baseband input
(Chip Matched Filter output)
-27 to 27 28 –215 to 215
Channel coefficients -20 to 20 28 –28 to 28
Adaptive Filter Coefficients
(Weights)
-2-6 to 2-6 214 –28 to 28
Step Size ~2-15 218 ~23
Filter Output -20 to 20 216 216
ALU width: 32 bit precision
16 bits
9 bits
9 bits
17 bits
Signal widths
Signal Port widthBaseband input (or chip matched filter output) 16 bitsChannel coefficients 9 bitsAdaptive Filter Coefficients (Weights) 9 bitsStep Size 8 bitsFilter Output 16 bitsALU width 32 bit precision
TI TMS320C6201 Development System
VLIW Architecture 1600 MIPS Peak 256 KB SRAM 8 MB DRAM PCI Interface
TI TMS320C6X architecture
Wideband W-CDMA Simulation Testbed
Develop an integrated software testbed
Unified framework to evaluate new
algorithms for coding, synchronization,
detection, etc.
Hardware/Software Co-Design
Simulink, Matlab, “C”
Simulation Acceleration
What we do with DSPs...
CDMA Wireless Link
SOURCE CODING
CHANNEL CODING
SPREADING MODULATION
TRANSMITTER
RECEIVER
Detected bits of K users
User’s data bits
K users
DECODER DETECTOR DEMODULATION
CHANNEL ESTIMATOR
Noise
Wireless ChannelUser_Data
Show StatsUpdate Parameters
Decorrelating Detector
Multiuser Detector
Error Counter
Chip MF
Max. Likelihood Channel Est.
Channel Estimation
CDMA Wireless System Testbed Simulink Version
Parameters
Multiuser Detection
Channel Estimation
AWGN Channel
User Data
Error Rate Calculation
Statistics
Chip matched filter
Prototyping Methodology
Display and
Analysis of Data
Simulink
C - Code Matlab CodeBlock Diagram
Libraries Algorithms
With RTW
support for
DSP hardware
Workstation
DSP hardwareDSP Code Generation Tools
RTW generated C -
Code
Current Infrastructure
400MHz Pentium PC host Two TI TMS320C6201 DSP
Development Boards (EVMs)
Optimizing “C” compiler and code generation tools
MS Visual Studio development environment
Future Environment
• PCI TIM (TI C40 Module) carrier
• C62/C67 DSP TIMs
• Xilinx Virtex FPGA module
Summary
What are DSPs? + Special features
Issues in algorithm development on DSP boards
– Prototyping
– Fixed Point Analysis
DSPs in Wireless communications
– DSPs in the wireless testbed project