DSP PROCESSORSTMS320C5X

Introduction to DSP Comparison of DSP with normal DSPTypes of architectureVon-NeumannHarvardModified Harvard

PROGRAM MEMORY ADDRESSPROGRAM MEMORY DATADATA MEMORY ADDRESSDATA MEMORY DATA

Modified Harvard

Dedicated MAC unit

Comparison of DSP and general purpose processor

DSP ProcessorGeneral purpose processorInstruction are executed in a single cycleMultiple clock cycles are requiredParallel executionSerial execution Separate program and data memory No separate memory Program and data memory are on chip Off chip program and data memory Queuing is implicit Queuing is explicit Address are generated combine Program counter is incremented sequentially Three separate computational units ALU, MAC and shifter ALU is the main computational unit

Features of TMS320C5X processor

DRAM CELL

SRAM CELL

SRAM CELLS

APPLICATIONS Avionics and defense

Video encoding and decoding

biometrics

TMS320C5X

Architecture of TMS320C5X

TMS320C54X architecture

Instruction setsLoad store InstructionsLST: load data value to ST0/ST1SST: store ST0/ST1 in data memory locationLMMR AR0,#1500h: contents of AR0 are loaded to data memory location of 1500hLACC: load data memory value with left shift to the accumulatorLAMM: Load contents of memory mapped register to accumulator.

Addition/subtraction instructionADD #1278h: the instruction adds 1278h to the accumulatorADD#1278h,2: the value 1278h is shifted by 2 positions and added to the accumulator.SUBB 55H,2: Accumulator is subtracted with the content of data memory with dma 55h after shifting by 2 positions left.