dsp processors (gowri modified).pptx
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DSP ProcessorsUNIT-V
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Figure 4.1(a) The 4x4 binary muli!licaion
"uli!lier
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Figure 4.1(b) The srucure o# a 4x4 $raun muli!lier
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"%& using DSP
&lr % '&lear %ccumulaor %
e! N ' e! N imes he ne insrucion
"%& *(+), *(1), % ' Fech he o memory locaions !oine/ by1 muli!ly hem ogeher an/ a// he resu0nal resul is sore/ bac in %
"o2 % *3 ' "o2e resul o memory
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Figure 4.4 % "%& uni
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Figure 4.7 % "%& uni ibis
In numerical analysis one or more guard digits can be use/ ore/uce he amoun o# roun/o9 error.
For eam!le su!!ose ha he 0nal resul o# a long muli-se!calculaion can be sa#ely roun/e/ o9 o N /ecimal !laces. Tha is osay he roun/o9 error inro/uce/ by his 0nal roun/o9 maes anegligible conribuion o he o2erall uncerainy.
:oe2er i is ;uie liely ha i is not sa#e o roun/ o9 heinerme/iae se!s in he calculaion o he same number o# /igis.$e aare ha roun/o9 errors can accumulae. I# M/ecimal !lacesare use/ in he inerme/iae calculaion e say hereare M−N guar/ /igis.<uar/ /igis are also use/ in =oaing !oin o!eraions in mos
com!uer sysems.
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Figure 4.>(a) The bus srucure o# 2on Neum
archiecure(The bus structure of von Nearchitecture (Related matter from ramedition page no 11.8) matter from raedition also there
Von Neumann archiecure
The von Neumann architecture also non as he von Neumann model architecture is a com!uer archiecure base/ on ha /escribe/ in 1647 by mahemaician an/ !hysicis ?ohn 2on Neumann an/ ohers.
The /esign o# a 2on Neumann archiecure is sim!ler han he more mo/ern
:ar2ar/ archiecure hich is also a sore/-!rogram sysem bu has one /e/ica//ress an/ /aa buses #or rea/ing /aa #rom an/ riing /aa o memory an
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Figure 4.>(b) The bus srucure o# :ar2ar/ archiecure((R
matter from ramesh babu 5
th
edition page no 11matter from ramesh babu 4th edition also ther
:ar2ar/ archiecure
The !arvard architecture is a com!uer archiecure ih !hysically sesorage an/ signal !ahays #or insrucions an/ /aa. The erm originae:ar2ar/ "ar I relay-base/ com!uer hich sore/ insrucions on !unchbis i/e) an/ /aa in elecro-mechanical couners. These early machinessorage enirely conaine/ ihin hecenral !rocessing uni an/ !ro2i/e/o he insrucion sorage as /aa. Programs nee/e/ o be loa/e/ by an o!rocessor coul/ no iniiali@e isel#.
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• "ontrast #ith von Neumann architectures
Un/er !ure 2on Neumann archiecure he &PU can be eiher rea/inginsrucion or rea/ingAriing /aa #romAo he memory. $oh canno osame ime since he insrucions an/ /aa use he same bus sysem.
com!uer using he :ar2ar/ archiecure he &PU can boh rea/ an ian/ !er#orm a /aa memory access a he same imee2en ihou a
% :ar2ar/ archiecure com!uer can hus be #aser #or a gi2en circuicom!leiy because insrucion #eches an/ /aa access /o no conesingle memory !ahay.
%lso a :ar2ar/ archiecure machine has /isinc co/e an/ /aa a//insrucion a//ress @ero is no he same as /aa a//ress @ero. Insruca//ress @ero migh i/eni#y a eny-#our bi 2alue hile /aa a//re
migh in/icae an eigh-bi bye ha is no !ar o# ha eny-#our b
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Figure 4.>(c) The bus srucure #or he archiecure ih one !rogramemory an/ o /aa memories
% mo/i0e/ :ar2ar/ archiecure machine is 2erymuch lie a :ar2ar/ archiecure machine bu irelaes he sric se!araion beeen insrucionan/ /aa hile sill leing he &PU concurrenly
access t#o (or more) memor$ buses. The mos
common mo/i0caion inclu/es se!arae insrucionan/ /aa caches bace/ by a common a//resss!ace. Chile he &PU eecues #rom cache i acsas a !ure :ar2ar/ machine. Chen accessingbacing memory i acs lie a 2on Neumannmachine (here co/e can be mo2e/ aroun/ lie/aa hich is a !oer#ul echni;ue). Thismo/i0caion is i/es!rea/ in mo/ern !rocessors
such as he %" archiecure an/ > !rocessors.I is someimes loosely calle/ a :ar2ar/archiecure o2erlooing he #ac ha i is acuallyEmo/i0e/.
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<PP (%eneral Purpose Processor) G Daa PahHnly
"emory Daa$us
%U
egiser 1"emory egiser
Same memory #or !rogram an//aa
% <PP unlie a Single Pur!oseProcessor can accom!lish 2ariousass 2ia !rograms rien in anInsrucion Se ha he
micro!rocessor can recogni@e."os !rocessors are buil #rom aconroller /aa!ah an/ memory
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Digial Signal Processors G Daa Pah Hnly
• % DSP &hi! is amicro!rocessor s!ecially/esigne/ #or DSPa!!licaions
• :ar2ar/ archiecure allosmuli!le memory rea/s
• %rchiecure o!imi@e/ o!ro2i/e ra!i/ !rocessing o#/iscree ime signals e.g."uli!ly an/ %ccumulae("%&) in one cycle
Program "emory Daa$us
%U
%ccumulaor
Program"emory
Daa"emory
"uli!leer
"uli!ler
Daa "emory Daa$us
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"emory srucures
PIPJININ<
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PIPJININ< B
Pi!elining is a echni;ue hich #ollos o or more o!eraions oo2erla! /uring eecuion.In !i!elining a as is broen /on ino a number o# /isincsubass hich are hen o2erla!!e/ /uring eecuion. I is use/eensi2ely in /igial signal !rocessors o increase s!ee/.
%n insrucion can be broen /on ino hree se!s. Jach se! inhe insrucion can be regar/e/ as a sage in a !i!eline an/ so canbe o2erla!!e/. $y o2erla!!ing he insrucions a ne insrucion issare/ a he sar o# each cloc cycle.
The 0gure shos he iming /iagram #or a hree-sage !i!eline /ran o highligh he insrucion se!s. Ty!ically each se! in he!i!eline aes one machine cycle. Thus /uring a gi2en cycle u! ohree /i9eren insrucions may be aci2e a he same ime alhough each ill be a he /i9eren sage o# com!leion. The ey o an insrucion !i!eline is ha hree !ars o# heinsrucion (ha is #ech /eco/e an/ eecue) are in/e!en/en an/so he eecuion o# muli!le insrucions can be o2erla!!e/.
I is seen ha a he ih cycle he !rocessor coul/ besimulaneously #eching he ih insrucion /eco/ing he (i-1)h
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Figure 4.1 Pi!elining #or s!ee/ing u! he eecuion o# an insruci
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Ty!es o# DSP
• o Jn/ &i'ed Point• T"S3+&355 %DSP3155 DSP7555
• :igh Jn/ &i'ed Point• T"S3+&7755 DSP1555
• %DSP31755 DSP7>++
• Floaing Poin• T"S3+&5 &K55 %DSP31+55 DSP6+++
DSP355
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Figure .1(a) Fie/-!oin #orma o re!resen signe/ inegers
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Figure .1(b) Fie/-!oin #orma o re!resen signe/ #racions
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Figure .3 IJJJ K74 #orma #or =oaing-!oin numbers
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Figure . (a) %n %AD con2erer ih b bis #or signal re!resenaio(b) ;uani@aion mo/el #or he %AD con2erer
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Figure . (c) ;uani@aion error in runcaion %AD con2erer
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Figure . (/) ;uani@aion error in roun/ing %AD con2erer (e!robabiliy /ensiy #uncion #or runcaion error (#) !robabiliy
/ensiy #uncion #or roun/ing error
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Figure .4 %n eam!le shoing he DA% con2erer error /ue o he@ero-or/er hol/ a is ou!uB (a) DSP ou!u (b) DA% ou!u
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Figure .4 %n eam!le shoing he DA% con2erer error /ue o he@ero-or/er hol/ a is ou!uB (c) he con2ol2ing !ulse ha genera
(b) #rom (a) (/) #re;uency conens o# he con2ol2ing !ulse in (c)
Fie/ Poin Vs Floaing
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Fie/ Poin Vs FloaingPoin• Fie/ PoinAFloaing Poin
• 0e/ !oin !rocessor are B
• chea!er• smaller• less !oer consuming• :ar/er o !rogram
• Cach #or errorsB runcaion o2er=o roun/ing
• imie/ /ynamic range• Use/ in 67L o# consumer !ro/ucs
• =oaing !oin !rocessors
• ha2e larger accuracy• are much easier o !rogram• can access larger memory
• I is har/er o creae an eMcien !rogram in & on a 0e/!oin !rocessors han on =oaing !oin !rocessors
Fie/ Poin Vs Floaing
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Fie/ Poin Vs FloaingPoin
Floaing Poin Fie/ Poin
%!!licaions
"o/ems
Digial Subscriber ine (DS)
Cireless $asesaions
&enral HMce Siches
Pri2ae $ranch Jchange (P$5)
Digial Imaging
D <ra!hics
S!eech ecogniion
Voice o2er IP
%!!licaions
Porable Pro/ucs
3< 3.7< an/ < &ell Phones
Digial %u/io Players
Digial Sill &ameras
Jlecronic $oos
Voice ecogniion
<PS ecei2ers
:ea/ses
$iomerics
Finger!rin ecogniion