draft – work in progress - not for publication 13 july 2005 pids preliminary results and key...

DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

PIDS Preliminary Results and Key Issues: 2005 ITRS

Peter M. Zeitzoff for PIDS Technology Working Group

ITRS Public MeetingSan FranciscoJuly 13, 2005


PIDS RosterJapan•T. Sugii (Chair)•S. Sawada•J. Ida•S. Oda•T. Hiramoto•S. Takagi•K. Shibahara•A. Hori•D. Hisamoto•T. Nakamura•Y. Tadaki•N. Nagashima•Y. Takeda•S. Tahara•K. Imai•Y. Akasaka•R. Shirota•M. Yoshimi•T. Sasaki

Taiwan•R. Liu (Chair)•Y. J. Mii•C. Diaz•W. T. Shiau•M. J. Tsai

Korea•I. S. Yeo

Europe•T. Skotnicki (Chair)•K. Schruefer•S DeLeonibus•K. De Meyer•R. Lander•M. Jurczak

US•P. Zeitzoff (Chair)•J. Chung•J. Brewer•L. Tran•M. Rodder•Q. Xiang•T-J. King•T. Ning•G. Yeap•M. Duane•T. Dellin•W. Tsai


Outline

• Scope and Subcategories

• Non-Volatile Memory

• DRAM

• Logic

• Reliability


PIDS Scope• PIDS = Process Integration,

Devices, and Structures• Main concerns

– MOSFET, memory, and passive devices and structures• Device physical and electrical characteristics

and requirements– Broad issues of device and circuit

performance, density, and power dissipation, particularly as they drive overall technology requirements

– Reliability


PIDS Subcategories

• Logic

– High-performance

– Low-power for mobile applications

• Memory

– DRAM

– Non-volatile memory (NVM)

• Reliability


Outline



• DRAM

• Logic

• Reliability


• NOR Flash– Technology node (F = minimum poly half pitch) remains unchanged

from 2004 update.– Tunnel oxide scaling slightly faster in near term.– Interpoly EOT scaling faster in both near term and long term

(deployment of high-k).– Control gate Lg scaling is considerably faster than 2004 update.– Cell size scaling is faster than 2004 update in both μm2 and F2.– Advances result from good engineering, not fundamental

breakthroughs.• NAND Flash

– F moves past DRAM in both near term and long term.– Cell size area factor, a = cell size/F2 remains the same (but F moves

with node).– W/E voltages remain the same as 2004 update (not moving with

node).– Tunnel oxide thickness remains the same as 2004 update.– Interpoly dielectric thickness remains the same as 2004 update.– Endurance and retention remain the same as 2004 update.

Non-Volatile Memory (NVM)

Preliminary Results


Long-term

Near-term

2004 2005 2006 2007 2008 2009

04 NAND/AND Flash 90 70 65 55 50 45

03Flash Roadmap 90 80 70 65 55 5003DRAM1/2pitch 90 80 70 65 57 50

2010 2011 2012 2013 2014 201504 NAND/AND Flash 45 40 35 32 28 25

03Flash Roadmap 50 39 35 2803DRAM1/2pitch 45 35 32 25

Technology Node(nm)

Proposal of NAND/AND Flash Roadmap

Preliminary Results


• FeRAM– Technology node still lags substantially behind DRAM/NAND Flash– Ferroelectric capacitor area scaling slows down – 3D is major challenge– Endurance improvement slows down starting from 2004.

• SONOS/NROM– 2-bit/cell due to localized charge storage.– Scalability expected similar to floating gate device.– No floating gate coupling issues.

• MRAM– Technology node pulls back by 1-2 years in near term and long term.– Both switching field and switching energy are aggressively scaled after 2008

compared to 2004 update. Much of this acceleration is labeled “red” indicating breakthroughs are needed for MRAM to stay competitive.

• PCRAM– New in 2005 PIDS: mainstream production expected soon.– For near term years, technology node similar to DRAM.

Non-Volatile Memory (NVM) (con’t.)

Preliminary Results


Outline



• DRAM

• Logic

• Reliability


• Scaling unchanged from 2003– DRAM half-pitch (F) : 3 year cycle

• 65nm in 2007, 45 nm in 2010

• Other results– a=(cell area)/F2: a=8 through 2007, a=6

thereafter

– Area size factor (% of chip area taken up by storage cells): 63% through 2007, 56% thereafter

– STC storage node dielectric: the same as 2003 ITRS

DRAM

Preliminary Results


First Year of IC Production200580nm

200670nm

200765nm

200855nm

200950nm

201045

2011 201235nm

201332

2014 201525nm

201622

2017 201818nm

2019 2020

DRAMsHigh-k dielectric Al2O3 & Ta2O5, MIS structure (k ~ 10–25) MIM Structures (k ~ 20–50) BST or other materials (k>100)

Three dimensional array device

Emerging research memory devices

Potential Solutions: DRAM

Preliminary Results


Scaling of DRAM Storage Dielectric

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

2005 2010 2015 2020

0

5

10

15

20

25

30

35

40

45

50

DRAM storage node celldielectric: equivalent physicalthickness, EOT nm

DRAM storage node capacitorvoltage, V

Electricfield of capacitordielectric, MV/cm

Preliminary Results


Outline



• DRAM

• Logic

• Reliability


Logic: 2005 Scaling Approach and Categories• MASTAR (detailed analytic device model from STM and

corporate partners) was used – MASTAR has been extensively verified against literature and other

data

– Initial choice of scaled MOSFET parameters is made

– Using MASTAR, MOSFET parameters are iteratively varied to meet ITRS targets

• Types of Logic– High Performance (HP) (e.g., MPU): target is historical 17%/year

transistor performance increase

– Low Power (for mobile applications): target is specific, low level of leakage current

• Low Standby Power (LSTP): very low leakage; for lower performance, consumer applications (e.g., cellphone)

• Low Operating Power (LOP): low dynamic power, rel. high performance (e.g., notebook computer)

• 2005 scaling results changed somewhat from 2003 ITRS


Intrinsic Transistor Delay, CV/I

(lower delay = higher speed)

Leakage Current(HP: standby power dissipation issues)

2005 ITRS: Low Power & High Performance (HP)

Preliminary Results

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

2005 2007 2009 2011 2013 2015 2017 2019

Calendar year

Isd

,lea

k (

uA

/um

)

HP Target:17%/yr, historical rate

LOP LSTP

LSTP Target: Isd,leak ~ 10 pA/um

LOP

HP


The “CMOS Change Crunch” Multiple, Big Changes Over Next 7 Years

2000 2005 2010 2015 2020First Year of “Volume Production”

High k Gate Dielectric HPLP

LPHP = High Performance Applications

= Low Power Applications

Driver:

Others

Fully Depleted SOI HP LP

Multiple Gate MOSFET HP LP

HPStrained Si LP

Preliminary Results

HPMetal Gate Electrode

LP


LSTP: EOT and Gate Leakage Current Density (Jg) Scaling

Preliminary Results

Jg,sim (SiON)

EOT

Jg,limit


Parallel Paths for High-Performance Logic in 2005 ITRS

Preliminary Results

Year in Production Units 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020Number of years from 2005 years 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15Technology Generation hp65 hp45 hp32 hp22 hp16

Physical Lgate (High Performance) nm 32 28 25 22 20 18 16 14 13 11 10 9 8 7 6 5

MG

Planar Bulk

FDSOI[MG = Multiple Gate (e.g., FinFET)]

•Approach

–Extend planar bulk as long as possible

–Implement FDSOI in parallel with planar bulk

–Establish MG later; MG is the ultimate, scaled CMOS

[FDSOI = Fully Depleted, Ultra-thin Body SOI]


Outline



• DRAM

• Logic

• Reliability


• High-k Gate Dielectrics– Dielectric breakdown; Transistor instability

• Metal Gate– Ion drift, VTH stability, oxidation; thermal-

mechanical• Cu/ Low k

– Electromigration and voiding; stability of interfaces; TDDB

– Impact of porous, weaker, less thermally conductive dielectrics

• Packaging– Solder bumps; fracture; EM in packaging; CTE

mismatch• Design & Test for Reliability

– Reliability simulation; Reliability screens

Reliability: Top 5 Near-Term Challenges

Preliminary Results


• Reliability risk is growing– New materials (e.g., high k/metal gate; low k) and new

devices (e.g., FINFET) and new packaging• Introduce new and/or modified failure mechanisms• Mechanisms need to be identified, modeled and controlled• Have less-than-historic time and resources to ensure

reliability– Difficult tradeoffs may require reduced reliability

margins– Need new Design for Reliability tools and reliability

screens• Need to sustain current high reliability levels in

spite of unprecedented changes

Reliability: Key 2005 Issues

Preliminary Results


• Memory– DRAM: Rapid scaling continuing– Numerous different types of NVM, with unique attributes

and scaling scenarios• Logic

– High-performance logic: performance increases by 17%/yr. ratehigh leakage current

– Low-power logic: low leakage currentreduced performance

– Numerous and rapid technology innovations required– 2005 ITRS: re-evaluation of scaling scenarios, timing and

sequence of technology innovations• Reliability

– Ensuring reliability for numerous and rapid technological innovations is a critical challenge

– Nevertheless, need to sustain current high reliability levels

Summary


BACK UP


Parallel Paths for LSTP in 2005 ITRS

Preliminary Results

[MG = Multiple Gate (e.g., FinFET)]

•Approach


–Implement FDSOI and MG in parallel

–Slowed Lg scaling for FDSOI in latter years



Parallel Paths for LOP in 2005 ITRS

Preliminary Results

[MG = Multiple Gate (e.g., FinFET)]

•Approach


–Implement FDSOI and MG in parallel

–FDSOI ends in 2016


draft – work in progress - not for publication 13 july 2005 pids preliminary results and key...

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