Sound Effect Generator Flash MCU
HT45F2020/HT45F2022
Revision: V1.00 Date: April 11, 2017
Rev. 1.00 2 April 11, 2017 Rev. 1.00 3 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Table of Contents
Features ................................................................................................................ 5CPU Features ..............................................................................................................................5Peripheral Features ......................................................................................................................5
General Description ............................................................................................. 6Selection Table ..................................................................................................... 6Block Diagram ...................................................................................................... 7Pin Assignment .................................................................................................... 7Pin Description .................................................................................................... 8Absolute Maximum Ratings ................................................................................ 9D.C. Characteristics ............................................................................................. 9A.C. Characteristics ........................................................................................... 10Shunt Regulator Electrical Characteristics – for HT45F2020 only ................ 11Power-on Reset Characteristics ....................................................................... 12System Architecture .......................................................................................... 12
Clocking and Pipelining ..............................................................................................................12Program Counter ........................................................................................................................13Stack ..........................................................................................................................................14Arithmetic and Logic Unit – ALU ................................................................................................14
Flash Program Memory ..................................................................................... 15Structure .....................................................................................................................................15Special Vectors ..........................................................................................................................15Look-up Table .............................................................................................................................15Table Program Example .............................................................................................................16In Circuit Programming – ICP ....................................................................................................17On-Chip Debug Support – OCDS ..............................................................................................18
Data Memory ...................................................................................................... 18Structure .....................................................................................................................................18General Purpose Data Memory .................................................................................................18Special Purpose Data Memory ..................................................................................................19
Special Function Register Description ............................................................ 20Indirect Addressing Registers – IAR0, IAR1 ..............................................................................20Memory Pointers – MP0, MP1 ...................................................................................................20Accumulator – ACC ....................................................................................................................21Program Counter Low Register – PCL .......................................................................................21Look-up Table Registers – TBLP, TBLH .....................................................................................21Status Register – STATUS .........................................................................................................21
Oscillators .......................................................................................................... 23Oscillator Overview ....................................................................................................................23System Clock Configurations ....................................................................................................23
Rev. 1.00 2 April 11, 2017 Rev. 1.00 3 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
High Speed Internal RC Oscillator – HIRC ...............................................................................24Internal 32kHz Oscillator – LIRC ...............................................................................................24Supplementary Oscillators ........................................................................................................24
Operating Modes and System Clocks ............................................................ 24System Clocks ..........................................................................................................................24System Operation Modes ...........................................................................................................25Control Register .........................................................................................................................27Operating Mode Switching ........................................................................................................28Standby Current Considerations ...............................................................................................32Wake-up .....................................................................................................................................32
Watchdog Timer ................................................................................................. 33Watchdog Timer Clock Source ...................................................................................................33Watchdog Timer Control Register ..............................................................................................33Watchdog Timer Operation ........................................................................................................34
Reset and Initialisation ...................................................................................... 35Reset Functions .........................................................................................................................35Reset Initial Conditions .............................................................................................................36
Input/Output Ports ............................................................................................ 38Pull-high Resistors .....................................................................................................................38Port A Wake-up ..........................................................................................................................39I/O Port Control Registers ..........................................................................................................39Pin-shared Functions .................................................................................................................40I/O Pin Structures .......................................................................................................................41Programming Considerations ....................................................................................................41
Timer Modules – TM .......................................................................................... 42Introduction ................................................................................................................................42TM Operation .............................................................................................................................42TM Clock Source ........................................................................................................................42TM Interrupts ..............................................................................................................................42TM External Pins .......................................................................................................................43TM Input/Output Pin Selection ...................................................................................................43Programming Considerations .....................................................................................................44
Periodic Type TM – PTM .................................................................................... 45Periodic TM Operation ...............................................................................................................45Periodic Type TM Register Description ......................................................................................46Periodic Type TM Operation Modes ...........................................................................................50
Shunt Regulator – for HT45F2020 only ............................................................ 59Sound Effect Generator .................................................................................... 60Interrupts ............................................................................................................ 60
Interrupt Registers ......................................................................................................................60Interrupt Operation .....................................................................................................................62Multi-function Interrupt ...............................................................................................................63
Rev. 1.00 4 April 11, 2017 Rev. 1.00 5 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Time Base Interrupt ....................................................................................................................63Timer Module Interrupts ............................................................................................................64Interrupt Wake-up Function ........................................................................................................64Programming Considerations .....................................................................................................64
Application Circuits ........................................................................................... 65Instruction Set .................................................................................................... 69
Introduction ................................................................................................................................69Instruction Timing .......................................................................................................................69Moving and Transferring Data ....................................................................................................69Arithmetic Operations .................................................................................................................69Logical and Rotate Operation ....................................................................................................70Branches and Control Transfer ..................................................................................................70Bit Operations ............................................................................................................................70Table Read Operations ..............................................................................................................70Other Operations ........................................................................................................................70
Instruction Set Summary .................................................................................. 71Table Conventions ......................................................................................................................71
Instruction Definition ......................................................................................... 73Package Information ......................................................................................... 82
8-pin SOP (150mil) Outline Dimensions ....................................................................................836-pin SOT23-6 Outline Dimensions ...........................................................................................84
Rev. 1.00 4 April 11, 2017 Rev. 1.00 5 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Features
CPU Features• PowerSupplyinputvoltage
♦ HT45F2020:8V~16V♦ HT45F2022:2.2V~5.5V
• Internalshuntregulatoroutput:5V–HT45F2020only
• Operatingvoltage♦ fSYS=8MHz:2.2V~5.5V
• Upto0.5μsinstructioncyclewith8MHzsystemclockatVDD=5V
• Powerdownandwake-upfunctionstoreducepowerconsumption
• Oscillators♦ InternalHighSpeedRC–HIRC♦ Internal32kHzRC–LIRC
• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP
• Fullyintegratedinternal8MHzoscillatorrequiresnoexternalcomponents
• Allinstructionsexecutedinoneortwoinstructioncycles
• Tablereadinstructions
• 63powerfulinstructions
• 2-levelsubroutinenesting
• Bitmanipulationinstruction
Peripheral Features• FlashProgramMemory:1K×14
• RAMDataMemory:32×8
• WatchdogTimerfunction
• 4bidirectionalI/Olines
• One10-bitPTMfor timemeasure,comparematchoutput,capture input,PWMoutputandsinglepulseoutputfunctions
• OneTime-Basefunctionforgenerationoffixedtimeinterruptsignals
• Packagetype:SOT23-6,8-pinSOP
Rev. 1.00 6 April 11, 2017 Rev. 1.00 7 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
General DescriptionThisseriesofdevicesareMCUbasedwaveformgeneratorsespeciallydesignedforproductswhichrequirecustomsoundeffectgeneration.The internalmicrocontrollersareFlashMemory8-bithighperformanceRISCarchitecturetype.OfferinguserstheconvenienceofFlashMemorymulti-programmingfeatures,thedevicesalsoincludesawiderangeofadditionalfunctionsandfeaturestoassistwiththeircustomaudiogeneration.OthermemoryincludesanareaofRAMDataMemory.
AnextremelyflexibleTimerModuleprovides timing,pulsegeneration,capture input,comparematchoutputandPWMgenerationfunctions.Protectivefeaturessuchasan internalWatchdogTimercoupledwithexcellentnoiseimmunityandESDprotectionensurethatreliableoperationismaintainedinhostileelectricalenvironments.
Afullchoiceofinternalhighspeedandlowspeedoscillatorfunctionsareprovidedwhichrequirenoexternalcomponentsfor their implementation.Theability tooperateandswitchdynamicallybetweenarangeofoperatingmodesusingdifferentclocksourcesgivesuserstheabilitytooptimisemicrocontrolleroperationandminimisepowerconsumption.Additionally,aninternal5.0VshuntregulatorisintegratedwithintheHT45F2020deviceofferingvoltageregulationfeaturesforawiderangeofinputoperatingvoltages.
WhenusedalongsideHoltek’ssoftwaredevelopmentplatform,designersareprovidedwiththesuiteoftoolstoenabletheeasygenerationandmixingofaudiofrequenciesforthecreationofcustomsoundeffects.TheinclusionofflexibleI/Oprogrammingfeatures,Time-Basefunctionalongwithmanyother featuresensure that thedevicewill findexcellentuse inapplicationssuchascars,motorcyclesandelectronicvehiclessecurityalarmapplicationsaswellasmanyothersetc.
Selection TableThedevicesinthisseriesoffersimilarfunctionsdifferingonlyintheinclusionofashuntregulator,whichresultsindifferentoperatingvoltagerange.
Part No. VDDProgram Memory
Data Memory I/O Timer Module Time
BaseShunt
Regulator Stacks Package
HT45F2020 4.75V~ 5.25V 1K×14 32×8 4 10-bit PTM×1 1 √ 2 SOT23-6
8SOP
HT45F2022 2.2V~ 5.5V 1K×14 32×8 4 10-bit PTM×1 1 2 SOT23-6
8SOP
Rev. 1.00 6 April 11, 2017 Rev. 1.00 7 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Block Diagram
8-bitRISCMCUCore
I/O Timer Module
Flash Program Memory
Flash Memory Programming
Circuitry WatchdogTimer
InterruptController
ResetCircuit
RAM Data Memory
Internal HIRC/LIRCOscillators
* Shunt RegulatorTimeBase
*TheShuntRegulatorisonlyavailablefortheHT45F2020device.
Pin Assignment
Top View2020/2022
6 5 4
321
VDD
VSS
PA0/P
TPI/IC
PD
APA2/PTC
K/ICPC
K
PA1/PTP/PTPB
PA3/P
TP/P
TPB
HT45F2020/HT45F2022SOT23-6-A
161514131211109
12345678
VDDVSS
PA0/PTPI/ICPDANCNCNCNC
OCDSCK
PA3/PTP/PTPBPA1/PTP/PTPBPA2/PTCK/ICPCKNCNCNCNCOCDSDA
HT45V2020/HT45V202216 NSOP-A
VDDPA0/PTPI/ICPDA NC
NC
PA1/PTP/PTPBPA3/PTP/PTPB VSS
PA2/PTCK/ICPCK
1234
8765
HT45F2020/HT45F20228 SOP-A
Note:1.Ifthepin-sharedpinfunctionshavemultipleoutputssimultaneously,thedesiredpin-sharedfunctionisdeterminedbythecorrespondingsoftwarecontrolbits.
2.TheOCDSDAandOCDSCKpinsaresuppliedfortheOCDSdedicatedpinsandassuchareonlyavailablefortheHT45V2020andHT45V2022EVdevices.
Rev. 1.00 8 April 11, 2017 Rev. 1.00 9 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Pin DescriptionWiththeexceptionofthepowerpins,allpinsonthedevicecanbereferencedbyitsPortname,e.g.PA0,PA1etc.,whichrefertothedigitalI/Ofunctionofthepins.HoweverthesePortpinsarealsosharedwithotherfunctionsuchastheTimerModulepinsetc.Thefunctionofeachpinislistedinthefollowingtable,howeverthedetailsbehindhoweachpinisconfigurediscontainedinothersectionsofthedatasheet.
Pin Name Function OPT I/T O/T Description
PA0/PTPI/ICPDAPA0
PAPUPAWUPAS0
ST CMOS General purpose I/O.Register enabled pull-high and wake-up.
PTPI PAS0 ST — PTM capture inputICPDA — ST CMOS ICP Address/Data
PA1/PTP/PTPBPA1
PAPUPAWUPAS0
ST CMOS General purpose I/O.Register enabled pull-high and wake-up.
PTP PAS0 — CMOS PTM outputPTPB PAS0 — CMOS PTM inverted output
PA2/PTCK/ICPCKPA2
PAPUPAWUPAS0
ST CMOS General purpose I/O.Register enabled pull-high and wake-up.
PTCK PAS0 ST — PTM clock inputICPCK — ST — ICP Clock pin
PA3/PTP/PTPBPA3
PAPUPAWUPAS0
ST CMOS General purpose I/O.Register enabled pull-high and wake-up.
PTP PAS0 — CMOS PTM outputPTPB PAS0 — CMOS PTM inverted output
VDD VDD — PWR — Power SupplyVSS VSS — PWR — GroundThe following pin are only for the HT45V2020/HT45V2022NC NC — — — No connectionOCDSDA OCDSDA — ST CMOS OCDS Address/Data, for EV chip onlyOCDSCK OCDSCK — ST — OCDS Clock pin, for EV chip only
Legend:I/T:InputtypeO/T:OutputtypeOPT:OptionalbyregisteroptionPWR:PowerST:SchmittTriggerinputCMOS:CMOSoutput
Rev. 1.00 8 April 11, 2017 Rev. 1.00 9 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Absolute Maximum RatingsSupplyVoltage...................................................................................................VSS-0.3VtoVSS+6.0VInputVoltage.....................................................................................................VSS-0.3VtoVDD+0.3VStorageTemperature..................................................................................................... -50°Cto125°COperatingTemperature................................................................................................... -40°Cto85°CIOLTotal....................................................................................................................................... 80mAIOHTotal...................................................................................................................................... -80mATotalPowerDissipation........................................................................................................... 500mW
Note:Theseare stress ratingsonly.Stressesexceeding the range specifiedunder“AbsoluteMaximumRatings”maycausesubstantialdamagetothedevice.Functionaloperationofthisdeviceatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicereliability.
D.C. CharacteristicsTa=25°C
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
VDDOperating Voltage – HT45F2022 — — 2.2 — 5.5 VOperating Voltage* – HT45F2020 — — 4.75 — 5.25 V
IDD
Operating Current (HIRC)
3V No load, all peripherals off,fSYS=fHIRC=8MHz
— 1.0 2.0 mA5V — 2.0 3.0 mA3V No load, all peripherals off,
fSYS=fHIRC/2 , fHIRC=8MHz— 1.0 1.5 mA
5V — 1.5 2.0 mA3V No load, all peripherals off,
fSYS=fHIRC/4 , fHIRC=8MHz— 0.9 1.3 mA
5V — 1.3 1.8 mA3V No load, all peripherals off,
fSYS=fHIRC/8 , fHIRC=8MHz— 0.8 1.1 mA
5V — 1.1 1.6 mA3V No load, all peripherals off,
fSYS=fHIRC/16 , fHIRC=8MHz— 0.7 1.0 mA
5V — 1.0 1.4 mA3V No load, all peripherals off,
fSYS=fHIRC/32 , fHIRC=8MHz— 0.6 0.9 mA
5V — 0.9 1.2 mA3V No load, all peripherals off,
fSYS=fHIRC/64 , fHIRC=8MHz— 0.5 0.8 mA
5V — 0.8 1.1 mA
Operating Current (LIRC)3V No load, all peripherals off,
fSYS=fLIRC=32kHz— 10 20 μA
5V — 30 50 μA
ISTB
Standby Current (SLEEP Mode)
3V No load, all peripherals off, WDT off
— 0.2 0.8 μA5V — 0.5 1 μA3V No load, all peripherals off,
WDT on— 1.3 5.0 μA
5V — 2.2 10 μA
Standby Current (IDLE0 Mode)3V No load, all peripherals off,
fSUB on— 1.3 3.0 μA
5V — 5.0 10 μA
Standby Current (IDLE1 Mode, HIRC)
3V No load, all peripherals off, fSUB on, fSYS=fHIRC=8MHz
— 0.8 1.6 mA5V — 1.0 2.0 mA
VIL Input Low Voltage for I/O Ports5V — 0 — 1.5 V— — 0 — 0.2VDD V
Rev. 1.00 10 April 11, 2017 Rev. 1.00 11 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
VIH Input High Voltage for I/O Ports5V — 3.5 — 5 V— — 0.8VDD — VDD V
IOL Sink Current for I/O Port3V VOL=0.1VDD 18 36 — mA5V VOL=0.1VDD 40 80 — mA
IOH Source Current for I/O Ports3V VOH=0.9VDD -3 -6 — mA5V VOH=0.9VDD -7 -14 — mA
RPHPull-high Resistance for I/O Ports and OCDS pins
3V — 20 60 100 kΩ5V — 10 30 50 kΩ
ILEAK Input Leakage Current3V
VIN=VDD or VIN=VSS— — ±1 μA
5V — — ±1 μA
IOCDS Operating Current (Normal Mode) 3V No load, fSYS=fHIRC=8MHz, WDT enable — 1.4 2.0 mA
Note:FortheHT45F2020anexternalresistorshouldbeseriallyconnectedbetweenthesupplypowerandVDDpin.Refertothe“ShuntRegulator”sectionforthedetails.
A.C. CharacteristicsTa=25°C
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
fSYSSystem Clock (HIRC) 2.2V~5.5V fSYS=fHIRC=8MHz — 8 — MHzSystem Clock (LIRC) 2.2V~5.5V fSYS=fLIRC=32kHz — 32 — kHz
fHIRCHigh Speed Internal RC Oscillator (HIRC)
3V/5V Ta=25°C -2% 8 +2% MHz3V/5V Ta=0°C to 70°C -5% 8 +5% MHz
2.2V~5.5V Ta=0°C to 70°C -8% 8 +8% MHz2.2V~5.5V Ta=-40°C to 85°C -12% 8 +12% MHz
fLIRCLow Speed Internal RC Oscillator (LIRC)
2.2V~5.5V Ta=-40°C ~ 85°C 8 32 50 kHz2.2V~5.5V Ta=-40°C ~ 85°C 8 32 50 kHz
tTCK PTCK Input Pin Minimum Pulse Width — — 0.3 — — μstTPI PTPI Input Pin Minimum Pulse Width — — 0.3 — — μs
tRSTD
System Reset Delay Time (POR Reset, WDT Software Reset) — — 25 50 100 ms
System Reset Delay Time (WDT Time-out Hardware Cold Reset) — — 8.3 16.7 33.3 ms
tSST
System Start-up Timer Period (Wake-up from Power Down Mode and fSYS Off)
— fSYS=fH ~ fH/64, fH=fHIRC 16 — — tHIRC
— fSYS=fSUB=fLIRC 2 — — tLIRC
System Start-up Timer Period(Slow Mode ↔ Normal Mode) — fHIRC off → on
(HIRCF=1) 16 — — tHIRC
System Start-up Timer Period (Wake-up from Power Down Mode and fSYS On)
— fSYS=fH ~ fH/64, fSYS=fHIRC 2 — — fH— fSYS=fLIRC 2 — — fSUB
System Start-up Timer Period (WDT Time-out Hardware Cold Reset) — — 0 — — fH
tSRESET Minimum Software Reset Width to Reset — — 45 90 250 μs
Note:1.tSYS=1/fSYS2.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1μFdecouplingcapacitorshouldbeconnectedbetweenVDDandVSSandlocatedasclosetothedeviceaspossible.
Rev. 1.00 10 April 11, 2017 Rev. 1.00 11 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Shunt Regulator Electrical Characteristics – for HT45F2020 onlyTa=25°C
Symbol Parameter Condition Min. Typ. Max. UnitVUNREG Supply Voltage — 8 — 16 V
VOUT1Load Voltage – No Load in Room Temperature
VUNREG=8V~16VISUPPLY=ISHUNT(Max) @ VUNREG=16VMCU in SLEEP mode, no load
-3% 5 +3% V
VOUT2Load Voltage – Load and supply voltage within specification
ISUPPLY=ISHUNT(Max) @ VUNREG=16VSelect RSER (1) as MCU in SLEEP mode with no load condition
1. VUNREG=8V, ILOAD=ILOAD(Max)
2. VUNREG=16V, ILOAD=0
-5% 5 +5% V
ILOAD Load Current (2) VUNREG=8V~16V, RSER=(16-VOUT1) / ISHUNT(Max)
0 — 15 mA
ISHUNT(Max) Maximum Shunt Current VUNREG=16V 80 — — mAISTATIC Maximum Static Current VUNREG=16V — — 5 mA
∆VLINE Line RegulationVUNREG=8 V to 16VRSER=(16V – VOUT1) / ISHUNT(Max)
MCU in SLEEP mode, no load— — 0.3 %/V
∆VOUT_RIPPLE Output Voltage Ripple
VUNREG=8 V to 16V,RSER=(16V – VOUT1) / ISHUNT(Max)
MCU alternately consumes the average current IMCU and ILOAD(Max).The MCU varies its consumption current once every 0.5ms (3)
— — 100 mV
∆VLOAD Load Regulation
VUNREG=8V, 12V or 16VRSER=(16V – VOUT1) / ISHUNT(Max)
ILOAD=0mA to ILOAD(Max),CBYPASS=4.7μF, MCU in SLEEP mode
— — 0.03 %/mA
RSERISUPPLY
VUNREG
VOUT
CBYPASS ISHUNT
VDD
Feedback
VSS
ILOADVDD
VSS
Shunt Regulator Operational Block DiagramNote:1.RSER=(VUNREG–VOUT)/ISUPPLY
2.Theloadcurrentmaximumspecificationvalueiscalculatedbasedonthefollowingformula.ILOAD(Max)=ISHUNT(Max)×(VUNREG(Min)–VOUT1(Max))/(VUNREG(Max)–VOUT1(Min))–ISTATIC(Measured)
VUNREG(Max),VOUT1(Max)=MaximumspecificationvalueforVUNREGandVOUT1respectivelyVUNREG(Min),VOUT1(Min)=MinimumspecificationvalueforVUNREGandVOUT1respectively
3.IMCU=MCUcurrentconsumptionmeasuredwhentheMCUtogglestwoI/Opinsevery0.5mswithnoload.
Rev. 1.00 12 April 11, 2017 Rev. 1.00 13 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Power-on Reset CharacteristicsTa=25°C
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mVRRPOR VDD Rising Rate to Ensure Power-on Reset — — 0.035 — — V/ms
tPORMinimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms
VDD
tPOR RRPOR
VPOR
Time
System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.ThedevicetakesadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersproviding increasedspeedofoperationandenhancedperformance.Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranchorcall instructions.An8-bitwideALUisusedinpracticallyall instructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.The internaldatapath issimplifiedbymovingdata throughtheAccumulatorandtheALU.Certain internalregistersare implemented in theDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitecturalfeaturesensure thataminimumofexternalcomponents is required toprovideafunctional I/Ocontrolsystemwithmaximumreliabilityandflexibility.Thismakesthedevicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.
Clocking and PipeliningThemainsystemclock,derivedfromeitheraHIRCorLIRCoscillator issubdivided intofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounter is incrementedat thebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles, thepipeliningstructureof themicrocontrollerensures that instructionsareeffectivelyexecuted inone instructioncycle.Theexception to thisare instructionswhere thecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.
Rev. 1.00 12 April 11, 2017 Rev. 1.00 13 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Fetch Inst. (PC)
(System Clock)fSYS
Phase Clock T1
Phase Clock T2
Phase Clock T3
Phase Clock T4
Program Counter PC PC+1 PC+2
PipeliningExecute Inst. (PC-1) Fetch Inst. (PC+1)
Execute Inst. (PC) Fetch Inst. (PC+2)
Execute Inst. (PC+1)
System Clocking and Pipelining
For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.
Fetch Inst. 11 MOV A,[12H]2 CALL DELAY3 CPL [12H]4 :5 :6 DELAY: NOP
Execute Inst. 1 Fetch Inst. 2 Execute Inst. 2
Fetch Inst. 3 Flush PipelineFetch Inst. 6 Execute Inst. 6
Fetch Inst. 7
Instruction Fetching
Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionisexecutedexcept for instructions, suchas“JMP”or“CALL” thatdemandsa jump toanon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.
Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.
Program Counter
Program Counter High Byte PCL RegisterPC9~PC8 PCL7~PCL0
Program Counter
Rev. 1.00 14 April 11, 2017 Rev. 1.00 15 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly.However,asonlythis lowbyteisavailable formanipulation, the jumpsare limited to thepresentpageofmemory that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.
StackThis isaspecialpartof thememorywhichisusedtosavethecontentsof theProgramCounteronly.Thestackisorganizedinto2levelsandneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.Theactivatedlevel is indexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.
Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointerisdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresultinastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.
Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.
StackPointer
Stack Level 2
Stack Level 1
Program Memory
Program Counter
Bottom of Stack
Top of Stack
Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:
• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA
• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA
• Rotation:RRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC
• IncrementandDecrement:INCA,INC,DECA,DEC
• Branchdecision:JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI
Rev. 1.00 14 April 11, 2017 Rev. 1.00 15 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthisdevicetheProgramMemoryisFlashtype,whichmeansitcanbeprogrammedandre-programmeda largenumberoftimes,allowingtheusertheconvenienceofcodemodificationonthesamedevice.Byusingtheappropriateprogrammingtools,theFlashdeviceofferuserstheflexibilitytoconvenientlydebuganddevelop their applicationswhilealsoofferingameansof fieldprogrammingandupdating.
StructureTheProgramMemoryhasacapacityof1K×14bits.TheProgramMemoryisaddressedby theProgramCounterandalsocontainsdata,tableinformationandinterruptentries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyaseparatetablepointerregister.
000H
008H
3FFH
Reset
Interrupt Vector
14 bits
010H
014H
Program Memory Structure
Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation0000His reservedforuseby thedevicereset forprograminitialisation.Afteradevicereset isinitiated,theprogramwilljumptothislocationandbeginexecution.
Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressofthelookupdatatoberetrievedinthetablepointerregister,TBLP.Thisregisterdefinesthetotaladdressofthelook-uptable.
Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe“TABRDC[m]”or“TABRDL[m]”instructionsrespectively.Whentheinstructionisexecuted,the lowerorder tablebyte from theProgramMemorywillbe transferred to theuserdefinedDataMemoryregister[m]asspecified in the instruction.Thehigherorder tabledatabytefromtheProgramMemorywillbe transferred to theTBLHspecial register.Anyunusedbits in thistransferredhigherorderbytewillbereadas“0”.
Rev. 1.00 16 April 11, 2017 Rev. 1.00 17 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.
PC High Byte Address
TBLP Register
Data14 bits
Program Memory
Register TBLH User Selected Register
High Byte Low Byte
Last page or present page
PC9~PC8
Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.ThisexampleusesrawtabledatalocatedintheProgramMemorywhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis“300H”whichreferstothestartaddressofthelastpagewithinthe1KwordsProgramMemoryofthedevice.Thetablepointerissetupheretohaveaninitialvalueof“06H”.ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress“306H”or6locationsafterthestartofthelastpage.Notethatthevalueforthetablepointerisreferencedtothefirstaddressofthespecificpageifthe“TABRDC[m]”instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe“TABRDC[m]”instructionisexecuted.
Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.
Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2::mov a,06h ; initialise low table pointer - note that this address is referencedmov tblp,a ; to the last page or present page::tabrdc tempreg1 ; transfers value in table referenced by table pointer, ; data at program memory address “306H” transferred to tempreg1 ; and TBLHdec tblp ; reduce value of table pointer by onetabrdc tempreg2 ; transfers value in table referenced by table pointer, ; data at program memory address “305H” transferred to tempreg2 and ; TBLH in this example the data “1AH” is transferred to tempreg1 and ; data “0FH” to register tempreg2 ::org 300h ; sets initial address of program memorydc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh:
Rev. 1.00 16 April 11, 2017 Rev. 1.00 17 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
In Circuit Programming – ICPTheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,andthenprogrammingorupgradingtheprogramata laterstage.Thisenablesproductmanufacturers toeasilykeep theirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.
TheHoltekFlashMCUtoWriterProgrammingPincorrespondencetableisasfollows:
Holtek Writer Pins MCU Programming Pins Pin DescriptionICPDA PA0 Programming Serial Data/AddressICPCK PA2 Programming ClockVDD VDD Power SupplyVSS VSS Ground
TheProgramMemorycanbeprogrammedserially in-circuitusing this4-wire interface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditional linefor theclock.Twoadditional linesarerequiredfor thepowersupply.The technicaldetails regarding the in-circuitprogrammingof thedevice arebeyond the scopeof thisdocument andwill be supplied insupplementaryliterature.
Duringtheprogrammingprocess,theusercantakecontroloftheICPDAandICPCKpinsfordataandclockprogrammingpurposestoensurethatnootheroutputsareconnectedtothesetwopins.
* *
Writer_VDD
ICPDA
ICPCK
Writer_VSS
To other Circuit
VDD
PA0
PA2
VSS
Writer Connector Signals
MCU ProgrammingPins
Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1kΩorthecapacitanceof*mustbelessthan1nF.
Rev. 1.00 18 April 11, 2017 Rev. 1.00 19 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
On-Chip Debug Support – OCDSThereareEVchipsnamedHT45V2020andHT45V2022,whichareusedtoemulatetheHT45F2020andHT45F2022devices.TheEVchipdeviceprovidesan“On-ChipDebug”function todebugthecorrespondingMCUdeviceduringthedevelopmentprocess.TheEVchipandtheactualMCUdevicearealmostfunctionallycompatibleexceptfor the“On-ChipDebug”function.UserscanusetheEVchipdevicetoemulatetherealchipdevicebehaviorbyconnectingtheOCDSDAandOCDSCKpins to theHoltekHT-IDEdevelopment tools.TheOCDSDApin is theOCDSData/Addressinput/outputpinwhiletheOCDSCKpinistheOCDSclockinputpin.WhenusersusetheEVchipfordebugging,otherfunctionswhicharesharedwiththeOCDSDAandOCDSCKpinsintheactualMCUdevicewillhavenoeffectintheEVchip.However,thetwoOCDSpinswhicharepin-sharedwiththeICPprogrammingpinsarestillusedastheFlashMemoryprogrammingpinsforICP.ForamoredetailedOCDSdescription,refertothecorrespondingdocumentnamed“Holteke-Linkfor8-bitMCUOCDSUser’sGuide”.
Holtek e-Link Pins EV Chip Pins Pin DescriptionOCDSDA OCDSDA On-chip Debug Support Data/Address input/outputOCDSCK OCDSCK On-chip Debug Support Clock input
VDD VDD Power SupplyVSS VSS Ground
Data MemoryTheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretemporaryinformationisstored.
StructureDividedintotwotypes,thefirstoftheseisanareaofRAM,knownastheSpecialFunctionDataMemory.Herearelocatedregisterswhicharenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisknownastheGeneralPurposeDataMemory,whichisreservedforgeneralpurposeuse.All locationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.ThestartaddressoftheDataMemoryforalldevicesistheaddress00H.
General Purpose Data MemoryAllmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserprogramingforbothreadingandwritingoperations.ByusingthebitoperationinstructionsindividualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipulationintheDataMemory.
Capacity Location32×8 Bank 0: 40H~5FH
Rev. 1.00 18 April 11, 2017 Rev. 1.00 19 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Special Purpose Data MemoryThis area ofDataMemory iswhere registers, necessary for the correct operation of themicrocontroller,arestored.Mostof theregistersarebothreadableandwriteablebutsomeareprotectedandarereadableonly,thedetailsofwhicharelocatedundertherelevantSpecialFunctionRegistersection.Notethatforlocationsthatareunused,anyreadinstructiontotheseaddresseswillreturnthevalue“00H”.
00H IAR0
01H MP0
02H IAR1
03H MP1
04H
05H ACC
06H PCL
07H TBLP
08H TBLH
09H
RSTFC
0AH STATUS
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
19H
18H
1BH
1AH
1DH
1CH
1FH
1EH
13H
14H
15H
16H
17H
HIRCC
PAPU
PAWU
20H
21H
22H
29H
28H
2AH
2BH
23H
24H
25H
26H
27H
PTMRPH
PA
PAC
PTMRPL
PAS0
INTC0
INTC1
MFI
WDTC
TBC
PTMDH
PTMC1
PTMC0
PTMDL
PTMAH
Bank 0 Bank0
2EH
30H
31H
32H
33H
34H
35H
36H
37H
38H
3FH
PTMAL
2CH
2DH
: Unused, read as "00"
2FH
PSCR
SCC
Special Purpose Data Memory
Rev. 1.00 20 April 11, 2017 Rev. 1.00 21 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsection,howeverseveralregistersrequireaseparatedescriptioninthissection.
Indirect Addressing Registers – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.ThemethodofindirectaddressingforRAMdatamanipulationuses theseIndirectAddressingRegistersandMemoryPointers, incontrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair,IAR0andMP0cantogetheraccessdatafromBank0whiletheIAR1andMP1registerpaircanaccessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof“00H”andwritingtotheregistersindirectlywillresultinnooperation.
Memory Pointers – MP0, MP1TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedtoistheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedtoaccessdatafromallbanksaccordingtoBPregister.DirectAddressingcanonlybeusedwithBank0,allotherBanksmustbeaddressedindirectlyusingMP1andIAR1.Notethatforthedevice,bit7oftheMemoryPointersisnotrequiredtoaddressthefullmemoryspace.Whenbit7oftheMemoryPointersforthedeviceisread,avalueof“1”willbereturned.
ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.
Indirect Addressing Program Exampledata .section ´data´adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ?code .section at 0 code´org 00hstart: mov a,04h ; setup size of block mov block,a mova,offsetadres1 ;AccumulatorloadedwithfirstRAMaddress movmp0,a ;setupmemorypointerwithfirstRAMaddressloop: clrIAR0 ;clearthedataataddressdefinedbymp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loopcontinue:
Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.
Rev. 1.00 20 April 11, 2017 Rev. 1.00 21 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuser-definedregisterandanother, it isnecessary todo thisbypassing thedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.
Program Counter Low Register – PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.
Look-up Table Registers – TBLP, TBLHThese twospecial functionregistersareused tocontroloperationof the look-up tablewhich isstoredintheProgramMemory.TBLPisthetablepointersandindicatethelocationwherethetabledata is located. Itsvaluemustbesetupbeforeanytablereadcommandsareexecuted. Itsvaluecanbechanged,forexampleusingthe“INC”or“DEC”instructions,allowingforeasytabledatapointingandreading.TBLHis thelocationwherethehighorderbyteof thetabledata isstoredaftera tablereaddatainstructionhasbeenexecuted.Notethat thelowerordertabledatabyteistransferredtoauserdefinedlocation.
Status Register – STATUSThis8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.
WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe“CLRWDT”or“HALT”instruction.ThePDFflagisaffectedonlybyexecutingthe“HALT”or“CLRWDT”instructionorduringasystempower-up.
Rev. 1.00 22 April 11, 2017 Rev. 1.00 23 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
TheZ,OV,AC,andCflagsgenerallyreflectthestatusofthelatestoperations.
• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.
• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.
• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.
• OVisset ifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.
• PDFisclearedbyasystempower-uporexecutingthe“CLRWDT”instruction.PDFissetbyexecutingthe“HALT”instruction.
• TOisclearedbyasystempower-uporexecutingthe“CLRWDT”or“HALT”instruction.TOissetbyaWDTtime-out.
Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.
STATUS Register
Bit 7 6 5 4 3 2 1 0Name — — TO PDF OV Z AC CR/W — — R R R/W R/W R/W R/WPOR — — 0 0 x x x x
“x”: unknownBit7~6 Unimplemented,readas“0”Bit5 TO:WatchdogTime-Outflag
0:Afterpoweruporexecutingthe“CLRWDT”or“HALT”instruction1:Awatchdogtime-outoccurred.
Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe“CLRWDT”instruction1:Byexecutingthe“HALT”instruction
Bit3 OV:Overflowflag0:nooverflow1:anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.
Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero
Bit1 AC:Auxiliaryflag0:noauxiliarycarry1:anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction
Bit0 C:Carryflag0:nocarry-out1:anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation
Cisalsoaffectedbyarotatethroughcarryinstruction.
Rev. 1.00 22 April 11, 2017 Rev. 1.00 23 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
OscillatorsVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughtherelevantcontrolregister.
Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfortheWatchdogTimerandTimeBaseInterrupts.Twofullyintegratedinternaloscillators,requiringnoexternalcomponents,areprovidedtoformarangeofbothfastandslowsystemoscillators.Thehigherfrequencyoscillatorprovideshigherperformancebutcarrywithitthedisadvantageofhigherpowerrequirements,whiletheoppositeisofcoursetrueforthelowerfrequencyoscillator.Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock, thedevicehas theflexibilitytooptimizetheperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.
Type Name FrequencyInternal High Speed RC HIRC 8MHzInternal Low Speed RC LIRC 32kHz
Oscillator Types
System Clock Configurations Thereare twomethodsofgeneratingthesystemclock,ahighspeedoscillatoranda lowspeedoscillator.Thehighspeedoscillatoristheinternal8MHzRCoscillator.Thelowspeedoscillatoristheinternal32kHzRCoscillator.SelectingwhethertheloworhighspeedoscillatorisusedasthesystemoscillatorisimplementedusingtheCKS2~CKS0bitsintheSCCregisterandasthesystemclockcanbedynamicallyselected.
HIRCENPrescaler
High Speed Oscillator
Low Speed Oscillator
fH/2
fH/16
fH/64
fH/8
fH/4
fH/32
CKS2~CKS0
fSYS
fSUB fSUBLIRC
fLIRC
fLIRC
HIRC
fH
IDLE0SLEEP
IDLE2SLEEP
System Clock Configurations
Rev. 1.00 24 April 11, 2017 Rev. 1.00 25 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
High Speed Internal RC Oscillator – HIRC ThehighspeedinternalRCoscillator isafullyintegratedsystemoscillatorrequiringnoexternalcomponents.TheinternalRCoscillatorhasafixedfrequencyof8MHz.Devicetrimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensure that the influenceof thepowersupplyvoltage, temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyofeither3Vor5Vandatatemperatureof25°Cdegrees,thefixedoscillationfrequencyof8MHzwillhaveatolerancewithin2%.
Internal 32kHz Oscillator – LIRC The internal32kHzSystemOscillator is the lowfrequencyoscillator. It isa fully integratedRCoscillatorwitha typicalfrequencyof32kHzat5V,requiringnoexternalcomponentsfor itsimplementation.Devicetrimmingduringthemanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.
Supplementary Oscillators Thelowspeedoscillator, inadditiontoprovidingasystemclocksource isalsousedtoprovideaclocksource to twootherdevicefunctions.Theseare theWatchdogTimerandtheTimeBaseInterrupts.
Operating Modes and System Clocks Presentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcoursevice-versa, lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovidedthedevicewithbothhighandlowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically, theusercanoptimisetheoperationof theirmicrocontrollertoachievethebestperformance/powerratio.
System Clocks Thedevicehasdifferentclocksources forboth theCPUandperipheral functionoperation.Byprovidingtheuserwithawiderangeofclockselectionsusingregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.
Themainsystemclock,cancomefromeitherahighfrequency,fH,orlowfrequency,fSUB,source,andisselectedusingtheCKS2~CKS0bits in theSCCregister.ThehighspeedsystemclockissourcedfromtheHIRCoscillator.ThelowspeedsystemclocksourcecanbesourcedfromtheLIRCoscillator.Theotherchoice,whichisadividedversionof thehighspeedsystemoscillatorhasarangeoffH/2~fH/64.
Rev. 1.00 24 April 11, 2017 Rev. 1.00 25 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HIRCENPrescaler
High Speed Oscillator
Low Speed Oscillator
fH/2
fH/16
fH/64
fH/8
fH/4
fH/32
CKS2~CKS0
fSYS
fSUB fSUB
LIRC
fLIRC
fLIRC
HIRC
fH
WDT
fSYS/4Time BasefSUB
fSYS
Prescaler
CLKSEL[1:0]
fPSC
IDLE0SLEEP
IDLE2SLEEP
TB[2:0]
Device Clock ConfigurationsNote:WhenthesystemclocksourcefSYSisswitchedtofSUBfromfH,thehighspeedoscillatorcanbestoppedto
conservethepowerorcontinuetooscillatetoprovidetheclocksource,fH~fH/64,forperipheralcircuittouse,whichisdeterminedbyconfiguringthecorrespondinghighspeedoscillatorenablecontrolbit.
System Operation ModesThere are six differentmodesof operation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller, theNORMALModeandSLOWMode.Theremainingfourmodes, theSLEEP,IDLE0,IDLE1andIDLE2ModeareusedwhenthemicrocontrollerCPUisswitchedofftoconservepower.
Operation Mode CPURelated Register value
fSYS fH fSUB fLIRCFHIDEN FSIDEN CKS[2:0]
NORMAL Mode On x x 000~110 On On On OnSLOW Mode On x x 111 On On/Off(1) On On
IDLE0 Mode Off 0 1000~110 Off
Off On On111 On
IDLE1 Mode Off 1 1 xxx On On On On
IDLE2 Mode Off 1 0000~110 On
On Off On111 Off
SLEEP Mode Off 0 0 xxx Off Off Off On/Off(2)
“x”: Don’t careNote:1.ThefHclockwillbeswitchedonoroffbyconfiguringthecorrespondingoscillatorenablebit in the
SLOWmode.2.ThefLIRCclockcanbeswitchedonoroffwhichiscontrolledbytheWDTfunctionbeingenabledordisabledintheSLEEPmode.
Rev. 1.00 26 April 11, 2017 Rev. 1.00 27 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
NORMAL ModeAsthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbythehighspeedoscillators.ThismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromthehighspeedoscillatorsHIRC.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0bitsintheSCCregister.Althoughahighspeedoscillatorisused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.
SLOW ModeThisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.TheclocksourceusedwillbefromfSUB.ThefSUBclockisderivedfromtheLIRCoscillator.Runningthemicrocontroller in thismodeallowsit torunwithmuchloweroperatingcurrents.
SLEEP ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENandFSIDENbitarelow.IntheSLEEPmodetheCPUwillbestopped,andthefSUBclocktoperipheralwillbestoppedtoo,buttheWatchdogTimerfunctionisdecidedbyuserapplication.
IDLE0 Mode TheIDLE0ModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENbitintheSCCregister is lowandtheFSIDENbit intheSCCregister ishigh.IntheIDLE0ModetheCPUwillbeswitchedoffbutthelowspeedoscillatorwillbeturnedontodrivesomeperipheralfunctions.
IDLE1 ModeTheIDLE1ModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENbitintheSCCregisterishighandtheFSIDENbitintheSCCregisterishigh.IntheIDLE1ModetheCPUwillbeswitchedoffbutboththehighandlowspeedoscillatorswillbeturnedontoprovideaclocksourcetokeepsomeperipheralfunctionsoperational.
IDLE2 ModeTheIDLE2ModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENbitintheSCCregisterishighandtheFSIDENbitintheSCCregisterislow.IntheIDLE2ModetheCPUwillbeswitchedoffbutthehighspeedoscillatorwillbeturnedontoprovideaclocksourcetokeepsomeperipheralfunctionsoperational.
Rev. 1.00 26 April 11, 2017 Rev. 1.00 27 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Control RegisterThe registers,SCCandHIRCC,areused tocontrol the systemclockand thecorrespondingoscillatorconfigurations.
Register Name
Bit
7 6 5 4 3 2 1 0SCC CKS2 CKS1 CKS0 — — — FHIDEN FSIDEN
HIRCC — — — — — — HIRCF HIRCEN
System Operating Mode Control Registers List
SCC Register
Bit 7 6 5 4 3 2 1 0Name CKS2 CKS1 CKS0 — — — FHIDEN FSIDENR/W R/W R/W R/W — — — R/W R/WPOR 0 0 0 — — — 0 0
Bit7~5 CKS2~CKS0:Systemclockselection000:fH
001:fH/2010:fH/4011:fH/8100:fH/16101:fH/32110:fH/64111:fSUB
Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.InadditiontothesystemclocksourcedirectlyderivedfromfHorfSUB,adividedversionofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource.
Bit4~2 Unimplemented,readas“0”Bit1 FHIDEN:HighFrequencyoscillatorcontrolwhenCPUisswitchedoff
0:Disable1:Enable
Thisbit isusedtocontrolwhether thehighspeedoscillator isactivatedorstoppedwhentheCPUisswitchedoffbyexecutingan“HALT”instruction.
Bit0 FSIDEN:LowFrequencyoscillatorcontrolwhenCPUisswitchedoff0:Disable1:Enable
Thisbit isusedtocontrolwhether the lowspeedoscillator isactivatedorstoppedwhentheCPUisswitchedoffbyexecutingan“HALT”instruction.
Rev. 1.00 28 April 11, 2017 Rev. 1.00 29 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HIRCC Register
Bit 7 6 5 4 3 2 1 0Name — — — — — — HIRCF HIRCENR/W — — — — — — R/W R/WPOR — — — — — — 0 1
Bit7~2 Unimplemented,readas“0”Bit1 HIRCF:HIRCoscillatorstableflag
0:Unstable1:Stable
Thisbit isusedto indicatewhether theHIRCoscillator isstableornot.WhentheHIRCENbit isset to1 toenable theHIRCoscillator, theHIRCFbitwill firstbeclearedto0andthensetto1aftertheHIRCoscillatorisstable.
Bit0 HIRCEN:HIRCoscillatorenablecontrol0:Disable1:Enable
Operating Mode Switching Thedevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselect thebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.
Insimpleterms,ModeSwitchingbetweentheNORMALModeandSLOWModeisexecutedusingtheCKS2~CKS0bitsintheSCCregisterwhileModeSwitchingfromtheNORMAL/SLOWModesto theSLEEP/IDLEModesisexecutedvia theHALTinstruction.WhenanHALTinstructionisexecuted,whether thedeviceenters theIDLEModeor theSLEEPMode isdeterminedby theconditionoftheFHIDENandFSIDENbitsintheSCCregister.
NORMALfSYS=fH~fH/64
fH onCPU runfSYS onfSUB on
SLOWfSYS=fSUBfSUB on
CPU runfSYS on
fH on/off
IDLE0HALT instruction executed
CPU stopFHIDEN=0FSIDEN=1
fH offfSUB on
IDLE1HALT instruction executed
CPU stopFHIDEN=1FSIDEN=1
fH onfSUB on
IDLE2HALT instruction executed
CPU stopFHIDEN=1FSIDEN=0
fH onfSUB off
SLEEPHALT instruction executed
CPU stopFHIDEN=0FSIDEN=0
fH offfSUB off
Rev. 1.00 28 April 11, 2017 Rev. 1.00 29 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
NORMAL Mode to SLOW Mode Switching WhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower, the systemclock can switch to run in theSLOWModeby set theCKS2~CKS0bitsto“111”intheSCCregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.
TheSLOWModeissourcedfromtheLIRCoscillatorandthereforerequires thisoscillator tobestablebeforefullmodeswitchingoccurs.
NORMAL Mode
SLOW Mode
CKS2~CKS0 = 111
SLEEP Mode
FHIDEN=0, FSIDEN=0HALT instruction is executed
IDLE0 Mode
FHIDEN=0, FSIDEN=1HALT instruction is executed
IDLE1 Mode
FHIDEN=1, FSIDEN=1HALT instruction is executed
IDLE2 Mode
FHIDEN=1, FSIDEN=0HALT instruction is executed
Rev. 1.00 30 April 11, 2017 Rev. 1.00 31 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
SLOW Mode to NORMAL Mode Switching InSLOWmodethesystemclockisderivedfromfSUB.WhensystemclockisswitchedbacktotheNORMALmodefromfSUB,theCKS2~CKS0bitsshouldbesetto“000”~“110”andthenthesystemclockwillrespectivelybeswitchedtofH~fH/64.
However, if fH isnotused inSLOWmodeand thusswitchedoff, itwill takesometime tore-oscillateandstabilisewhenswitching to theNORMALmode from theSLOWMode.This ismonitoredusingtheHIRCFbitintheHIRCCregister.ThetimedurationrequiredforthehighspeedsystemoscillatorstabilizationisspecifiedintheA.C.characteristics.
NORMAL Mode
SLOW Mode
CKS2~CKS0 = 000~110
SLEEP Mode
FHIDEN=0, FSIDEN=0HALT instruction is executed
IDLE0 Mode
FHIDEN=0, FSIDEN=1HALT instruction is executed
IDLE1 Mode
FHIDEN=1, FSIDEN=1HALT instruction is executed
IDLE2 Mode
FHIDEN=1, FSIDEN=0HALT instruction is executed
Entering the SLEEP Mode ThereisonlyonewayforthedevicetoentertheSLEEPModeandthatistoexecutethe“HALT”instructionintheapplicationprogramwithboththeFHIDENandFSIDENbitsintheSCCregisterequalto“0”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• The systemclockwill be stoppedand the applicationprogramwill stopat the “HALT”instruction.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownflagPDFwillbeset,andWDTtimeoutflagTOwillbecleared.
• TheWDTwillbeclearedandresumecountingastheWDTisenabled.IftheWDTisdisabledthenWDTwillbeclearedandstopped.
Rev. 1.00 30 April 11, 2017 Rev. 1.00 31 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Entering the IDLE0 Mode ThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeFHIDENbitintheSCCregisterequalto“0”andtheFSIDENbitintheSCCregisterequalto“1”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• ThefHclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction,butthefSUBclockwillbeon.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownflagPDFwillbeset,andWDTtimeoutflagTOwillbecleared.
• TheWDTwillbeclearedandresumecountingastheWDTisenabled.IftheWDTisdisabledthenWDTwillbeclearedandstopped.
Entering the IDLE1 Mode ThereisonlyonewayforthedevicetoentertheIDLE1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeFHIDENbit inSCCregisterequalto“1”andtheFSIDENbitintheSCCregisterequalto“1”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• ThefHandfSUBclockswillbeonbuttheapplicationprogramwillstopatthe“HALT”instruction.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownflagPDFwillbeset,andWDTtimeoutflagTOwillbecleared.
• TheWDTwillbeclearedandresumecountingastheWDTisenabled.IftheWDTisdisabledthenWDTwillbeclearedandstopped.
Entering the IDLE2 Mode ThereisonlyonewayforthedevicetoentertheIDLE2Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeFHIDENbitintheSCCregisterequalto“1”andtheFSIDENbit inSCCregisterequal to“0”.Whenthis instructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• ThefHclockwillbeonbutthefSUBclockwillbeoffandtheapplicationprogramwillstopatthe“HALT”instruction.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownflagPDFwillbeset,andWDTtimeoutflagTOwillbecleared.
• TheWDTwillbeclearedandresumecountingastheWDTisenabled.IftheWDTisdisabledthenWDTwillbeclearedandstopped.
Rev. 1.00 32 April 11, 2017 Rev. 1.00 33 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Standby Current Considerations AsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicetoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1andIDLE2Mode,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesignerif thepowerconsumptionistobeminimised.SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.
Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuits thatdonotdrawcurrent,suchasotherCMOSinputs.Alsonote thatadditionalstandbycurrentwillalsoberequirediftheLIRCoscillatorhasenabled.
In theIDLE1andIDLE2Modethehighspeedoscillator ison, if theperipheral functionclocksourceisderivedfromthehighspeedoscillator,theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.
Wake-upTominimisepowerconsumptionthedevicecanenter theSLEEPoranyIDLEMode,wheretheCPUwillbeswitchedoff.However,whenthedeviceiswokenupagain,itwilltakeaconsiderabletimefortheoriginalsystemoscillatortorestart,stabliseandallownormaloperationtoresume.
AfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:
• AnexternalfallingedgeonPortA
• Asysteminterrupt
• AWDToverflow
Whenthedeviceexecutesthe“HALT”instruction,thePDFflagwillbesetto1.ThePDFflagwillbeclearedto0ifthedeviceexperiencesasystempower-uporexecutestheclearWatchdogTimerinstruction.IfthesystemiswokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiatedandtheTOflagwillbesetto1.TheTOflagissetifaWDTtime-outoccursandcausesawake-upthatonlyresetstheProgramCounterandStackPointer,otherflagsremainintheiroriginalstatus.
EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowakeupthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.Inthissituation,theinterruptwhichwokeupthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.
Rev. 1.00 32 April 11, 2017 Rev. 1.00 33 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.
Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbytheinternalfLIRCclockwhichissuppliedbytheLIRCoscillator.TheWatchdogTimersourceclockisthensubdividedbyaratioof28to215togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.TheLIRCinternaloscillatorhasanapproximateperiodof32kHzatasupplyvoltageof5V.However,itshouldbenotedthatthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.
Watchdog Timer Control RegisterAsingleregister,WDTC,controlstherequiredtimeoutperiodaswellastheenable/disableandresetMCUoperation.ThisregistercontrolstheoveralloperationoftheWatchdogTimer.
WDTC Register
Bit 7 6 5 4 3 2 1 0Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1
Bit7~3 WE4~WE0:WDTfunctionsoftwarecontrol10101:Disable01010:EnableOthervalues:ResetMCU(TheresetoperationwillbeactivatedaftertSRESETtime.)
Whenthesebitsarechangedbytheenvironmentalnoiseorsoftwaresettingtoresetthemicrocontroller,theresetoperationwillbeactivatedafteradelaytime,tSRESET,andtheWRFbitintheRSTFCregisterwillbesetto1.
Bit2~0 WS2~WS0:WDTtime-outperiodselection000:28/fLIRC001:29/fLIRC010:210/fLIRC011:211/fLIRC100:212/fLIRC101:213/fLIRC110:214/fLIRC111:215/fLIRC
These threebitsdetermine thedivisionratioof theWatchdogTimersourceclock,whichinturndeterminesthetimeoutperiod.
RSTFC Register
Bit 7 6 5 4 3 2 1 0Name — — — — — — — WRFR/W — — — — — — — R/WPOR — — — — — — — 0
Bit7~1 Unimplemented,readas“0”Bit0 WRF:WDTcontrolregistersoftwareresetflag
0:Notoccurred1:Occurred
Thisbit isset to1by theWDTcontrol registersoftwareresetandclearedby theapplicationprogram.Notethatthisbitcanonlybeclearedto0bytheapplicationprogram.
Rev. 1.00 34 April 11, 2017 Rev. 1.00 35 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.WithregardtotheWatchdogTimerenable/disablefunction,therearefivebits,WE4~WE0,intheWDTCregistertoofferadditionalenable/disableandresetcontrolof theWatchdogTimer.TheWDTfunctionwillbedisabledwhentheWE4~WE0bitsaresettoavalueof10101B.TheWDTfunctionwillbeenablediftheWE4~WE0bitsvalueisequalto01010B.IftheWE4~WE0bitsaresettoanyothervaluesbytheenvironmentalnoiseorsoftwaresetting,except01010Band10101B,itwillresetthedeviceafteradelaytime,tSRESET.Afterpoweronthesebitswillhavethevalueof01010B.
WE4~WE0 Bits WDT Function10101B Disable01010B Enable
Any other value Reset MCU
Watchdog Timer Enable/Disable Control
Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.ThefirstisaWDTreset,whichmeansacertainvalueexcept01010Band10101BwrittenintotheWE4~WE0bitfiled,thesecondisusingtheWatchdogTimersoftwareclearinstructionandthethirdisviaaHALTinstruction.
ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistousethesingle“CLRWDT”instructiontocleartheWDT.
Themaximumtimeoutperiod iswhenthe215divisionratio isselected.Asanexample,witha32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround1secondsforthe215divisionratio,andaminimumtimeoutof8msforthe28divisionration.
“CLR WDT”Instruction
8-stage Divider WDT Prescaler
WE4~WE0 bitsWDTC Register Reset MCU
LIRCfLIRC fLIRC/28
8-to- 1 MUX
CLR
WS2~WS0 WDT Time-out(28/fLIRC ~ 215/fLIRC)
“HALT”Instruction
Watchdog Timer
Rev. 1.00 34 April 11, 2017 Rev. 1.00 35 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawell-definedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.
AnothertypeofresetiswhentheWatchdogTimeroverflowsandresets.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.
Reset FunctionsTherearethreewaysinwhicharesetcanoccur,eachofwhichwillbedescribedasfollows.
Power-on ResetThemostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/OportandportcontrolregisterswillpowerupinahighconditionensuringthatallI/Oportswillbefirstsettoinputs.
VDD
Power-on Reset
SST Time-out
tRSTD
Note:tRSTDispower-ondelaywithtypicaltime=50msPower-On Reset Timing Chart
Watchdog Time-out Reset during Normal Operation TheWatchdogtime-outResetduringnormaloperationisalittledifferentfromPower-onreset.MostoftheconditionsremainunchangedexceptthattheWatchdogtime-outflagTOwillbesetto“1”.
WDT Time-out
Internal ResettRSTD + tSST
Note:tRSTDispower-ondelaywithtypicaltime=16.7msWDT Time-out Reset during Normal Operation Timing Chart
Rev. 1.00 36 April 11, 2017 Rev. 1.00 37 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Watchdog Time-out Reset during SLEEP or IDLE Mode TheWatchdogtime-outResetduringSLEEPorIDLEModeisalittledifferentfromPower-onreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto“0”andtheTOflagwillbesetto“1”.RefertotheA.C.CharacteristicsfortSSTdetails.
WDT Time-out
Internal ResettSST
WDT Time-out Reset during SLEEP or IDLE Timing Chart
Reset Initial Conditions Thedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:
TO PDF Reset Conditions0 0 Power-on reset1 u WDT time-out reset during Normal or SLOW Mode operation1 1 WDT time-out reset during IDLE or SLEEP Mode operation
Note: “u” stands for unchangedThefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.
Item Condition after ResetProgram Counter Reset to zeroInterrupts All interrupts will be disabledWDT,Time Base Clear after reset, WDT begins countingTimer Module Timer Module will be turned offInput/Output Ports I/O ports will be setup as inputsStack Pointer Stack Pointer will point to the top of the stack
Rev. 1.00 36 April 11, 2017 Rev. 1.00 37 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrolleris inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachofthemicrocontrollerinternalregisters.
Register Reset(Power On)
WDT Time-out(Normal Operation)
WDT Time-out(IDLE/SLEEP)*
Program Counter 0 0 0 H 0 0 0 H 0 0 0 HMP0 x x x x x x x x x x x x x x x x u u u u u u u uMP1 x x x x x x x x x x x x x x x x u u u u u u u uACC x x x x x x x x u u u u u u u u u u u u u u u uPCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBLP x x x x x x x x u u u u u u u u u u u u u u u uTBLH - - x x x x x x - - u u u u u u - - u u u u u uSTATUS - - 0 0 x x x x - - 1 u u u u u - - 1 1 u u u uRSTFC - - - - - - - 0 - - - - - - - u - - - - - - - uINTC0 - - 0 - - 0 - 0 - - 0 - - 0 - 0 - - u - - u - uINTC1 - - - 0 - - - 0 - - - 0 - - - 0 - - - u - - - uMFI - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uPA - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u uPAC - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u uPAPU - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uPAWU - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uWDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 u u u u u u u uPSCR - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTBC 0 - - - - 0 0 0 0 - - - - 0 0 0 u - - - - u u uSCC 0 0 0 - - - 0 0 0 0 0 - - - 0 0 u u u - - - u uHIRCC - - - - - - 0 1 - - - - - - 0 1 - - - - - - u uPAS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTMC0 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u - - -PTMC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTMDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTMDH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTMAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTMAH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTMRPL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTMRPH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u
Note:“u”standsforunchanged“x”standsforunknown
“-”standsforunimplemented
Rev. 1.00 38 April 11, 2017 Rev. 1.00 39 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Input/Output Ports HoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.
Thedeviceprovidesbidirectional input/output lines labeledwithportnamePA.TheseI/Oportsaremappedto theRAMDataMemorywithspecificaddressesasshownin theSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction“MOVA,[m]”,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.
Register Name
Bit
7 6 5 4 3 2 1 0PA — — — — PA3 PA2 PA1 PA0
PAC — — — — PAC3 PAC2 PAC1 PAC0PAPU — — — — PAPU3 PAPU2 PAPU1 PAPU0PAWU — — — — PAWU3 PAWU2 PAWU1 PAWU0
I/O Logic Function Register List
Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternal resistor.Toeliminate theneedfor theseexternal resistors,all I/Opins,whenconfiguredasan inputhave thecapabilityofbeingconnected toan internalpull-highresistor.Thesepull-highresistorsareselectedusingtherelevantpull-highcontrolregistersPAPU,andareimplementedusingweakPMOStransistors.Notethatthepull-highresistorcanbecontrolledbytherelevantpull-highcontrolregistersonlywhenthepin-sharedfunctionalpinisselectedasadigitalinputorNMOSoutput.Otherwise,thepull-highresistorscannotbeenabled.
PAPU Register
Bit 7 6 5 4 3 2 1 0Name — — — — PAPU3 PAPU2 PAPU1 PAPU0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0
Bit7~4 Unimplemented,readas“0”Bit3~0 PAPU3~PAPU0:PortAbit3~bit0Pull-highControl
0:Disable1:Enable
Rev. 1.00 38 April 11, 2017 Rev. 1.00 39 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.Notethatthewake-upfunctioncanbecontrolledbythewake-upcontrolregistersonlywhenthepin-sharedfunctionalpinisselectedasgeneralpurposeinput/outputandtheMCUentersthePowerdownmode.
PAWU Register
Bit 7 6 5 4 3 2 1 0Name — — — — PAWU3 PAWU2 PAWU1 PAWU0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0
Bit7~4 Unimplemented,readas“0”Bit3~0 PAWU3~PAWU0:PortAbit3~bit0Wake-upControl
0:Disable1:Enable
I/O Port Control RegistersEachI/OporthasitsowncontrolregisterknownasPAC,tocontroltheinput/outputconfiguration.With thiscontrol register,eachCMOSoutputor inputcanbe reconfigureddynamicallyundersoftwarecontrol.EachpinoftheI/Oportsisdirectlymappedtoabitinitsassociatedportcontrolregister.FortheI/Opintofunctionasaninput, thecorrespondingbitofthecontrolregistermustbewrittenasa“1”.Thiswill thenallowthe logicstateof the inputpin tobedirectly readbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa“0”,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.
PAC Register
Bit 7 6 5 4 3 2 1 0Name — — — — PAC3 PAC2 PAC1 PAC0R/W — — — — R/W R/W R/W R/WPOR — — — — 1 1 1 1
Bit7~4 Unimplemented,readas“0”Bit3~0 PAC3~PAC0:PortAbit3~bit0Input/OutputControl
0:Output1:Input
Rev. 1.00 40 April 11, 2017 Rev. 1.00 41 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Pin-shared FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeovercome.Forthesepins,thedesiredfunctionofthemulti-functionI/Opinsisselectedbytheapplicationprogramcontrol.
Pin-shared Function Selection RegistersThelimitednumberofsuppliedpinsinapackagecanimposerestrictionsontheamountoffunctionsacertaindevicecancontain.Howeverbyallowingthesamepinstoshareseveraldifferentfunctionsandprovidingameansoffunctionselection,awiderangeofdifferentfunctionscanbeincorporatedintoevenrelativelysmallpackagesizes.Thedevice includesPortAoutput functionselectionregister“n”,labeledasPASn,whichcanselectthedesiredfunctionsofthemulti-functionpin-sharedpins.
When thepin-shared input function isselected tobeused, thecorresponding inputandoutputfunctionsselectionshouldbeproperlymanaged.
Themostimportantpoint tonoteis tomakesurethat thedesiredpin-sharedfunctionisproperlyselectedandalsodeselected.Toselect thedesiredpin-sharedfunction, thepin-sharedfunctionshouldfirstbecorrectlyselectedusingthecorrespondingpin-sharedcontrolregister.Afterthatthecorrespondingperipheralfunctionalsettingshouldbeconfiguredandthentheperipheralfunctioncanbeenabled.Tocorrectlydeselectthepin-sharedfunction,theperipheralfunctionshouldfirstbedisabledandthenthecorrespondingpin-sharedfunctioncontrolregistercanbemodifiedtoselectotherpin-sharedfunctions.
PAS0 Register
Bit 7 6 5 4 3 2 1 0Name PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~6 PAS07~PAS06:PA3pinfunctionselection0x:PA310:PTP11:PTPB
Bit5~4 PAS05~PAS04:PA2pinfunctionselection00:PA2/PTCK01:PA2/PTCK10:PA2/PTCK11:PA2/PTCK
Bit3~2 PAS03~PAS02:PA1pinfunctionselection0x:PA110:PTP11:PTPB
Bit1~0 PAS01~PAS00:PA0pinfunctionselection00:PA0/PTPI01:PA0/PTPI10:PA0/PTPI11:PA0/PTPI
Rev. 1.00 40 April 11, 2017 Rev. 1.00 41 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
I/O Pin StructuresTheaccompanyingdiagramillustratestheinternalstructureoftheI/Ologicfunction.Astheexactlogicalconstructionof theI/Opinwilldifferfromthisdiagram,it issuppliedasaguideonlytoassistwiththefunctionalunderstandingofthelogicfunctionI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.
MUX
VDD
Control Bit
Data Bit
Data Bus
Write Control Register
Chip Reset
Read Control Register
Read Data Register
Write Data Register
System Wake-up wake-up Select PA only
I/O pin
WeakPull-up
Pull-highRegisterSelect
Q
D
CK
Q
D
CK
Q
QS
S
Logic Function Input/Output Structure
Programming Considerations Withintheuserprogram,oneofthefirstthingstoconsiderisportinitialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoaninputstate, thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.Iftheportcontrolregister,PAC,arethenprogrammedtosetupsomepinsasoutputs, theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregister,PA,arefirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvalues into theappropriateportcontrolregisterorbyprogrammingindividualbitsintheportcontrolregisterusingthe“SET[m].i”and“CLR[m].i”instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.
PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.
Rev. 1.00 42 April 11, 2017 Rev. 1.00 43 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdeviceistheabilitytocontrolandmeasuretime.ToimplementtimerelatedfunctionsthedeviceincludesaPeriodicTimerModule,generallyabbreviated to thenamePTM.ThePTMaremulti-purpose timingunitsandserve toprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeingthefunctionalunitforthegenerationofPWMsignals.ThePTMhastwoindividual interrupts.Theadditionof inputandoutputpinsfor thePTMensures thatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.
ThebrieffeaturesofthePeriodicTMaredescribedherewithmoredetailedinformationprovidedinthePeriodicTypeTMsection.
IntroductionThedevicecontainsa10-bitPeriodicTypeTM.ThemainfeaturesofthePTMaresummarisedintheaccompanyingtable.
TM Function PTMTimer/Counter √Input Capture √Compare Match Output √PWM Channels 1Single Pulse Output 1PWM Alignment EdgePWM Adjustment Period & Duty Duty or Period
PTM Function Summary
TM OperationThePeriodicTMoffersadiverse rangeof functions, fromsimple timingoperations toPWMsignalgeneration.ThekeytounderstandinghowtheTMoperates is tosee it in termsofafreerunningcount-upcounterwhosevalueisthencomparedwiththevalueofpre-programmedinternalcomparators.Whenthefreerunningcount-upcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounterisdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.
TM Clock SourceTheclocksourcewhichdrivesthemaincounterinthePTMcanoriginatefromvarioussources.Theselectionof therequiredclocksourceis implementedusingthePTCK2~PTCK0bits inthePTMcontrolregister,PTMC0.Theclocksourcecanbearatioofthesystemclock,fSYS,ortheinternalhighclock,fH,thefSUBclocksourceortheexternalPTCKpin.ThePTCKpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceforeventcounting.
TM InterruptsThePeriodictypeTMhastwointernalinterrupts,theinternalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.WhenaTMinterruptisgenerated,itcanbeusedtoclearthecounterandalsotochangethestateoftheTMoutputpin.
Rev. 1.00 42 April 11, 2017 Rev. 1.00 43 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
TM External Pins ThePeriodictypeTMhastwoTMinputpins,withthelabelPTCKandPTPIrespectively.ThePTMinputpin,PTCK,isessentiallyaclocksourceforthePTMandisselectedusingthePTCK2~PTCK0bitsinthePTMC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.ThePTCKinputpincanbechosentohaveeitherarisingorfallingactiveedge.ThePTCKpinisalsousedastheexternal triggerinputpininsinglepulseoutputmodefor thePTMrespectively.
TheotherPTMinputpin,PTPI, is thecapture inputwhoseactiveedgecanbearisingedge,afallingedgeorbothrisingandfallingedgesandtheactiveedgetransitiontypeisselectedusingthePTIO1~PTIO0bitsinthePTMC1registerrespectively.Thereisanothercaptureinput,PTCK,forPTMcaptureinputmode,whichcanbeusedastheexternaltriggerinputsourceexceptthePTPIpin.
ThePTMhastwooutputpins,PTPandPTPB.ThePTPBistheinvertedsignalofthePTPoutput.TheTMoutputpinscanbeselectedusing thecorrespondingpin-sharedfunctionselectionbitsdescribedinthePin-sharedFunctionsection.WhentheTMisintheCompareMatchOutputMode,thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalPTPorPTPBoutputpinisalsothepinwheretheTMgeneratesthePWMoutputwaveform.AstheTMoutputpinsarepin-sharedwithotherfunctions, theTMoutputfunctionmustfirstbesetupusingrelevantpin-sharedfunctionselectionregister.
PTM
Input OutputPTCK, PTPI PTP, PTPB
TM External Pins
TM Input/Output Pin SelectionSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunctionisimplementedusingtherelevantpin-sharedfunctionselectionregisters,withthecorrespondingselectionbits ineachpin-sharedfunctionregistercorrespondingtoaTMinput/outputpin.ConfiguringtheselectionbitscorrectlywillsetupthecorrespondingpinasaTMinput/output.Thedetailsofthepin-sharedfunctionselectionaredescribedinthepin-sharedfunctionsection.
PTM
PTCK
PTP
PTPICCR capture input
CCR output
PTPB
PTM Function Pin Control Block Diagram
Rev. 1.00 44 April 11, 2017 Rev. 1.00 45 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Programming ConsiderationsTheTMCounterRegistersandtheCapture/CompareCCRAandCCRPregisters,allhavea lowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.
AstheCCRAandCCRPregistersareimplementedinthewayshowninthefollowingdiagramandaccessingtheseregisterpairsiscarriedoutinaspecificwayasdescribedabove,itisrecommendedtousethe“MOV”instructiontoaccesstheCCRAandCCRPlowbyteregisters,namedPTMALandPTMRPL,usingthefollowingaccessprocedures.AccessingtheCCRAorCCRPlowbyteregisterswithoutfollowingtheseaccessprocedureswillresultinunpredictablevalues.
Data Bus
8-bit Buffer
PTMDHPTMDL
PTMAHPTMAL
PTM Counter Register (Read only)
PTM CCRA Register (Read/Write)
PTMRPHPTMRPL
PTM CCRP Register (Read/Write)
Thefollowingstepsshowthereadandwriteprocedures:
• WritingDatatoCCRAorCCRP♦ Step1.WritedatatoLowBytePTMALorPTMRPL
– notethatheredataisonlywrittentothe8-bitbuffer.♦ Step2.WritedatatoHighBytePTMAHorPTMRPH
– heredata iswrittendirectly to thehighbyteregistersandsimultaneouslydata is latchedfromthe8-bitbuffertotheLowByteregisters.
• ReadingDatafromtheCounterRegistersandCCRAorCCRP♦ Step1.ReaddatafromtheHighBytePTMDH,PTMAHorPTMRPH
– heredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.
♦ Step2.ReaddatafromtheLowBytePTMDL,PTMALorPTMRPL– thisstepreadsdatafromthe8-bitbuffer.
Rev. 1.00 44 April 11, 2017 Rev. 1.00 45 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Periodic Type TM – PTMThePeriodicTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.ThePeriodicTMcanalsobecontrolledwithtwoexternalinputpinsandcandrivetwoexternaloutputpin.
PTM Core PTM Input Pin PTM Output Pin10-bit PTM PTCK, PTPI PTP, PTPB
fSYS
fSYS/4
fH/64fH/16
fSUB
PTCK
000
001
010
011
100
101
110
111
PTCK2~PTCK0
10-bit Count-up Counter
10-bit Comparator P
CCRP
b0~b9
b0~b9
10-bit Comparator A
PTONPTPAU
Comparator A Match
Comparator P Match
Counter Clear 01
Output Control
Polarity Control
Pin Control
PTP
PTOC
PTM1, PTM0PTIO1, PTIO0
PTMAF Interrupt
PTMPF Interrupt
PTPOL PAS0
CCRA
PTCCLR
EdgeDetector
PTPI
PTIO1, PTIO0
fSUB
10 Pin
Control
PTCAPTS
PTPB
PAS0
Periodic Type TM Block Diagram
Periodic TM OperationThesizeofPeriodicTMis10-bitwideanditscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPandCCRAcomparatorsare10-bitwidewhosevalueisrespectivelycomparedwithallcounterbits.
Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogramis toclear thecounterbychangingthePTONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aPTMinterruptsignalwillalsousuallybegenerated.ThePeriodicTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontroltheoutputpins.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.
Rev. 1.00 46 April 11, 2017 Rev. 1.00 47 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Periodic Type TM Register DescriptionOveralloperationofthePeriodicTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whiletworead/writeregisterpairsexisttostoretheinternal10-bitCCRAandCCRPvalue.Theremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodes.
Register Name
Bit
7 6 5 4 3 2 1 0PTMC0 PTPAU PTCK2 PTCK1 PTCK0 PTON — — —PTMC1 PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLRPTMDL D7 D6 D5 D4 D3 D2 D1 D0PTMDH — — — — — — D9 D8PTMAL D7 D6 D5 D4 D3 D2 D1 D0PTMAH — — — — — — D9 D8PTMRPL PTRP7 PTRP6 PTRP5 PTRP4 PTRP3 PTRP2 PTRP1 PTRP0PTMRPH — — — — — — PTRP9 PTRP8
Periodic TM Registers List
PTMC0 Register
Bit 7 6 5 4 3 2 1 0Name PTPAU PTCK2 PTCK1 PTCK0 PTON — — —R/W R/W R/W R/W R/W R/W — — —POR 0 0 0 0 0 — — —
Bit7 PTPAU:PTMCounterPausecontrol0:Run1:Pause
Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditionthePTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.
Bit6~4 PTCK2~PTCK0:SelectPTMCounterclock000:fSYS/4001:fSYS010:fH/16011:fH/64100:fSUB101:fSUB110:PTCKrisingedgeclock111:PTCKfallingedgeclock
ThesethreebitsareusedtoselecttheclocksourceforthePTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.
Rev. 1.00 46 April 11, 2017 Rev. 1.00 47 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Bit3 PTON:PTMCounterOn/Offcontrol0:Off1:On
Thisbitcontrolstheoverallon/offfunctionofthePTM.SettingthebithighenablesthecountertorunwhileclearingthebitdisablesthePTM.Clearingthisbit tozerowillstopthecounterfromcountingandturnoffthePTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IfthePTMisintheCompareMatchOutputModeorthePWMoutputModeorSinglePulseOutputMode,thenthePTMoutputpinwillberesettoitsinitialcondition,asspecifiedbythePTOCbit,whenthePTONbitchangesfromlowtohigh.
Bit2~0 Unimplemented,readas“0”
PTMC1 Register
Bit 7 6 5 4 3 2 1 0Name PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~6 PTM1~PTM0:SelectPTMOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMOutputModeorSinglePulseOutputMode11:Timer/CounterMode
ThesebitssetuptherequiredoperatingmodeforthePTM.ToensurereliableoperationthePTMshouldbeswitchedoffbeforeanychangesaremadetothePTM1andPTM0bits.IntheTimer/CounterMode,thePTMoutputpincontrolwillbedisabled.
Bit5~4 PTIO1~PTIO0:SelectPTMexternalpinPTPorPTPIfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput
PWMOutputMode/SinglePulseOutputMode00:PWMoutputinactivestate01:PWMoutputactivestate10:PWMoutput11:SinglePulseOutput
CaptureInputMode00:InputcaptureatrisingedgeofPTPIorPTCK01:InputcaptureatfallingedgeofPTPIorPTCK10:Inputcaptureatrising/fallingedgeofPTPIorPTCK11:Inputcapturedisabled
Timer/CounterModeUnused
ThesetwobitsareusedtodeterminehowthePTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodethePTMisrunning.
Rev. 1.00 48 April 11, 2017 Rev. 1.00 49 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
IntheCompareMatchOutputMode,thePTIO1andPTIO0bitsdeterminehowthePTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.ThePTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueofthePTMoutputpinshouldbesetupusingthePTOCbitinthePTMC1register.NotethattheoutputlevelrequestedbythePTIO1andPTIO0bitsmustbedifferentfromtheinitialvaluesetupusingthePTOCbitotherwisenochangewilloccuronthePTMoutputpinwhenacomparematchoccurs.AfterthePTMoutputpinchangesstate,itcanberesettoitsinitiallevelbychangingthelevelofthePTONbitfromlowtohigh.In thePWMMode, thePTIO1andPTIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePTMoutputfunctionismodifiedbychangingthesetwobits.ItisnecessarytoonlychangethevaluesofthePTIO1andPTIO0bitsonlyafterthePTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccurifthePTIO1andPTIO0bitsarechangedwhenthePTMisrunning.
Bit3 PTOC:PTMPTPOutputcontrolCompareMatchOutputMode0:Initiallow1:Initialhigh
PWMOutputMode/SinglePulseOutputMode0:Activelow1:Activehigh
This is theoutputcontrolbit for thePTMoutputpin. ItsoperationdependsuponwhetherPTMisbeingused in theCompareMatchOutputModeor in thePWMMode/SinglePulseOutputMode.IthasnoeffectifthePTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogiclevelofthePTMoutputpinbeforeacomparematchoccurs.In thePWMMode/SinglePulseOutputModeitdeterminesifthePWMsignalisactivehighoractivelow.
Bit2 PTPOL:PTMPTPOutputpolaritycontrol0:Non-inverted1:Inverted
ThisbitcontrolsthepolarityofthePTPoutputpin.WhenthebitissethighthePTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectifthePTMisintheTimer/CounterMode.
Bit1 PTCAPTS:PTMCaptureTriigerSourceselection0:FromPTPIpin1:FromPTCKpin
Bit0 PTCCLR:PTMCounterClearconditionselection0:ComparatorPmatch1:ComparatorAmatch
Thisbit isused toselect themethodwhichclears thecounter.Remember that thePeriodicTMcontains twocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear theinternalcounter.With thePTCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.ThePTCCLRbitisnotusedinthePWMOutput,SinglePulseOutputorCaptureInputMode.
Rev. 1.00 48 April 11, 2017 Rev. 1.00 49 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
PTMDL Register
Bit 7 6 5 4 3 2 1 0Name D7 D6 D5 D4 D3 D2 D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0
Bit7~0 PTMCounterLowByteRegisterbit7~bit0PTM10-bitCounterbit7~bit0
PTMDH Register
Bit 7 6 5 4 3 2 1 0Name — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0
Bit7~2 Unimplemented,readas“0”Bit1~0 PTMCounterHighByteRegisterbit1~bit0
PTM10-bitCounterbit9~bit8
PTMAL Register
Bit 7 6 5 4 3 2 1 0Name D7 D6 D5 D4 D3 D2 D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~0 PTMCCRALowByteRegisterbit7~bit0PTM10-bitCCRAbit7~bit0
PTMAH Register
Bit 7 6 5 4 3 2 1 0Name — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0
Bit7~2 Unimplemented,readas“0”Bit1~0 PTMCCRAHighByteRegisterbit1~bit0
PTM10-bitCCRAbit9~bit8
PTMRPL Register
Bit 7 6 5 4 3 2 1 0Name PTRP7 PTRP6 PTRP5 PTRP4 PTRP3 PTRP2 PTRP1 PTRP0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~0 PTMCCRPLowByteRegisterbit7~bit0PTM10-bitCCRPbit7~bit0
Rev. 1.00 50 April 11, 2017 Rev. 1.00 51 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
PTMRPH Register
Bit 7 6 5 4 3 2 1 0Name — — — — — — PTRP9 PTRP8R/W — — — — — — R/W R/WPOR — — — — — — 0 0
Bit7~2 Unimplemented,readas“0”Bit1~0 PTMCCRPHighByteRegisterbit1~bit0
PTM10-bitCCRPbit9~bit8
Periodic Type TM Operation ModesThePeriodicTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingthePTM1andPTM0bitsinthePTMC1register.
Compare Match Output ModeToselectthismode,bitsPTM1andPTM0inthePTMC1register,shouldbesetto00respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhenthePTCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothPTMAFandPTMPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.
IfthePTCCLRbitinthePTMC1registerishighthenthecounterwillbeclearedwhenacomparematchoccursfromComparatorA.However,hereonlythePTMAFinterruptrequestflagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenPTCCLRishighnoPTMPFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbesetto“0”.
Asthenameof themodesuggests,afteracomparisonismade, thePTMoutputpinwillchangestate.ThePTMoutputpinconditionhoweveronlychangesstatewhenaPTMAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.ThePTMPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectonthePTMoutputpin.ThewayinwhichthePTMoutputpinchangesstatearedeterminedbytheconditionofthePTIO1andPTIO0bitsinthePTMC1register.ThePTMoutputpincanbeselectedusingthePTIO1andPTIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.TheinitialconditionofthePTMoutputpin,whichissetupafterthePTONbitchangesfromlowtohigh,issetupusingthePTOCbit.Notethatif thePTIO1andPTIO0bitsarezerothennopinchangewilltakeplace.
Rev. 1.00 50 April 11, 2017 Rev. 1.00 51 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Counter Value
0x3FF
CCRP
CCRA
PTON
PTPAU
PTPOL
CCRP Int. Flag PTMPF
CCRA Int. Flag PTMAF
PTM O/P Pin
Time
CCRP=0
CCRP > 0
Counter overflowCCRP > 0
Counter cleared by CCRP value
Pause
Resume
Stop
Counter Restart
PTCCLR = 0; PTM [1:0] = 00
Output pin set to initial Level Low if PTOC=0
Output Toggle with PTMAF flag
Note PTIO [1:0] = 10 Active High Output selectHere PTIO [1:0] = 11
Toggle Output select
Output not affected by PTMAF flag. Remains High until reset by PTON bit
Output PinReset to Initial value
Output controlled by other pin-shared function
Output Invertswhen PTPOL is high
Compare Match Output Mode – PTCCLR=0Note:1.WithPTCCLR=0,aComparatorPmatchwillclearthecounter
2.ThePTMoutputpiniscontrolledonlybythePTMAFflag3.TheoutputpinisresettoitsinitialstatebyaPTONbitrisingedge
Rev. 1.00 52 April 11, 2017 Rev. 1.00 53 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Counter Value
0x3FF
CCRP
CCRA
PTON
PTPAU
PTPOL
CCRP Int. Flag PTMPF
CCRA Int. Flag PTMAF
PTM O/P Pin
Time
CCRA=0
CCRA = 0Counter overflowCCRA > 0 Counter cleared by CCRA value
Pause
Resume
Stop Counter Restart
PTCCLR = 1; PTM [1:0] = 00
Output pin set to initial Level Low if PTOC=0
Output Toggle with PTMAF flag
Note PTIO [1:0] = 10 Active High Output selectHere PTIO [1:0] = 11
Toggle Output select
Output not affected by PTMAF flag. Remains High until reset by PTON bit Output Pin
Reset to Initial valueOutput controlled by other pin-shared function
Output Invertswhen PTPOL is high
PTMPF not generated
No PTMAF flag generated on CCRA overflow
Output does not change
Compare Match Output Mode – PTCCLR=1Note:1.WithPTCCLR=1,aComparatorAmatchwillclearthecounter
2.ThePTMoutputpiniscontrolledonlybythePTMAFflag3.TheoutputpinisresettoitsinitialstatebyaPTONbitrisingedge4.APTMPFflagisnotgeneratedwhenPTCCLR=1
Rev. 1.00 52 April 11, 2017 Rev. 1.00 53 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Timer/Counter ModeToselectthismode,bitsPTM1andPTM0inthePTMC1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegenerating thesameinterrupt flags.Theexception is that in theTimer/CounterMode thePTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AsthePTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.
PWM Output ModeToselectthismode,bitsPTM1andPTM0inthePTMC1registershouldbesetto10respectivelyandalso thePTIO1andPTIO0bitsshouldbeset to10respectively.ThePWMfunctionwithinthePTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontrol,etc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleonthePTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.
AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.In thePWMmode, thePTCCLRbithasnoeffectas thePWMperiod.BothoftheCCRPandCCRAregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.
Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.ThePTOCbitinthePTMC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoPTIO1andPTIO0bitsareusedtoenablethePWMoutputortoforcethePTMoutputpintoafixedhighorlowlevel.ThePTPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.
• 10-bit PWM Output Mode, Edge-aligned Mode
CCRP 1~1023 0Period 1~1023 1024Duty CCRA
IffSYS=16MHz,TMclocksourceselectfSYS/4,CCRP=512andCCRA=128,
ThePTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%,
IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.
Rev. 1.00 54 April 11, 2017 Rev. 1.00 55 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Counter Value
CCRP
CCRA
PTON
PTPAU
PTPOL
CCRP Int. Flag PTMPF
CCRA Int. Flag PTMAF
PTM O/P Pin(PTOC=1)
Time
Counter cleared by CCRP
Pause Resume Counter Stop if PTON bit low
Counter Reset when PTON returns high
PTM [1:0] = 10
PWM Duty Cycle set by CCRA PWM resumes
operationOutput controlled by other pin-shared function Output Inverts
When PTPOL = 1PWM Period set by CCRP
PTM O/P Pin(PTOC=0)
PWM ModeNote:1.ThecounterisclearedbyCCRP
2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenPTIO[1:0]=00or014.ThePTCCLRbithasnoinfluenceonPWMoperation
Rev. 1.00 54 April 11, 2017 Rev. 1.00 55 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Single Pulse Output ModeToselectthismode,bitsPTM1andPTM0inthePTMC1registershouldbesetto10respectivelyandalsothePTIO1andPTIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseonthePTMoutputpin.
ThetriggerforthepulseoutputleadingedgeisalowtohightransitionofthePTONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,thePTONbitcanalsobemadetoautomaticallychangefromlowtohighusingtheexternalPTCKpin,whichwillinturninitiatetheSinglePulseoutput.WhenthePTONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.ThePTONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhenthePTONbit isclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.
HoweveracomparematchfromComparatorAwillalsoautomaticallyclearthePTONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaPTMinterrupt.Thecountercanonlyberesetback tozerowhen thePTONbitchangesfromlowtohighwhen thecounterrestarts.IntheSinglePulseModeCCRPisnotused.ThePTCCLRisnotusedinthisMode.
PTON bit0 → 1
S/W Command SET“PTON”
orPTCK Pin Transition
PTON bit1 → 0
CCRA Trailing Edge
S/W Command CLR“PTON”
orCCRA Compare Match
PTP Output Pin
Pulse Width = CCRA Value
CCRALeading Edge
Single Pulse Generation
Rev. 1.00 56 April 11, 2017 Rev. 1.00 57 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Counter Value
CCRP
CCRA
PTON
PTPAU
PTPOL
CCRP Int. Flag PTMPF
CCRA Int. Flag PTMAF
PTM O/P Pin(PTOC=1)
Time
Counter stopped by CCRA
PauseResume Counter Stops
by software
Counter Reset when PTON returns high
PTM [1:0] = 10 ; PTIO [1:0] = 11
Pulse Width set by CCRA
Output Invertswhen PTPOL = 1
No CCRP Interrupts generated
PTM O/P Pin(PTOC=0)
PTCK pin
Software Trigger
Cleared by CCRA match
PTCK pin Trigger
Auto. set by PTCK pin
Software Trigger
Software Clear
Software TriggerSoftware
Trigger
Single Pulse ModeNote:1.CounterstoppedbyCCRA
2.CCRPisnotused3.ThepulsetriggeredbythePTCKpinorbysettingthePTONbithigh4.APTCKpinactiveedgewillautomaticallysetthePTONbithigh5.IntheSinglePulseMode,PTIO[1:0]mustbesetto“11”andcannotbechanged.
Rev. 1.00 56 April 11, 2017 Rev. 1.00 57 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Capture Input ModeToselectthismodebitsPTM1andPTM0inthePTMC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedonthePTPIorPTCKpin,selectedbythePTCAPTSbitinthePTMC1register.Theinputpinactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingthePTIO1andPTIO0bitsinthePTMC1register.ThecounterisstartedwhenthePTONbitchangesfromlowtohighwhich is initiatedusing theapplicationprogram.
WhentherequirededgetransitionappearsonthePTPIorPTCKpinthepresentvalueinthecounterwillbelatchedintotheCCRAregistersandaPTMinterruptgenerated.IrrespectiveofwhateventsoccuronthePTPIorPTCKpinthecounterwillcontinuetofreerununtil thePTONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;inthiswaytheCCRPvaluecanbeusedtocontrolthemaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aPTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.ThePTIO1andPTIO0bitscanselecttheactivetriggeredgeonthePTPIorPTCKpintobearisingedge,fallingedgeorbothedgetypes.IfthePTIO1andPTIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensonthePTPIorPTCKpin,howeveritmustbenotedthatthecounterwillcontinuetorun.
AsthePTPIorPTCKpinispinsharedwithotherfunctions,caremustbetakenifthePTMisintheInputCaptureMode.Thisisbecauseifthepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.ThePTCCLR,PTOCandPTPOLbitsarenotusedinthisMode.
Rev. 1.00 58 April 11, 2017 Rev. 1.00 59 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Counter Value
YY
CCRP
PTON
PTPAU
CCRP Int. Flag PTMPF
CCRA Int. Flag PTMAF
CCRA Value
Time
Counter cleared by CCRP
PauseResume
Counter Reset
PTM [1:0] = 01
PTM capture pinPTPI or PTCK
XX
Counter Stop
PTIO [1:0] Value
XX YY XX YY
Active edge Active
edgeActive edge
00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disable Capture
Capture Input ModeNote:1.PTM[1:0]=01andactiveedgesetbythePTIO[1:0]bits
2.APTMCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.PTCCLRbitnotused4.Nooutputfunction–PTOCandPTPOLbitsarenotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.
Rev. 1.00 58 April 11, 2017 Rev. 1.00 59 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Shunt Regulator – for HT45F2020 onlyTheHT45F2020deviceincludesafullyintegratedshuntregulator.Thedeviceofferstheadvantagesofa fully internal shunt regulatorallowing it tobeusedwithawide rangeofexternalpowersupplyvoltageswiththesimpleadditionofanexternalresistorandcapacitor.Theshuntregulatorisacommonandsimpletypeofregulatorwhoseoutput isusedasthedevicepowersupply.It isconstructedofapowertransistorandavoltagefeedbackcircuit.Thepowertransistor,whoseoutputcurrentiscontrolledbyavoltagefeedbackcircuit, isusedtoshunttheextracurrenttomaintainaconstantregulatedvoltageonVDD.Thispowertransistorprovidesacurrentpathfromthedevicesupplyvoltagetoground.Anexternalresistor,RSER,shouldbeproperlyselectedtoseriallyconnectVDDtotheexternalpowersupply.TheshuntregulatormaynothavetheexpectedperformanceiftheRSERresistanceistoosmallortoolarge.AcapacitorisexternallyconnectedbetweenVDDandVSSpinstostabilisetheregulatedvoltage.Notethatexcessivepowerdissipationinformofheatduetotheshuntcurrentthroughthepowertransistorshouldbetakenintoconsiderationintheuserapplications.
RSERISUPPLY
VUNREG
VOUT
CBYPASS ISHUNT
VDD
Feedback
VSS
ILOADVDD
VSS
Shunt Regulator Block Diagram – HT45F2020
Examinationof the shunt regulatorblockdiagramwill reveal that the supplycurrentwillbedeterminedbythevalueoftheexternalRSERresistor.Forthisreasonselectionofthisresistorvalueisanimportantissue.ItisrecommendedthatthefollowingcriteriaareusedwhendecidingonthevalueofRSER.
ThevalueofRSERiscalculatedasfollows:
RSER=(VUNREG–VDD)/ISUPPLY;
WhereISUPPLY=ISHUNT(Max)≤whichshouldbelessthanorequalto80mA.
Themaximumvalueoftheloadcurrentiscalculatedasfollows:
ILOAD(Max)=ISHUNT(Max)×(VUNREG(Min)–VOUT1(Max))/(VUNREG(Max)−VOUT1(Min))−ISTATIC(Measured);
WhereVUNREG(Max),VOUT1(Max)=MaximumspecificationvalueforVUNREGandVOUT1respectively.
AndVUNREG(Min),VOUT1(Min)=MinimumspecificationvalueforVUNREGandVOUT1respectively.
Rev. 1.00 60 April 11, 2017 Rev. 1.00 61 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Sound Effect GeneratorThesoundeffectgeneratorisdesignedtobeusedinconjunctionwiththeHolteksuppliedSoundEffectGeneratorWizard,whichwillallowuserstoeasilyandrapidlydeveloptheirsoundgeneratorapplications.UsingtheHolteksuppliedSoundEffectGeneratorWizarddevelopmenttools,soundfileproductionalongwithprogrammingandplaysoundevaluationismadeintoaneasyandrapidprocess.Otherfunctionsincludea200mssoftchirpandfade-infeatures.Withitshighlyintegratedrangeof functionsanddevelopmentplatformHoltekhasgreatly simplified the soundeffectgenerationprocessandoneinwhichthehardwareonlyrequiresaminimumofexternalcomponents.
AnevaluationboardisavailablefromHoltektoenabletheeasydevelopmentofuserapplications.This isusedtogetherwiththeSoundEffectGeneratorWizardsoftwareandtheHolteke-Linktoenabletheusersoundfilestobeprogrammedintothedevice.Theevaluationboardalsoallowstheusertoimmediatelyplaythefilesthusallowingforrapidevaluationoftherequiredsoundeffects.Refertothe“SoundEffectGeneratorWizardUserGuide”formoredetailedinformation.
InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModulerequiresmicrocontrollerattention, theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontrollertodirectattentiontotheirrespectiveneeds.Thedeviceonlycontainsinternalinterruptsfunctions.TheinternalinterruptsaregeneratedbyvariousinternalfunctionssuchasTMs,andTimeBases.
Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshownintheaccompanyingtable.ThefirstistheINTC0~INTC1registerswhichsetuptheprimaryinterrupts,thesecondistheMFIregisterwhichsetuptheMulti-functioninterrupts.
Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran“E”forenable/disablebitor“F”forrequestflag.
Function Enable Bit Request FlagGlobal EMI —
Multi-function MFE MFFTime Base TBE TBF
PTMPTMPE PTMPFPTMAE PTMAF
Interrupt Register Bit Naming Conventions
Register Name
Bit
7 6 5 4 3 2 1 0INTC0 — — TBF — — TBE — EMIINTC1 — — — MFF — — — MFE
MFI — — PTMAF PTMPF — — PTMAE PTMPE
Interrupt Registers List
Rev. 1.00 60 April 11, 2017 Rev. 1.00 61 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
INTC0 Register
Bit 7 6 5 4 3 2 1 0Name — — TBF — — TBE — EMIR/W — — R/W — — R/W — R/WPOR — — 0 — — 0 — 0
Bit7~6 Unimplemented,readas“0”Bit5 TBF:TimeBaseinterruptrequestflag
0:Norequest1:Interruptrequest
Bit4~3 Unimplemented,readas“0”Bit2 TBE:TimeBaseinterruptcontrol
0:Disable1:Enable
Bit1 Unimplemented,readas“0”Bit0 EMI:Globalinterruptcontrol
0:Disable1:Enable
INTC1 Register
Bit 7 6 5 4 3 2 1 0Name — — — MFF — — — MFER/W — — — R/W — — — R/WPOR — — — 0 — — — 0
Bit7~5 Unimplemented,readas“0”Bit4 MFF:Multi-functioninterruptrequestflag
0:Norequest1:Interruptrequest
Bit3~1 Unimplemented,readas“0”Bit0 MFE:Multi-functioninterruptcontrol
0:Disable1:Enable
MFI Register
Bit 7 6 5 4 3 2 1 0Name — — PTMAF PTMPF — — PTMAE PTMPER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0
Bit7~6 Unimplemented,readas“0”Bit5 PTMAF:PTMComparatorAmatchinterruptrequestflag
0:Norequest1:Interruptrequest
Bit4 PTMPF:PTMComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest
Bit3~2 Unimplemented,readas“0”Bit1 PTMAE:PTMComparatorAmatchinterruptcontrol
0:Disable1:Enable
Rev. 1.00 62 April 11, 2017 Rev. 1.00 63 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Bit0 PTMPE:PTMComparatorPmatchinterruptcontrol0:Disable1:Enable
Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTMComparatorPorComparatorAmatchetc.,therelevantinterruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumptoitsrelevantvector,iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.
Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea“JMP”whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha“RETI”,whichretrieves theoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.
Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theAccompanyingdiagramswith theirorderofpriority.Some interrupt sourceshave theirownindividualvectorwhileothersshare thesamemulti-function interruptvector.Oncean interruptsubroutineisserviced,all theother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduringthis interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.
Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.
Time Base TBF TBE EMI 08H
EMI 10H
Interrupt Name
RequestFlags
Enable Bits
Master Enable Vector
EMI auto disabled in ISR
PriorityHigh
Low
PTM P PTMPF PTMPE
PTM A PTMAF PTMAEM. Funct MFF MFE
Interrupts contained within Multi-Function Interrupts
xxE Enable Bits
xxF Request Flag, auto reset in ISR
LegendxxF Request Flag, no auto reset in ISR
Interrupt Scheme
Rev. 1.00 62 April 11, 2017 Rev. 1.00 63 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Multi-function InterruptWithinthedevicethereisaMulti-functioninterrupt.Unliketheotherindependentinterrupts, theinterrupthasnoindependentsource,butratherareformedfromotherexistinginterruptsources,namelytheTMinterrupt.
AMulti-functioninterruptrequestwilltakeplacewhenanyoftheMulti-functioninterruptrequestflagMFFisset.TheMulti-functioninterruptflagwillbesetwhenanyoftheirincludedfunctionsgenerateaninterruptrequestflag.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,whentheMulti-functioninterruptisenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-functioninterruptoccurs,asubroutinecall tooneoftheMulti-functioninterruptvectorswill takeplace.Whentheinterruptisserviced,therelatedMulti-FunctionrequestflagwillbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.
However, itmustbenoted that, although theMulti-function Interrupt request flagswill beautomaticallyresetwhen the interrupt isserviced, therequest flagsfromtheoriginalsourceoftheMulti-function interruptwillnotbeautomatically resetandmustbemanually resetby theapplicationprogram.
Time Base InterruptThefunctionoftheTimeBaseInterruptistoprovideregulartimesignalintheformofaninternalinterrupt.Itiscontrolledbytheoverflowsignalfromitsinternaltimer.Whenthishappensitsinterruptrequest flag,TBF,willbeset.Toallowtheprogramtobranch to its respective interruptvectoraddresses, theglobal interruptenablebit,EMIandTimeBaseenablebit,TBE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecalltoitsrespectivevectorlocationwilltakeplace.Whentheinterruptisserviced,theinterruptrequestflag,TBF,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.
ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.Itsclocksource, fPSC,originates fromthe internalclocksourcefSYS, fSYS/4or fSUBand thenpassesthroughadivider,thedivisionratioofwhichisselectedbyprogrammingtheappropriatebitsintheTBCregistertoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcewhichinturncontrolstheTimeBaseinterruptperiodisselectedusingtheCLKSEL[1:0]inthePSCRregisterrespectively.
fSYS/4fSYS
fSUB
MUX
Prescaler
CLKSEL[1:0]
fPSC fPSC/28 ~ fPSC/215 MUX
TB[2:0]
Time Base Interrupt
TBON
Time Base Interrupt
PSCR Register
Bit 7 6 5 4 3 2 1 0Name — — — — — — CLKSEL1 CLKSEL0R/W — — — — — — R/W R/WPOR — — — — — — 0 0
Bit7~2 Unimplemented,readas“0”Bit1~0 CLKSEL1~CLKSEL0:Prescalerclocksourceselection
00:fSYS01:fSYS/41x:fSUB
Rev. 1.00 64 April 11, 2017 Rev. 1.00 65 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
TBC Register
Bit 7 6 5 4 3 2 1 0Name TBON — — — — TB2 TB1 TB0R/W R/W — — — — R/W R/W R/WPOR 0 — — — — 0 0 0
Bit7 TBON:TimeBaseEnableControl0:Disable1:Enable
Bit6~3 Unimplemented,readas“0”Bit2~0 TB2~TB0:TimeBasetime-outperiodselection
000:28/fPSC001:29/fPSC010:210/fPSC011:211/fPSC100:212/fPSC101:213/fPSC110:214/fPSC111:215/fPSC
Timer Module Interrupts ThePTMhas two interruptswhicharebothcontainedwithin theMulti-functionInterrupt.ForthePTMthereare twointerruptrequestflagsPTMPFandPTMAFandtwoenablebitsPTMPEandPTMAE.APTMinterruptrequestwilltakeplacewhenanyofthePTMrequestflagsisset,asituationwhichoccurswhenaPTMcomparatorPorcomparatorAmatchsituationhappens.
Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtherespectivePTMInterruptenablebit,andtheassociatedMulti-functioninterruptenablebit,MFF,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaPTMcomparatormatchsituationoccurs,asubroutinecalltotherelevantPTMInterruptvectorlocations,will takeplace.WhenthePTMinterrupt isserviced, theEMIbitwillbeautomaticallyclearedtodisableother interrupts,howeveronlytherelatedMFFflagwillbeautomaticallycleared.AsthePTMinterruptrequestflagswillnotbeautomaticallycleared, theyhavetobeclearedbytheapplicationprogram.
Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.
Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.
Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptservice routine is executed, asonly theMulti-function interrupt request flags,MFF,willbeautomaticallycleared, the individual request flag for the functionneeds tobeclearedby theapplicationprogram.
Rev. 1.00 64 April 11, 2017 Rev. 1.00 65 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
It isrecommendedthatprogramsdonotusethe“CALL”instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.
Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.
AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.
Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.
Application Circuits
Direct Driving – HT45F2020
VDD
VSS
PTPPTPB
IO1
12V
100μF IO2
150Ω/2W 200Ω/0.5WSpeaker
Note:ThePTPandPTPBsignalsarethePTMcomplementaryoutputs.
Rev. 1.00 66 April 11, 2017 Rev. 1.00 67 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Single-End Driving – HT45F2020
VDD
VSS
PTPPTPB
IO2IO1
100Ω
12V
10μF
750Ω/0.25W
8Ω/15W Speaker
47kΩ
Note:ThePTPandPTPBsignalsarethePTMcomplementaryoutputs.
Push-Pull Driving – HT45F2020
820ΩVDD
VSS
PTP
PTPB
IO2IO1
10μF
8Ω/15WSpeaker
820Ω
470Ω 470Ω
47kΩ47kΩ
220Ω220Ω
12V
430Ω/0.25W
Note:ThePTPandPTPBsignalsarethePTMcomplementaryoutputs.
Rev. 1.00 66 April 11, 2017 Rev. 1.00 67 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Direct Driving – HT45F2022
VDD
VSS
PTPPTPB
IO1
5V
100μF IO2
200Ω/0.5WSpeaker
Note:ThePTPandPTPBsignalsarethePTMcomplementaryoutputs.
Single-End Driving – HT45F2022
VDD
VSS
PTPPTPB
IO2IO1
100Ω
10μF
8Ω/15W Speaker
47kΩ
5V
Note:ThePTPandPTPBsignalsarethePTMcomplementaryoutputs.
Rev. 1.00 68 April 11, 2017 Rev. 1.00 69 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Push-Pull Driving – HT45F2022
820ΩVDD
VSS
PTP
PTPB
IO2IO1
10μF
8Ω/15WSpeaker
820Ω
470Ω 470Ω
47kΩ47kΩ
220Ω220Ω
5V
Note:ThePTPandPTPBsignalsarethePTMcomplementaryoutputs.
Rev. 1.00 68 April 11, 2017 Rev. 1.00 69 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Instruction Set
IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.
Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.
Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe“CLRPCL”or“MOVPCL,A”.Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.
Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofseveralkindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsistoreceivedatafromtheinputportsandtransferdatatotheoutputports.
Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandless than0forsubtraction.Theincrementanddecrement instructionssuchasINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.
Rev. 1.00 70 April 11, 2017 Rev. 1.00 71 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.
Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction“RET”inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.
Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe“SET[m].i”or“CLR[m].i”instructionsrespectively.Thefeatureremovestheneedforprogrammerstofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.
Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.
Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe“HALT”instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.
Rev. 1.00 70 April 11, 2017 Rev. 1.00 71 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.
Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress
Mnemonic Description Cycles Flag AffectedArithmeticADD A,[m] Add Data Memory to ACC 1 Z, C, AC, OVADDM A,[m] Add ACC to Data Memory 1Note Z, C, AC, OVADD A,x Add immediate data to ACC 1 Z, C, AC, OVADC A,[m] Add Data Memory to ACC with Carry 1 Z, C, AC, OVADCM A,[m] Add ACC to Data memory with Carry 1Note Z, C, AC, OVSUB A,x Subtract immediate data from the ACC 1 Z, C, AC, OVSUB A,[m] Subtract Data Memory from ACC 1 Z, C, AC, OVSUBM A,[m] Subtract Data Memory from ACC with result in Data Memory 1Note Z, C, AC, OVSBC A,[m] Subtract Data Memory from ACC with Carry 1 Z, C, AC, OVSBCM A,[m] Subtract Data Memory from ACC with Carry, result in Data Memory 1Note Z, C, AC, OVDAA [m] Decimal adjust ACC for Addition with result in Data Memory 1Note CLogic OperationAND A,[m] Logical AND Data Memory to ACC 1 ZOR A,[m] Logical OR Data Memory to ACC 1 ZXOR A,[m] Logical XOR Data Memory to ACC 1 ZANDM A,[m] Logical AND ACC to Data Memory 1Note ZORM A,[m] Logical OR ACC to Data Memory 1Note ZXORM A,[m] Logical XOR ACC to Data Memory 1Note ZAND A,x Logical AND immediate Data to ACC 1 ZOR A,x Logical OR immediate Data to ACC 1 ZXOR A,x Logical XOR immediate Data to ACC 1 ZCPL [m] Complement Data Memory 1Note ZCPLA [m] Complement Data Memory with result in ACC 1 ZIncrement & DecrementINCA [m] Increment Data Memory with result in ACC 1 ZINC [m] Increment Data Memory 1Note ZDECA [m] Decrement Data Memory with result in ACC 1 ZDEC [m] Decrement Data Memory 1Note ZRotateRRA [m] Rotate Data Memory right with result in ACC 1 NoneRR [m] Rotate Data Memory right 1Note NoneRRCA [m] Rotate Data Memory right through Carry with result in ACC 1 CRRC [m] Rotate Data Memory right through Carry 1Note CRLA [m] Rotate Data Memory left with result in ACC 1 NoneRL [m] Rotate Data Memory left 1Note NoneRLCA [m] Rotate Data Memory left through Carry with result in ACC 1 CRLC [m] Rotate Data Memory left through Carry 1Note C
Rev. 1.00 72 April 11, 2017 Rev. 1.00 73 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Mnemonic Description Cycles Flag AffectedData MoveMOV A,[m] Move Data Memory to ACC 1 NoneMOV [m],A Move ACC to Data Memory 1Note NoneMOV A,x Move immediate data to ACC 1 NoneBit OperationCLR [m].i Clear bit of Data Memory 1Note NoneSET [m].i Set bit of Data Memory 1Note NoneBranch OperationJMP addr Jump unconditionally 2 NoneSZ [m] Skip if Data Memory is zero 1Note NoneSZA [m] Skip if Data Memory is zero with data movement to ACC 1Note NoneSZ [m].i Skip if bit i of Data Memory is zero 1Note NoneSNZ [m].i Skip if bit i of Data Memory is not zero 1Note NoneSIZ [m] Skip if increment Data Memory is zero 1Note NoneSDZ [m] Skip if decrement Data Memory is zero 1Note NoneSIZA [m] Skip if increment Data Memory is zero with result in ACC 1Note NoneSDZA [m] Skip if decrement Data Memory is zero with result in ACC 1Note NoneCALL addr Subroutine call 2 NoneRET Return from subroutine 2 NoneRET A,x Return from subroutine and load immediate data to ACC 2 NoneRETI Return from interrupt 2 NoneTable Read OperationTABRD [m] Read table (specific page) to TBLH and Data Memory 2Note NoneTABRDC [m] Read table (current page) to TBLH and Data Memory 2Note NoneTABRDL [m] Read table (last page) to TBLH and Data Memory 2Note NoneMiscellaneousNOP No operation 1 NoneCLR [m] Clear Data Memory 1Note NoneSET [m] Set Data Memory 1Note NoneCLR WDT Clear Watchdog Timer 1 TO, PDFCLR WDT1 Pre-clear Watchdog Timer 1 TO, PDFCLR WDT2 Pre-clear Watchdog Timer 1 TO, PDFSWAP [m] Swap nibbles of Data Memory 1Note NoneSWAPA [m] Swap nibbles of Data Memory with result in ACC 1 NoneHALT Enter power down mode 1 TO, PDF
Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.
2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.For the“CLRWDT1”and“CLRWDT2”instructionstheTOandPDFflagsmaybeaffectedbytheexecution status.TheTOandPDFflagsareclearedafterboth“CLRWDT1”and“CLRWDT2”instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.
Rev. 1.00 72 April 11, 2017 Rev. 1.00 73 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Instruction Definition
ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C
ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C
ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C
ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C
ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C
AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z
AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z
ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z
Rev. 1.00 74 April 11, 2017 Rev. 1.00 75 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None
CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None
CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None
CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF
CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF
CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF
CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z
Rev. 1.00 74 April 11, 2017 Rev. 1.00 75 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z
DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C
DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z
DECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z
HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF
INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z
INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z
Rev. 1.00 76 April 11, 2017 Rev. 1.00 77 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None
MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None
MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None
MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None
NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None
OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z
OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z
ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z
RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None
Rev. 1.00 76 April 11, 2017 Rev. 1.00 77 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None
RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None
RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None
RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None
RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C
RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C
RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None
Rev. 1.00 78 April 11, 2017 Rev. 1.00 79 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryisrotatedrightby1bitwithbit0rotatedintobit7. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None
RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C
RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C
SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C
SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C
SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None
Rev. 1.00 78 April 11, 2017 Rev. 1.00 79 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None
SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None
SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None
SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None
SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None
SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None
SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C
Rev. 1.00 80 April 11, 2017 Rev. 1.00 81 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C
SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C
SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None
SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None
SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None
SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None
SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None
Rev. 1.00 80 April 11, 2017 Rev. 1.00 81 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z
XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z
XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z
Rev. 1.00 82 April 11, 2017 Rev. 1.00 83 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Package Information
Note that thepackage informationprovidedhere is for consultationpurposesonly.As thisinformationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsiteforthelatestversionofthePackage/CartonInformation.
Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.
• FurtherPackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)
• PackingMeterialsInformation
• Cartoninformation
Rev. 1.00 82 April 11, 2017 Rev. 1.00 83 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
8-pin SOP (150mil) Outline Dimensions
SymbolDimensions in inch
Min. Nom. Max.A — 0.236 BSC —B — 0.154 BSC —C 0.012 — 0.020C′ — 0.193 BSC —D — — 0.069E — 0.050 BSC —F 0.004 — 0.010G 0.016 — 0.050H 0.004 — 0.010α 0° — 8°
SymbolDimensions in mm
Min. Nom. Max.A — 6.00 BSC —B — 3.90 BSC —C 0.31 — 0.51C′ — 4.90 BSC —D — — 1.75E — 1.27 BSC —F 0.10 — 0.25G 0.40 — 1.27H 0.10 — 0.25α 0° — 8°
Rev. 1.00 84 April 11, 2017 Rev. 1.00 85 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
6-pin SOT23-6 Outline Dimensions
H
SymbolDimensions in inch
Min. Nom. Max.A — — 0.057
A1 — — 0.006A2 0.035 0.045 0.051b 0.012 — 0.020C 0.003 — 0.009D — 0.114 BSC —E — 0.063 BSC —e — 0.037 BSC —
e1 — 0.075 BSC —H — 0.110 BSC —L1 — 0.024 BSC —θ 0° — 8°
SymbolDimensions in mm
Min. Nom. Max.A — — 1.45
A1 — — 0.15A2 0.90 1.15 1.30b 0.30 — 0.50C 0.08 — 0.22D — 2.90 BSC —E — 1.60 BSC —e — 0.95 BSC —
e1 — 1.90 BSC —H — 2.80 BSC —L1 — 0.60 BSC —θ 0° — 8°
Rev. 1.00 84 April 11, 2017 Rev. 1.00 85 April 11, 2017
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
HT45F2020/HT45F2022Sound Effect Generator Flash MCU
Copyright© 2017 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com/en/.