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SDC merge advantage using FISHTAIL toolSDC merge advantage using FISHTAIL tool
2010 Oct 20thHiroshi KuharaDevelopment Department 1STARC (Semiconductor Technology Academic Research Center)
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AgendaAgendaIntroduction to STARCPurpose of Multi-Mode SDCExample of Multi-Mode SDC application
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Introduction to STARCIntroduction to STARC
Process Friendly Design Technologies
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Consolidation(Development site)
Consolidate resources
Innovation
Spread Results
High level design
Mixed signal designProcess friendly design
Shuttle serviceTest and fault diagnostics
Standardization(Platform)
AdvantageReduce design costShorten design TAT
DisadvantageInsufficient performance
Advantage >> Disadvantage
Focus(Design Methodology)
Infrastructure for innovation• Early and certainrealization of new ideas
STARCSTARC ActivitiesActivities
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STARCAD-CEL RoadmapSTARCAD-CEL RoadmapSTARCAD-CEL(One Step Ahead of DFM)Process Friendly Design development
V4.0Holistic low power
Phase 1Toward 45nm design technology
2011
V0.565nm basic flow
V1.0Variation effect
V1.5Ultra low power
V2.0Yield effect
V3.0Lithography effect
V5.0
2009 20102007 20082006
V2.545nm realization
V3.5Thermal effect
V4.5Electrical Quality
Phase 2Toward 32nm design technology
Holistic variation effect
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Purpose of Multi-Mode SDCPurpose of Multi-Mode SDC
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What is Multi-mode SDC ?What is Multi-mode SDC ?Multi-mode SDC is
SDC constraints for multiple operational modes in a single designAn operational mode is each situation where the design operates ata different frequency, function, timing, library, etc.Example: Test mode, function (mission, standby) mode etc.
Almost all SoC designs have multiple operational modes and eachmode has a corresponding SDC.
Multi-mode SDC merge is ?The merging of the multiple operational SDC modes into a single SDC.
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Issues of designing with Multi-mode SDC (1)Issues of designing with Multi-mode SDC (1)Increase in number of SDC files
Increase of operational modes due to complex designIncrease of corners due to deep sub micron effects-> operational modes x corners = increase in the number of scenarios
# SDC for Slow Modecreate_clock –period 10 CLK1・・・
# SDC for Fast Modecreate_clock –period 20 CLK1---
P=SS V=L T=H W=Cmin
P=FF V=H T=L W=Cmin
8 mod
es
9 cor
ners
Implementation Tool
modes x corners
---
---Spec
Test・mode
Standby・mode
Slow mode
Fast mode
Scenarios=72
Longer TAT More memory
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Reduce runtime by merging multiple SDC files for each mode into 1 mode
# SDC for Slow Modecreate_clock –period 10 CLK1・・・
# SDC for Fast Modecreate_clock –period 20 CLK1---
P=SS V=L T=H W=Cmin
P=FF V=H T=L W=Cmin
Implementation Tool
mode x corners
---
---
Scenarios = 9
# merge SDCcreate_clock –period 20 CLK1---
1 mod
e
SDCmerge
8 mod
es
9 cor
ners
Issues of designing with Multi-mode SDC (2)Issues of designing with Multi-mode SDC (2)
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Requirements for multi-mode SDC mergeRequirements for multi-mode SDC mergeGenerates the equivalent constraints for the prior SDC files
No loss of constraints compared with original SDCsNot optimistic compared with original SDCsNot too pessimistic compared with original SDCs
Example of inappropriate SDC merge
mode1
mode2
merged
merged
Fast/Slow
slow
loss of constraint
optimistic
SDC merge
SDC merge
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Multi-mode SDC merge with FishTail toolMulti-mode SDC merge with FishTail toolExample of multi-mode SDC merge using Focus (FishTail)
Example of SDC merge by Focus
CK
FF3
FF1
FF2
SEL
0
1
# mode1.sdccreate_clock –period 10 [get_ports CK]set_case_analyssis 0 [get_ports SEL]
# mode2.sdccreate_clock –period 10 [get_ports CK]set_case_analyssis 1 [get_ports SEL]
MUX # merged.sdccreate_clock –period 10 [get_ports CK]set_case_analysis 0 [get_ports SEL]set_case_analysis 1 [get_ports SEL]set_false_path [ get_ports SEL ]
Focus
Reduction of case analysis
Avoid unnecessary timing check due to the reduction of case analysis (Add False Path Statement)
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Example of Multi-Mode SDC applicationExample of Multi-Mode SDC application
TAT reduction using Focus
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Focus example (1)Focus example (1)Design flow
Execute and compare placerTAT with Pre&Post SDC merge
Data used
Circuit size:330K gatesOperational modes:8 modes
ModeSDCs
MergedSDCNetlist
Compareruntime
Results ResultsCompareQoR
Evaluation flow (1)
Focus
Placement Placement
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Focus example (1)Focus example (1)Comparison of runtime
Around 20% improvementvs. Multi-mode placement
CPU time
SDCmerge
Multi-mode
Placement runtime
21% reduction
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Focus example (1) Focus example (1) Comparison of QoR
Almost same area vs.Multi-mode
Almost same timingCompared by running STAwith the original SDC files Multi-mode SDC merge
SETUP(WNS) -0.10 -0.08SETUP(TNS) -0.58 -0.39
Slack [nsec]
area
SDCmerge
Multi-mode
Area
Timing
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Focus example (1) Focus example (1) Equivalence verification
Check equivalence withPre&Post SDC merge byrunning Confirm/Refocus
ModeSDCs
MergedSDCNetlist
Equivalence check flow
Refocus
Confirm Confirm
Report(HTML)
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Focus example (2) Focus example (2) Evaluation flow
Compare all stages of Place&Routing with Pre&Post ofSDC Merge
Data usedCircuit size:1.2M gatesOperational modes:9 modes
CompareRuntime &
Memory usage
ComparisonQoR
Evaluation flow (2)
ModeSDCs
MergedSDCNETLIST
P&R result P&R result
Focus
P&R P&R
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CPU time
SDCmerge
Multi-mode
P&R runtime
Focus example (2) Focus example (2) Comparison of runtime, memory usage
About 60% runtimereduction vs. Multi-mode
Almost same Memoryusage as Multi-mode
About 60% reduction
Memory usage
SDC merge
Multi-mode
Peak memory during P&R
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Focus example (2)Focus example (2)Comparison of QoR
Almost same area vs.Multi-mode
Almost same timing Compared by running STAwith original SDC files
Multi-mode SDC mergeSETUP(WNS) -0.02 -0.01SETUP(TNS) -0.14 -0.01HOLD(WNS) -0.68 -0.69HOLD(TNS) -196.83 -179.49
Slack [nsec]
Timing
area
SDCmerge
Multi-mode
Area
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Advantage of applying FocusAdvantage of applying FocusReducing P&R runtime by applying Focus
P&R runtime is really reduced by making smaller number of scenarios
More effective with increasing SDC modes
Converged to 1 equivalent SDC file from multiple input SDC files
Possible to verify merge results using Confirm/Refocus
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IssuesIssuesFocus runtime
Total runtime benefit reduceddue to SDC merge overhead
Confirmed the speed updue to parallel processing(New version already supports this)
Currently verifyingthe result
MergedSDC
SDCs
Mode 1
Mode 2
Mode n
Merge all modeMerged
SDC
SDCs
Mode 1 Mode 2 Mode n
Merge all mode
・・・
TAT reduction due to parallel processing(Image)
0 2 4 6 8 10CPU time [hour]
Parallel
Single
SDC merge runtime
Focu
sflo
w
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IssuesIssuesPseudo error during SDC equivalence check with Pre&Post SDC merge
Difficulty of debugging huge circuits if many pseudo errors occur
CK
FF3
FF1
FF2
SEL
0
1
Inconsistent error at MUX(No error at case analysis)
MUX
Example of pseudo error with equivalence verification
# mode1.sdccreate_clock –period 10 [get_ports CK]set_case_analyssis 0 [get_ports SEL]# mode2.sdc
create_clock –period 10 [get_ports CK]set_case_analyssis 1 [get_ports SEL]
# merged.sdccreate_clock –period 10 [get_ports CK]set_case_analysis 0 [get_ports SEL]set_case_analysis 1 [get_ports SEL]set_false_path [ get_ports SEL ]
Confirm/Refocus
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IssuesIssuesConstraint ECO
How to cope with modification/additionto SDC due to changing specification or constraint modification during design
Incremental SDC merge preservesTAT improvement
Detail placement
Placement optimization
CTS
Optimize after CTS
Routing
Optimize after Routing
SDCs
MergedSDC
P&R
flow
ECODebug
Feedback loop for modification/addition to SDC
Focus Re execute fromSDC merge
(Incremental)
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AcknowledgmentsAcknowledgmentsWe would like to thank the FishTail staff for all of their support.
STARC looks forward to more innovations to increase designer productivity from FishTail.